PartDevices > EFM32JG1B200F256GM48
Macros |
|
| #define | __CM3_REV 0x0201U |
| #define | _EFM32_JADE_FAMILY 1 |
| #define | _EFM_DEVICE |
| #define | _SILICON_LABS_32B_PLATFORM 2 |
| #define | _SILICON_LABS_32B_PLATFORM_2 |
| #define | _SILICON_LABS_32B_PLATFORM_2_GEN 1 |
| #define | _SILICON_LABS_32B_PLATFORM_2_GEN_1 |
| #define | _SILICON_LABS_32B_SERIES 1 |
| #define | _SILICON_LABS_32B_SERIES_1 |
| #define | _SILICON_LABS_32B_SERIES_1_CONFIG 1 |
| #define | _SILICON_LABS_32B_SERIES_1_CONFIG_1 |
| #define | _SILICON_LABS_GECKO_INTERNAL_SDID 80 |
| #define | _SILICON_LABS_GECKO_INTERNAL_SDID_80 |
| #define | ACMP_COUNT 2 |
| #define | ACMP_PRESENT |
| #define | ADC_COUNT 1 |
| #define | ADC_PRESENT |
| #define | AFACHAN_MAX 61U |
| #define | AFCHAN_MAX 72U |
| #define | AFCHANLOC_MAX 32U |
| #define | BITBAND_PER_BASE ((uint32_t) 0x42000000UL) |
| #define | BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) |
| #define | BOOTLOADER_COUNT 1 |
| #define | BOOTLOADER_PRESENT |
| #define | CMU_COUNT 1 |
| #define | CMU_PRESENT |
| #define | CRYOTIMER_COUNT 1 |
| #define | CRYOTIMER_PRESENT |
| #define | CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) |
| #define | CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) |
| #define | CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) |
| #define | CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) |
| #define | CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO_COUNT 1 |
| #define | CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) |
| #define | CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) |
| #define | CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO_PRESENT |
| #define | DCDC_COUNT 1 |
| #define | DCDC_PRESENT |
| #define | DMA_CHAN_COUNT 8 |
| #define | EMU_COUNT 1 |
| #define | EMU_PRESENT |
| #define | EXT_IRQ_COUNT 34 |
| #define | FLASH_BASE (0x00000000UL) |
| #define | FLASH_MEM_BASE ((uint32_t) 0x00000000UL) |
| #define | FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) |
| #define | FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) |
| #define | FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) |
| #define | FLASH_PAGE_SIZE 2048U |
| #define | FLASH_SIZE (0x00040000UL) |
| #define | GPCRC_COUNT 1 |
| #define | GPCRC_PRESENT |
| #define | GPIO_COUNT 1 |
| #define | GPIO_PRESENT |
| #define | I2C_COUNT 1 |
| #define | I2C_PRESENT |
| #define | IDAC_COUNT 1 |
| #define | IDAC_PRESENT |
| #define | LDMA_COUNT 1 |
| #define | LDMA_PRESENT |
| #define | LETIMER_COUNT 1 |
| #define | LETIMER_PRESENT |
| #define | LEUART_COUNT 1 |
| #define | LEUART_PRESENT |
| #define | MSC_COUNT 1 |
| #define | MSC_PRESENT |
| #define | PART_NUMBER "EFM32JG1B200F256GM48" |
| #define | PCNT_COUNT 1 |
| #define | PCNT_PRESENT |
| #define | PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) |
| #define | PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) |
| #define | PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) |
| #define | PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) |
| #define | PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) |
| #define | PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) |
| #define | PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) |
| #define | PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) |
| #define | PER_MEM_BASE ((uint32_t) 0x40000000UL) |
| #define | PER_MEM_BITS ((uint32_t) 0x00000014UL) |
| #define | PER_MEM_END ((uint32_t) 0x400E7FFFUL) |
| #define | PER_MEM_SIZE ((uint32_t) 0xE8000UL) |
| #define | PRS_CHAN_COUNT 12 |
| #define | PRS_COUNT 1 |
| #define | PRS_PRESENT |
| #define | RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) |
| #define | RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) |
| #define | RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) |
| #define | RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) |
| #define | RAM_MEM_BASE ((uint32_t) 0x20000000UL) |
| #define | RAM_MEM_BITS ((uint32_t) 0x0000000FUL) |
| #define | RAM_MEM_END ((uint32_t) 0x20007BFFUL) |
| #define | RAM_MEM_SIZE ((uint32_t) 0x7C00UL) |
| #define | RMU_COUNT 1 |
| #define | RMU_PRESENT |
| #define | RTCC_COUNT 1 |
| #define | RTCC_PRESENT |
| #define | SRAM_BASE (0x20000000UL) |
| #define | SRAM_SIZE (0x00008000UL) |
| #define | TIMER_COUNT 2 |
| #define | TIMER_PRESENT |
| #define | USART_COUNT 2 |
| #define | USART_PRESENT |
| #define | WDOG_COUNT 1 |
| #define | WDOG_PRESENT |
Macro Definition Documentation
| #define __CM3_REV 0x0201U |
Cortex-M3 Core revision r2p1
Definition at line
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| #define _EFM32_JADE_FAMILY 1 |
Part family JADE Gecko MCU Family
Definition at line
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| #define _EFM_DEVICE |
Silicon Labs EFM-type microcontroller
Definition at line
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| #define _SILICON_LABS_32B_PLATFORM 2 |
-
Deprecated: - Silicon Labs platform name
Definition at line
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| #define _SILICON_LABS_32B_PLATFORM_2 |
-
Deprecated: - Silicon Labs platform name
Definition at line
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| #define _SILICON_LABS_32B_PLATFORM_2_GEN 1 |
-
Deprecated: - Platform 2, generation 1
Definition at line
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| #define _SILICON_LABS_32B_PLATFORM_2_GEN_1 |
-
Deprecated: - Platform 2, generation 1
Definition at line
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| #define _SILICON_LABS_32B_SERIES 1 |
Silicon Labs series number
Definition at line
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| #define _SILICON_LABS_32B_SERIES_1 |
Silicon Labs series number
Definition at line
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| #define _SILICON_LABS_32B_SERIES_1_CONFIG 1 |
Series 1, Configuration 1
Definition at line
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| #define _SILICON_LABS_32B_SERIES_1_CONFIG_1 |
Series 1, Configuration 1
Definition at line
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| #define _SILICON_LABS_GECKO_INTERNAL_SDID 80 |
Silicon Labs internal use only, may change any time
Definition at line
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| #define _SILICON_LABS_GECKO_INTERNAL_SDID_80 |
Silicon Labs internal use only, may change any time
Definition at line
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| #define ACMP_COUNT 2 |
2 ACMPs available
Definition at line
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| #define ACMP_PRESENT |
ACMP is available in this part
Definition at line
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| #define ADC_COUNT 1 |
1 ADCs available
Definition at line
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| #define ADC_PRESENT |
ADC is available in this part
Definition at line
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| #define AFACHAN_MAX 61U |
Analog AF channels
Definition at line
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| #define AFCHAN_MAX 72U |
AF channels connect the different on-chip peripherals with the af-mux
Definition at line
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| #define AFCHANLOC_MAX 32U |
AF channel maximum location number
Definition at line
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Referenced by DBG_SWOEnable() , and GPIO_DbgLocationSet() .
| #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) |
Bit banding area Peripheral Address Space bit-band area
Definition at line
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of file
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Referenced by BUS_RegBitRead() , and BUS_RegBitWrite() .
| #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) |
SRAM Address Space bit-band area
Definition at line
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Referenced by BUS_RamBitRead() , and BUS_RamBitWrite() .
| #define BOOTLOADER_COUNT 1 |
1 BOOTLOADER available
Definition at line
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| #define BOOTLOADER_PRESENT |
BOOTLOADER is available in this part
Definition at line
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| #define CMU_COUNT 1 |
1 CMU available
Definition at line
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| #define CMU_PRESENT |
CMU is available in this part
Definition at line
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| #define CRYOTIMER_COUNT 1 |
1 CRYOTIMER available
Definition at line
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| #define CRYOTIMER_PRESENT |
CRYOTIMER is available in this part
Definition at line
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of file
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| #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) |
CRYPTO_BITCLR base address
Definition at line
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of file
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| #define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO_BITCLR used bits
Definition at line
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of file
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| #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) |
CRYPTO_BITCLR end address
Definition at line
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of file
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| #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO_BITCLR available address space
Definition at line
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of file
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| #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) |
CRYPTO_BITSET base address
Definition at line
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| #define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO_BITSET used bits
Definition at line
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of file
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| #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) |
CRYPTO_BITSET end address
Definition at line
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of file
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| #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO_BITSET available address space
Definition at line
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| #define CRYPTO_COUNT 1 |
1 CRYPTO available
Definition at line
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| #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) |
CRYPTO base address
Definition at line
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| #define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO used bits
Definition at line
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of file
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| #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) |
CRYPTO end address
Definition at line
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of file
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| #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO available address space
Definition at line
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| #define CRYPTO_PRESENT |
CRYPTO is available in this part
Definition at line
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| #define DCDC_COUNT 1 |
1 DCDC available
Definition at line
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| #define DCDC_PRESENT |
DCDC is available in this part
Definition at line
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of file
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| #define DMA_CHAN_COUNT 8 |
Number of DMA channels
Definition at line
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of file
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Referenced by NANDFLASH_Init() .
| #define EMU_COUNT 1 |
1 EMU available
Definition at line
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| #define EMU_PRESENT |
EMU is available in this part
Definition at line
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of file
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| #define EXT_IRQ_COUNT 34 |
Number of External (NVIC) interrupts
Definition at line
186
of file
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Referenced by CORE_GetNvicRamTableHandler() , CORE_IrqIsBlocked() , CORE_NvicIRQDisabled() , CORE_NvicMaskClearIRQ() , CORE_NvicMaskSetIRQ() , and CORE_SetNvicRamTableHandler() .
| #define FLASH_BASE (0x00000000UL) |
Flash and SRAM limits for EFM32JG1B200F256GM48 Flash Base Address
Definition at line
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| #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) |
Memory Base addresses and limits FLASH base address
Definition at line
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| #define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) |
FLASH used bits
Definition at line
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of file
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| #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) |
FLASH end address
Definition at line
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of file
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| #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) |
FLASH available address space
Definition at line
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of file
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| #define FLASH_PAGE_SIZE 2048U |
Flash Memory page size
Definition at line
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of file
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Referenced by MSC_ErasePage() , and SYSTEM_GetFlashPageSize() .
| #define FLASH_SIZE (0x00040000UL) |
Available Flash Memory
Definition at line
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of file
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| #define GPCRC_COUNT 1 |
1 GPCRC available
Definition at line
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of file
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| #define GPCRC_PRESENT |
GPCRC is available in this part
Definition at line
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of file
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| #define GPIO_COUNT 1 |
1 GPIO available
Definition at line
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| #define GPIO_PRESENT |
GPIO is available in this part
Definition at line
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| #define I2C_COUNT 1 |
1 I2Cs available
Definition at line
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| #define I2C_PRESENT |
I2C is available in this part
Definition at line
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| #define IDAC_COUNT 1 |
1 IDACs available
Definition at line
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of file
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| #define IDAC_PRESENT |
IDAC is available in this part
Definition at line
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| #define LDMA_COUNT 1 |
1 LDMA available
Definition at line
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| #define LDMA_PRESENT |
LDMA is available in this part
Definition at line
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| #define LETIMER_COUNT 1 |
1 LETIMERs available
Definition at line
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of file
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| #define LETIMER_PRESENT |
LETIMER is available in this part
Definition at line
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| #define LEUART_COUNT 1 |
1 LEUARTs available
Definition at line
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| #define LEUART_PRESENT |
LEUART is available in this part
Definition at line
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| #define MSC_COUNT 1 |
1 MSC available
Definition at line
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of file
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| #define MSC_PRESENT |
MSC is available in this part
Definition at line
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| #define PART_NUMBER "EFM32JG1B200F256GM48" |
Configure part number Part Number
Definition at line
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of file
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| #define PCNT_COUNT 1 |
1 PCNTs available
Definition at line
206
of file
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Referenced by CMU_PCNTClockExternalSet() .
| #define PCNT_PRESENT |
PCNT is available in this part
Definition at line
205
of file
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| #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) |
PER_BITCLR base address
Definition at line
144
of file
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Referenced by BUS_RegMaskedClear() .
| #define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) |
PER_BITCLR used bits
Definition at line
147
of file
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| #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) |
PER_BITCLR end address
Definition at line
146
of file
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| #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) |
PER_BITCLR available address space
Definition at line
145
of file
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| #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) |
PER_BITSET base address
Definition at line
160
of file
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.
Referenced by BUS_RegMaskedSet() .
| #define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) |
PER_BITSET used bits
Definition at line
163
of file
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| #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) |
PER_BITSET end address
Definition at line
162
of file
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| #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) |
PER_BITSET available address space
Definition at line
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of file
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| #define PER_MEM_BASE ((uint32_t) 0x40000000UL) |
PER base address
Definition at line
164
of file
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.
Referenced by BUS_RegBitRead() , BUS_RegBitWrite() , BUS_RegMaskedClear() , and BUS_RegMaskedSet() .
| #define PER_MEM_BITS ((uint32_t) 0x00000014UL) |
PER used bits
Definition at line
167
of file
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.
| #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) |
PER end address
Definition at line
166
of file
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| #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) |
PER available address space
Definition at line
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of file
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| #define PRS_CHAN_COUNT 12 |
Number of PRS channels
Definition at line
184
of file
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.
Referenced by PRS_GpioOutputLocation() , PRS_Reset() , and PRS_SourceSignalSet() .
| #define PRS_COUNT 1 |
1 PRS available
Definition at line
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of file
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.
| #define PRS_PRESENT |
PRS is available in this part
Definition at line
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of file
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.
| #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) |
RAM_CODE base address
Definition at line
140
of file
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.
| #define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) |
RAM_CODE used bits
Definition at line
143
of file
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.
| #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) |
RAM_CODE end address
Definition at line
142
of file
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.
| #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) |
RAM_CODE available address space
Definition at line
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of file
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.
| #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) |
RAM base address
Definition at line
168
of file
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.
Referenced by EMU_RamPowerDown() .
| #define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) |
RAM used bits
Definition at line
171
of file
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.
| #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) |
RAM end address
Definition at line
170
of file
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.
| #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) |
RAM available address space
Definition at line
169
of file
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.
| #define RMU_COUNT 1 |
1 RMU available
Definition at line
222
of file
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.
| #define RMU_PRESENT |
RMU is available in this part
Definition at line
221
of file
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.
| #define RTCC_COUNT 1 |
1 RTCC available
Definition at line
238
of file
efm32jg1b200f256gm48.h
.
| #define RTCC_PRESENT |
RTCC is available in this part
Definition at line
237
of file
efm32jg1b200f256gm48.h
.
| #define SRAM_BASE (0x20000000UL) |
SRAM Base Address
Definition at line
181
of file
efm32jg1b200f256gm48.h
.
Referenced by BUS_RamBitRead() , BUS_RamBitWrite() , CORE_InitNvicVectorTable() , and EMU_RamPowerDown() .
| #define SRAM_SIZE (0x00008000UL) |
Available SRAM Memory
Definition at line
182
of file
efm32jg1b200f256gm48.h
.
Referenced by CORE_InitNvicVectorTable() , and EMU_RamPowerDown() .
| #define TIMER_COUNT 2 |
2 TIMERs available
Definition at line
198
of file
efm32jg1b200f256gm48.h
.
| #define TIMER_PRESENT |
TIMER is available in this part
Definition at line
197
of file
efm32jg1b200f256gm48.h
.
| #define USART_COUNT 2 |
2 USARTs available
Definition at line
200
of file
efm32jg1b200f256gm48.h
.
| #define USART_PRESENT |
USART is available in this part
Definition at line
199
of file
efm32jg1b200f256gm48.h
.
| #define WDOG_COUNT 1 |
1 WDOGs available
Definition at line
216
of file
efm32jg1b200f256gm48.h
.
| #define WDOG_PRESENT |
WDOG is available in this part
Definition at line
215
of file
efm32jg1b200f256gm48.h
.