BUSEMLIB

Detailed Description

BUS register and RAM bit/field read/write API.

API to perform bit-band and field set/clear access to RAM and peripherals.

Functions

__STATIC_INLINE unsigned int BUS_RamBitRead (volatile const uint32_t *addr, unsigned int bit)
 Perform a single-bit read operation on a 32-bit word in RAM.
 
__STATIC_INLINE void BUS_RamBitWrite (volatile uint32_t *addr, unsigned int bit, unsigned int val)
 Perform a single-bit write operation on a 32-bit word in RAM.
 
__STATIC_INLINE unsigned int BUS_RegBitRead (volatile const uint32_t *addr, unsigned int bit)
 Perform a single-bit read operation on a peripheral register.
 
__STATIC_INLINE void BUS_RegBitWrite (volatile uint32_t *addr, unsigned int bit, unsigned int val)
 Perform a single-bit write operation on a peripheral register.
 
__STATIC_INLINE void BUS_RegMaskedClear (volatile uint32_t *addr, uint32_t mask)
 Perform a masked clear operation on the peripheral register address.
 
__STATIC_INLINE uint32_t BUS_RegMaskedRead (volatile const uint32_t *addr, uint32_t mask)
 Perform a peripheral register masked read.
 
__STATIC_INLINE void BUS_RegMaskedSet (volatile uint32_t *addr, uint32_t mask)
 Perform a masked set operation on a peripheral register address.
 
__STATIC_INLINE void BUS_RegMaskedWrite (volatile uint32_t *addr, uint32_t mask, uint32_t val)
 Perform peripheral register masked clear and value write.
 

Function Documentation

__STATIC_INLINE unsigned int BUS_RamBitRead ( volatile const uint32_t *  addr,
unsigned int  bit 
)

Perform a single-bit read operation on a 32-bit word in RAM.

This function uses Cortex-M bit-banding hardware to perform an atomic read operation on a single register bit. See the reference manual for more details about bit-banding.

Note
This function is atomic on Cortex-M cores with bit-banding support. RAM bit-banding is performed using the memory alias region at BITBAND_RAM_BASE.
Parameters
[in]addrRAM address.
[in]bitA bit position to read, 0-31.
Returns
The requested bit shifted to bit position 0 in the return value.

Definition at line 113 of file em_bus.h.

References BITBAND_RAM_BASE, and SRAM_BASE.

__STATIC_INLINE void BUS_RamBitWrite ( volatile uint32_t *  addr,
unsigned int  bit,
unsigned int  val 
)

Perform a single-bit write operation on a 32-bit word in RAM.

This function uses Cortex-M bit-banding hardware to perform an atomic read-modify-write operation on a single bit write on a 32-bit word in RAM. See the reference manual for more details about bit-banding.

Note
This function is atomic on Cortex-M cores with bit-banding support. Bit- banding is a multicycle read-modify-write bus operation. RAM bit-banding is performed using the memory alias region at BITBAND_RAM_BASE.
Parameters
[in]addrAn ddress of a 32-bit word in RAM.
[in]bitA bit position to write, 0-31.
[in]valA value to set bit to, 0 or 1.

Definition at line 75 of file em_bus.h.

References BITBAND_RAM_BASE, and SRAM_BASE.

__STATIC_INLINE unsigned int BUS_RegBitRead ( volatile const uint32_t *  addr,
unsigned int  bit 
)

Perform a single-bit read operation on a peripheral register.

This function uses Cortex-M bit-banding hardware to perform an atomic read operation on a single register bit. See the reference manual for more details about bit-banding.

Note
This function is atomic on Cortex-M cores with bit-banding support. Peripheral register bit-banding is performed using the memory alias region at BITBAND_PER_BASE.
Parameters
[in]addrA peripheral register address.
[in]bitA bit position to read, 0-31.
Returns
The requested bit shifted to bit position 0 in the return value.

Definition at line 192 of file em_bus.h.

References BITBAND_PER_BASE, and PER_MEM_BASE.

Referenced by CMU_AUXHFRCOBandSet(), CMU_Calibrate(), CMU_CalibrateCountGet(), CMU_HFRCOBandSet(), CMU_OscillatorEnable(), CMU_OscillatorTuningSet(), EMU_VmonChannelStatusGet(), EMU_VmonStatusGet(), EMU_VScaleWait(), GPIO_PinInGet(), GPIO_PinOutGet(), and WDOGn_Enable().

__STATIC_INLINE void BUS_RegBitWrite ( volatile uint32_t *  addr,
unsigned int  bit,
unsigned int  val 
)

Perform a single-bit write operation on a peripheral register.

This function uses Cortex-M bit-banding hardware to perform an atomic read-modify-write operation on a single register bit. See the reference manual for more details about bit-banding.

Note
This function is atomic on Cortex-M cores with bit-banding support. Bit- banding is a multicycle read-modify-write bus operation. Peripheral register bit-banding is performed using the memory alias region at BITBAND_PER_BASE.
Parameters
[in]addrA peripheral register address.
[in]bitA bit position to write, 0-31.
[in]valA value to set bit to, 0 or 1.

Definition at line 146 of file em_bus.h.

References BITBAND_PER_BASE, and PER_MEM_BASE.

Referenced by ACMP_CapsenseInit(), ADC_InitScan(), ADC_InitSingle(), CHIP_Init(), CMU_CalibrateCont(), CMU_ClockEnable(), CMU_ClockSelectSet(), CMU_HFXOInit(), CMU_LFXOInit(), CMU_PCNTClockExternalSet(), CRYOTIMER_EM4WakeupEnable(), CRYOTIMER_Enable(), CRYPTO_KeyBufWrite(), EMU_EM2Block(), EMU_EM2UnBlock(), EMU_EnterEM4H(), EMU_EnterEM4S(), EMU_VmonEnable(), GPCRC_Enable(), GPIO_DbgSWDClkEnable(), GPIO_DbgSWDIOEnable(), GPIO_DbgSWOEnable(), GPIO_EM4SetPinRetention(), GPIO_ExtIntConfig(), GPIO_PinLock(), I2C_Enable(), I2C_Init(), LDMA_EnableChannelRequest(), LESENSE_AltExConfig(), LESENSE_ChannelConfig(), LESENSE_ChannelEnable(), MSC_EnableAutoCacheFlush(), MSC_EnableCache(), MSC_EnableCacheIRQs(), PCNT_CounterReset(), PCNT_Init(), PCNT_PRSInputEnable(), PCNT_Reset(), RMU_ResetCauseClear(), RMU_ResetControl(), RTCC_Enable(), SMU_EnablePPU(), SMU_SetPrivilegedAccess(), WDOGn_Enable(), and WDOGn_Lock().

__STATIC_INLINE void BUS_RegMaskedClear ( volatile uint32_t *  addr,
uint32_t  mask 
)

Perform a masked clear operation on the peripheral register address.

A peripheral register masked clear provides a single-cycle and atomic clear operation of a bit-mask in a peripheral register. All 1s in the mask are set to 0 in the register. All 0s in the mask are not changed in the register. RAMs and special peripherals are not supported. See the reference manual for more details about the peripheral register field clear.

Note
This function is single-cycle and atomic on cores with peripheral bit set and clear support. It uses the memory alias region at PER_BITCLR_MEM_BASE.
Parameters
[in]addrA peripheral register address.
[in]maskA mask to clear.

Definition at line 259 of file em_bus.h.

References PER_BITCLR_MEM_BASE, and PER_MEM_BASE.

Referenced by ACMP_IntDisable(), BUS_RegMaskedWrite(), EMU_EnterEM4(), GPIO_PinOutClear(), GPIO_PortOutClear(), LDMA_StartTransfer(), and LDMA_StopTransfer().

__STATIC_INLINE uint32_t BUS_RegMaskedRead ( volatile const uint32_t *  addr,
uint32_t  mask 
)

Perform a peripheral register masked read.

Read an unshifted and masked value from a peripheral register.

Note
This operation is not hardware accelerated.
Parameters
[in]addrA peripheral register address.
[in]maskA peripheral register mask.
Returns
An unshifted and masked register value.

Definition at line 325 of file em_bus.h.

__STATIC_INLINE void BUS_RegMaskedSet ( volatile uint32_t *  addr,
uint32_t  mask 
)

Perform a masked set operation on a peripheral register address.

A peripheral register masked set provides a single-cycle and atomic set operation of a bit-mask in a peripheral register. All 1s in the mask are set to 1 in the register. All 0s in the mask are not changed in the register. RAMs and special peripherals are not supported. See the reference manual for more details about the peripheral register field set.

Note
This function is single-cycle and atomic on cores with peripheral bit set and clear support. It uses the memory alias region at PER_BITSET_MEM_BASE.
Parameters
[in]addrA peripheral register address.
[in]maskA mask to set.

Definition at line 225 of file em_bus.h.

References PER_BITSET_MEM_BASE, and PER_MEM_BASE.

Referenced by BUS_RegMaskedWrite(), GPIO_PinOutSet(), and GPIO_PortOutSet().

__STATIC_INLINE void BUS_RegMaskedWrite ( volatile uint32_t *  addr,
uint32_t  mask,
uint32_t  val 
)

Perform peripheral register masked clear and value write.

This function first clears the mask in the peripheral register, then writes the value. Typically, the mask is a bit-field in the register and the value val is within the mask.

Note
This operation is not atomic. Note that the mask is first set to 0 before the val is set.
Parameters
[in]addrA peripheral register address.
[in]maskA peripheral register mask.
[in]valA peripheral register value. The value must be shifted to the correct bit position in the register corresponding to the field defined by the mask parameter. The register value must be contained in the field defined by the mask parameter. This function is not performing masking of val internally.

Definition at line 296 of file em_bus.h.

References BUS_RegMaskedClear(), and BUS_RegMaskedSet().

Referenced by ACMP_CapsenseChannelSet(), ACMP_GPIOSetup(), ACMP_Init(), ACMP_VASetup(), ACMP_VBSetup(), ADC_Init(), CMU_LFXOInit(), GPIO_DriveStrengthSet(), GPIO_ExtIntConfig(), and I2C_BusFreqSet().