Active or High-Performance State Operational Mode#

In the Active State, the SiWx917 SoC and SiWx917 NCP support three operational modes. Each mode has different current‑consumption characteristics.

  • Transmit Mode

  • Receive Mode

  • Listen Mode

Transmit Mode#

In Transmit Mode, all NWP power domains are active/operational except the receiver section of the Base Band Processor (BBP), Analog Front End (AFE), and RF Front End (RFFE). This mode uses the power profile required to support transmission activities.

SiWx917 SoC Transmit Mode in Active StateSiWx917 SoC Transmit Mode in Active State

SiWx917 NCP Listen Mode in Active StateSiWx917 NCP Listen Mode in Active State

Receive Mode#

In the receive mode, the transmit sections of the BBP, AFE, and RFFE are inactive.

SiWx917 SoC Receive Mode in Active StateSiWx917 SoC Receive Mode in Active State

SiWx917 NCP Listen Mode in Active StateSiWx917 NCP Listen Mode in Active State

Listen Mode#

This mode is a subset of the receive mode where certain portions of the BBP and AFE are inactive as no packet reception is in progress.

SiWx917 SoC Listen Mode in Active StateSiWx917 SoC Listen Mode in Active State

SiWx917 NCP Listen Mode in Active StateSiWx917 NCP Listen Mode in Active State

Sleep State Operational Mode (Ultra Low Power Mode)#

The SiWx917’s Sleep state Operational Mode is called Ultra Low Power (ULP) Mode with RAM Retention.

  • The Wireless Modem, NWP, and Security sections are inactive in the Ultra Low Power mode.

  • The PMU controls all other sections of the chip.

  • The always‑on logic domain runs at a reduced supply voltage and uses a 32 kHz low‑frequency clock.

  • Software Configuration: You can configure the 32 kHz clock source in software. Available options include:

    • Internal 32 kHZ RC clock (default)

    • 32 kHZ external crystal clock (enable BIT(22))

    • 32 kHZ bypass clock on UULP_VBAT_GPIO_3 (enable BIT(23))

Enable the selected bit in the Boot Configuration (sl_wifi_device_configuration_t.boot_config.ext_custom_fea- ture_bit_map). For more details on 32 kHZ Clock Source, refer to the 7.4.1 Clock Specification section in the SiWx917 SoC Data Sheet or the SiWx917 NCP Data Sheet and Chip Schematic.

  • The SiWx917 NCP host interface is inactive in Sleep Mode and reactivates each time the device wakes up.

SiWx917 SoC Ultra Low Power Mode with RAM RetentionSiWx917 SoC Ultra Low Power Mode with RAM Retention

SiWx917 NCP Ultra Low Power Mode with RAM RetentionSiWx917 NCP Ultra Low Power Mode with RAM Retention