EFM32JG1B200F256GM48Devices

Modules

Bit Fields
 
Core
Processor and Core Peripheral Section.
 
Part
 
Peripheral Declarations
 
Peripheral Memory Map
 
Peripheral Offsets
 
Peripheral TypeDefs
Device Specific Peripheral Register Structures.
 

Macros

#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET)   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
 Set the value of a bit field within a register.
 

Typedefs

typedef enum IRQn IRQn_Type
 

Enumerations

enum  IRQn {
  NonMaskableInt_IRQn = -14,
  HardFault_IRQn = -13,
  MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11,
  UsageFault_IRQn = -10,
  SVCall_IRQn = -5,
  DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2,
  SysTick_IRQn = -1,
  EMU_IRQn = 0,
  WDOG0_IRQn = 2,
  LDMA_IRQn = 8,
  GPIO_EVEN_IRQn = 9,
  TIMER0_IRQn = 10,
  USART0_RX_IRQn = 11,
  USART0_TX_IRQn = 12,
  ACMP0_IRQn = 13,
  ADC0_IRQn = 14,
  IDAC0_IRQn = 15,
  I2C0_IRQn = 16,
  GPIO_ODD_IRQn = 17,
  TIMER1_IRQn = 18,
  USART1_RX_IRQn = 19,
  USART1_TX_IRQn = 20,
  LEUART0_IRQn = 21,
  PCNT0_IRQn = 22,
  CMU_IRQn = 23,
  MSC_IRQn = 24,
  CRYPTO_IRQn = 25,
  LETIMER0_IRQn = 26,
  RTCC_IRQn = 29,
  CRYOTIMER_IRQn = 31
}
 

Macro Definition Documentation

#define SET_BIT_FIELD (   REG,
  MASK,
  VALUE,
  OFFSET 
)    REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));

Set the value of a bit field within a register.

Parameters
REGThe register to update
MASKThe mask for the bit field to update
VALUEThe value to write to the bit field
OFFSETThe number of bits that the field is offset within the register. 0 (zero) means LSB.

Definition at line 418 of file efm32jg1b200f256gm48.h.

Typedef Documentation

typedef enum IRQn IRQn_Type

Interrupt Number Definition

Enumeration Type Documentation

enum IRQn

Interrupt Number Definition

Enumerator
NonMaskableInt_IRQn 

2 Cortex-M3 Non Maskable Interrupt

HardFault_IRQn 

3 Cortex-M3 Hard Fault Interrupt

MemoryManagement_IRQn 

4 Cortex-M3 Memory Management Interrupt

BusFault_IRQn 

5 Cortex-M3 Bus Fault Interrupt

UsageFault_IRQn 

6 Cortex-M3 Usage Fault Interrupt

SVCall_IRQn 

11 Cortex-M3 SV Call Interrupt

DebugMonitor_IRQn 

12 Cortex-M3 Debug Monitor Interrupt

PendSV_IRQn 

14 Cortex-M3 Pend SV Interrupt

SysTick_IRQn 

15 Cortex-M3 System Tick Interrupt

EMU_IRQn 

16+0 EFM32 EMU Interrupt

WDOG0_IRQn 

16+2 EFM32 WDOG0 Interrupt

LDMA_IRQn 

16+8 EFM32 LDMA Interrupt

GPIO_EVEN_IRQn 

16+9 EFM32 GPIO_EVEN Interrupt

TIMER0_IRQn 

16+10 EFM32 TIMER0 Interrupt

USART0_RX_IRQn 

16+11 EFM32 USART0_RX Interrupt

USART0_TX_IRQn 

16+12 EFM32 USART0_TX Interrupt

ACMP0_IRQn 

16+13 EFM32 ACMP0 Interrupt

ADC0_IRQn 

16+14 EFM32 ADC0 Interrupt

IDAC0_IRQn 

16+15 EFM32 IDAC0 Interrupt

I2C0_IRQn 

16+16 EFM32 I2C0 Interrupt

GPIO_ODD_IRQn 

16+17 EFM32 GPIO_ODD Interrupt

TIMER1_IRQn 

16+18 EFM32 TIMER1 Interrupt

USART1_RX_IRQn 

16+19 EFM32 USART1_RX Interrupt

USART1_TX_IRQn 

16+20 EFM32 USART1_TX Interrupt

LEUART0_IRQn 

16+21 EFM32 LEUART0 Interrupt

PCNT0_IRQn 

16+22 EFM32 PCNT0 Interrupt

CMU_IRQn 

16+23 EFM32 CMU Interrupt

MSC_IRQn 

16+24 EFM32 MSC Interrupt

CRYPTO_IRQn 

16+25 EFM32 CRYPTO Interrupt

LETIMER0_IRQn 

16+26 EFM32 LETIMER0 Interrupt

RTCC_IRQn 

16+29 EFM32 RTCC Interrupt

CRYOTIMER_IRQn 

16+31 EFM32 CRYOTIMER Interrupt

Definition at line 58 of file efm32jg1b200f256gm48.h.