WDOG Bit FieldsDevices > WDOG

Macros

#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL
#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL
#define _WDOG_CMD_CLEAR_MASK 0x1UL
#define _WDOG_CMD_CLEAR_SHIFT 0
#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL
#define _WDOG_CMD_MASK 0x00000001UL
#define _WDOG_CMD_RESETVALUE 0x00000000UL
#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL
#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL
#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL
#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL
#define _WDOG_CTRL_CLKSEL_SHIFT 12
#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL
#define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL
#define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL
#define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL
#define _WDOG_CTRL_CLRSRC_SHIFT 30
#define _WDOG_CTRL_CLRSRC_SW 0x00000000UL
#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL
#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL
#define _WDOG_CTRL_DEBUGRUN_SHIFT 1
#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL
#define _WDOG_CTRL_EM2RUN_MASK 0x4UL
#define _WDOG_CTRL_EM2RUN_SHIFT 2
#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL
#define _WDOG_CTRL_EM3RUN_MASK 0x8UL
#define _WDOG_CTRL_EM3RUN_SHIFT 3
#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL
#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL
#define _WDOG_CTRL_EM4BLOCK_SHIFT 5
#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL
#define _WDOG_CTRL_EN_MASK 0x1UL
#define _WDOG_CTRL_EN_SHIFT 0
#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL
#define _WDOG_CTRL_LOCK_MASK 0x10UL
#define _WDOG_CTRL_LOCK_SHIFT 4
#define _WDOG_CTRL_MASK 0xC7033F7FUL
#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL
#define _WDOG_CTRL_PERSEL_MASK 0xF00UL
#define _WDOG_CTRL_PERSEL_SHIFT 8
#define _WDOG_CTRL_RESETVALUE 0x00000F00UL
#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL
#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL
#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6
#define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL
#define _WDOG_CTRL_WARNSEL_MASK 0x30000UL
#define _WDOG_CTRL_WARNSEL_SHIFT 16
#define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL
#define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL
#define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL
#define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL
#define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31
#define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL
#define _WDOG_CTRL_WINSEL_MASK 0x7000000UL
#define _WDOG_CTRL_WINSEL_SHIFT 24
#define _WDOG_IEN_MASK 0x0000001FUL
#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL
#define _WDOG_IEN_PEM0_MASK 0x8UL
#define _WDOG_IEN_PEM0_SHIFT 3
#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL
#define _WDOG_IEN_PEM1_MASK 0x10UL
#define _WDOG_IEN_PEM1_SHIFT 4
#define _WDOG_IEN_RESETVALUE 0x00000000UL
#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL
#define _WDOG_IEN_TOUT_MASK 0x1UL
#define _WDOG_IEN_TOUT_SHIFT 0
#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL
#define _WDOG_IEN_WARN_MASK 0x2UL
#define _WDOG_IEN_WARN_SHIFT 1
#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL
#define _WDOG_IEN_WIN_MASK 0x4UL
#define _WDOG_IEN_WIN_SHIFT 2
#define _WDOG_IF_MASK 0x0000001FUL
#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL
#define _WDOG_IF_PEM0_MASK 0x8UL
#define _WDOG_IF_PEM0_SHIFT 3
#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL
#define _WDOG_IF_PEM1_MASK 0x10UL
#define _WDOG_IF_PEM1_SHIFT 4
#define _WDOG_IF_RESETVALUE 0x00000000UL
#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL
#define _WDOG_IF_TOUT_MASK 0x1UL
#define _WDOG_IF_TOUT_SHIFT 0
#define _WDOG_IF_WARN_DEFAULT 0x00000000UL
#define _WDOG_IF_WARN_MASK 0x2UL
#define _WDOG_IF_WARN_SHIFT 1
#define _WDOG_IF_WIN_DEFAULT 0x00000000UL
#define _WDOG_IF_WIN_MASK 0x4UL
#define _WDOG_IF_WIN_SHIFT 2
#define _WDOG_IFC_MASK 0x0000001FUL
#define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL
#define _WDOG_IFC_PEM0_MASK 0x8UL
#define _WDOG_IFC_PEM0_SHIFT 3
#define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL
#define _WDOG_IFC_PEM1_MASK 0x10UL
#define _WDOG_IFC_PEM1_SHIFT 4
#define _WDOG_IFC_RESETVALUE 0x00000000UL
#define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL
#define _WDOG_IFC_TOUT_MASK 0x1UL
#define _WDOG_IFC_TOUT_SHIFT 0
#define _WDOG_IFC_WARN_DEFAULT 0x00000000UL
#define _WDOG_IFC_WARN_MASK 0x2UL
#define _WDOG_IFC_WARN_SHIFT 1
#define _WDOG_IFC_WIN_DEFAULT 0x00000000UL
#define _WDOG_IFC_WIN_MASK 0x4UL
#define _WDOG_IFC_WIN_SHIFT 2
#define _WDOG_IFS_MASK 0x0000001FUL
#define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL
#define _WDOG_IFS_PEM0_MASK 0x8UL
#define _WDOG_IFS_PEM0_SHIFT 3
#define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL
#define _WDOG_IFS_PEM1_MASK 0x10UL
#define _WDOG_IFS_PEM1_SHIFT 4
#define _WDOG_IFS_RESETVALUE 0x00000000UL
#define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL
#define _WDOG_IFS_TOUT_MASK 0x1UL
#define _WDOG_IFS_TOUT_SHIFT 0
#define _WDOG_IFS_WARN_DEFAULT 0x00000000UL
#define _WDOG_IFS_WARN_MASK 0x2UL
#define _WDOG_IFS_WARN_SHIFT 1
#define _WDOG_IFS_WIN_DEFAULT 0x00000000UL
#define _WDOG_IFS_WIN_MASK 0x4UL
#define _WDOG_IFS_WIN_SHIFT 2
#define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL
#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL
#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL
#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8
#define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL
#define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL
#define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0
#define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL
#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL
#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL
#define _WDOG_SYNCBUSY_CMD_SHIFT 1
#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL
#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL
#define _WDOG_SYNCBUSY_CTRL_SHIFT 0
#define _WDOG_SYNCBUSY_MASK 0x0000000FUL
#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL
#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL
#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2
#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL
#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL
#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3
#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL
#define WDOG_CMD_CLEAR (0x1UL << 0)
#define WDOG_CMD_CLEAR_CLEARED ( _WDOG_CMD_CLEAR_CLEARED << 0)
#define WDOG_CMD_CLEAR_DEFAULT ( _WDOG_CMD_CLEAR_DEFAULT << 0)
#define WDOG_CMD_CLEAR_UNCHANGED ( _WDOG_CMD_CLEAR_UNCHANGED << 0)
#define WDOG_CTRL_CLKSEL_DEFAULT ( _WDOG_CTRL_CLKSEL_DEFAULT << 12)
#define WDOG_CTRL_CLKSEL_LFRCO ( _WDOG_CTRL_CLKSEL_LFRCO << 12)
#define WDOG_CTRL_CLKSEL_LFXO ( _WDOG_CTRL_CLKSEL_LFXO << 12)
#define WDOG_CTRL_CLKSEL_ULFRCO ( _WDOG_CTRL_CLKSEL_ULFRCO << 12)
#define WDOG_CTRL_CLRSRC (0x1UL << 30)
#define WDOG_CTRL_CLRSRC_DEFAULT ( _WDOG_CTRL_CLRSRC_DEFAULT << 30)
#define WDOG_CTRL_CLRSRC_PCH0 ( _WDOG_CTRL_CLRSRC_PCH0 << 30)
#define WDOG_CTRL_CLRSRC_SW ( _WDOG_CTRL_CLRSRC_SW << 30)
#define WDOG_CTRL_DEBUGRUN (0x1UL << 1)
#define WDOG_CTRL_DEBUGRUN_DEFAULT ( _WDOG_CTRL_DEBUGRUN_DEFAULT << 1)
#define WDOG_CTRL_EM2RUN (0x1UL << 2)
#define WDOG_CTRL_EM2RUN_DEFAULT ( _WDOG_CTRL_EM2RUN_DEFAULT << 2)
#define WDOG_CTRL_EM3RUN (0x1UL << 3)
#define WDOG_CTRL_EM3RUN_DEFAULT ( _WDOG_CTRL_EM3RUN_DEFAULT << 3)
#define WDOG_CTRL_EM4BLOCK (0x1UL << 5)
#define WDOG_CTRL_EM4BLOCK_DEFAULT ( _WDOG_CTRL_EM4BLOCK_DEFAULT << 5)
#define WDOG_CTRL_EN (0x1UL << 0)
#define WDOG_CTRL_EN_DEFAULT ( _WDOG_CTRL_EN_DEFAULT << 0)
#define WDOG_CTRL_LOCK (0x1UL << 4)
#define WDOG_CTRL_LOCK_DEFAULT ( _WDOG_CTRL_LOCK_DEFAULT << 4)
#define WDOG_CTRL_PERSEL_DEFAULT ( _WDOG_CTRL_PERSEL_DEFAULT << 8)
#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6)
#define WDOG_CTRL_SWOSCBLOCK_DEFAULT ( _WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6)
#define WDOG_CTRL_WARNSEL_DEFAULT ( _WDOG_CTRL_WARNSEL_DEFAULT << 16)
#define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31)
#define WDOG_CTRL_WDOGRSTDIS_DEFAULT ( _WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31)
#define WDOG_CTRL_WDOGRSTDIS_DIS ( _WDOG_CTRL_WDOGRSTDIS_DIS << 31)
#define WDOG_CTRL_WDOGRSTDIS_EN ( _WDOG_CTRL_WDOGRSTDIS_EN << 31)
#define WDOG_CTRL_WINSEL_DEFAULT ( _WDOG_CTRL_WINSEL_DEFAULT << 24)
#define WDOG_IEN_PEM0 (0x1UL << 3)
#define WDOG_IEN_PEM0_DEFAULT ( _WDOG_IEN_PEM0_DEFAULT << 3)
#define WDOG_IEN_PEM1 (0x1UL << 4)
#define WDOG_IEN_PEM1_DEFAULT ( _WDOG_IEN_PEM1_DEFAULT << 4)
#define WDOG_IEN_TOUT (0x1UL << 0)
#define WDOG_IEN_TOUT_DEFAULT ( _WDOG_IEN_TOUT_DEFAULT << 0)
#define WDOG_IEN_WARN (0x1UL << 1)
#define WDOG_IEN_WARN_DEFAULT ( _WDOG_IEN_WARN_DEFAULT << 1)
#define WDOG_IEN_WIN (0x1UL << 2)
#define WDOG_IEN_WIN_DEFAULT ( _WDOG_IEN_WIN_DEFAULT << 2)
#define WDOG_IF_PEM0 (0x1UL << 3)
#define WDOG_IF_PEM0_DEFAULT ( _WDOG_IF_PEM0_DEFAULT << 3)
#define WDOG_IF_PEM1 (0x1UL << 4)
#define WDOG_IF_PEM1_DEFAULT ( _WDOG_IF_PEM1_DEFAULT << 4)
#define WDOG_IF_TOUT (0x1UL << 0)
#define WDOG_IF_TOUT_DEFAULT ( _WDOG_IF_TOUT_DEFAULT << 0)
#define WDOG_IF_WARN (0x1UL << 1)
#define WDOG_IF_WARN_DEFAULT ( _WDOG_IF_WARN_DEFAULT << 1)
#define WDOG_IF_WIN (0x1UL << 2)
#define WDOG_IF_WIN_DEFAULT ( _WDOG_IF_WIN_DEFAULT << 2)
#define WDOG_IFC_PEM0 (0x1UL << 3)
#define WDOG_IFC_PEM0_DEFAULT ( _WDOG_IFC_PEM0_DEFAULT << 3)
#define WDOG_IFC_PEM1 (0x1UL << 4)
#define WDOG_IFC_PEM1_DEFAULT ( _WDOG_IFC_PEM1_DEFAULT << 4)
#define WDOG_IFC_TOUT (0x1UL << 0)
#define WDOG_IFC_TOUT_DEFAULT ( _WDOG_IFC_TOUT_DEFAULT << 0)
#define WDOG_IFC_WARN (0x1UL << 1)
#define WDOG_IFC_WARN_DEFAULT ( _WDOG_IFC_WARN_DEFAULT << 1)
#define WDOG_IFC_WIN (0x1UL << 2)
#define WDOG_IFC_WIN_DEFAULT ( _WDOG_IFC_WIN_DEFAULT << 2)
#define WDOG_IFS_PEM0 (0x1UL << 3)
#define WDOG_IFS_PEM0_DEFAULT ( _WDOG_IFS_PEM0_DEFAULT << 3)
#define WDOG_IFS_PEM1 (0x1UL << 4)
#define WDOG_IFS_PEM1_DEFAULT ( _WDOG_IFS_PEM1_DEFAULT << 4)
#define WDOG_IFS_TOUT (0x1UL << 0)
#define WDOG_IFS_TOUT_DEFAULT ( _WDOG_IFS_TOUT_DEFAULT << 0)
#define WDOG_IFS_WARN (0x1UL << 1)
#define WDOG_IFS_WARN_DEFAULT ( _WDOG_IFS_WARN_DEFAULT << 1)
#define WDOG_IFS_WIN (0x1UL << 2)
#define WDOG_IFS_WIN_DEFAULT ( _WDOG_IFS_WIN_DEFAULT << 2)
#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8)
#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT ( _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8)
#define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT ( _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0)
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0)
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0)
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0)
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0)
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0)
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0)
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0)
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0)
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0)
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0)
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0)
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0)
#define WDOG_SYNCBUSY_CMD (0x1UL << 1)
#define WDOG_SYNCBUSY_CMD_DEFAULT ( _WDOG_SYNCBUSY_CMD_DEFAULT << 1)
#define WDOG_SYNCBUSY_CTRL (0x1UL << 0)
#define WDOG_SYNCBUSY_CTRL_DEFAULT ( _WDOG_SYNCBUSY_CTRL_DEFAULT << 0)
#define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2)
#define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT ( _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2)
#define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3)
#define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT ( _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3)

Macro Definition Documentation

#define _WDOG_CMD_CLEAR_CLEARED   0x00000001UL

Mode CLEARED for WDOG_CMD

Definition at line 158 of file efm32jg1b_wdog.h .

#define _WDOG_CMD_CLEAR_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CMD

Definition at line 156 of file efm32jg1b_wdog.h .

#define _WDOG_CMD_CLEAR_MASK   0x1UL

Bit mask for WDOG_CLEAR

Definition at line 155 of file efm32jg1b_wdog.h .

#define _WDOG_CMD_CLEAR_SHIFT   0

Shift value for WDOG_CLEAR

Definition at line 154 of file efm32jg1b_wdog.h .

#define _WDOG_CMD_CLEAR_UNCHANGED   0x00000000UL

Mode UNCHANGED for WDOG_CMD

Definition at line 157 of file efm32jg1b_wdog.h .

#define _WDOG_CMD_MASK   0x00000001UL

Mask for WDOG_CMD

Definition at line 152 of file efm32jg1b_wdog.h .

#define _WDOG_CMD_RESETVALUE   0x00000000UL

Default value for WDOG_CMD

Definition at line 151 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_CLKSEL_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CTRL

Definition at line 115 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_CLKSEL_LFRCO   0x00000001UL

Mode LFRCO for WDOG_CTRL

Definition at line 117 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_CLKSEL_LFXO   0x00000002UL

Mode LFXO for WDOG_CTRL

Definition at line 118 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_CLKSEL_MASK   0x3000UL

Bit mask for WDOG_CLKSEL

Definition at line 114 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_CLKSEL_SHIFT   12

Shift value for WDOG_CLKSEL

Definition at line 113 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Init() .

#define _WDOG_CTRL_CLKSEL_ULFRCO   0x00000000UL

Mode ULFRCO for WDOG_CTRL

Definition at line 116 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_CLRSRC_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CTRL

Definition at line 134 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_CLRSRC_MASK   0x40000000UL

Bit mask for WDOG_CLRSRC

Definition at line 133 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_CLRSRC_PCH0   0x00000001UL

Mode PCH0 for WDOG_CTRL

Definition at line 136 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_CLRSRC_SHIFT   30

Shift value for WDOG_CLRSRC

Definition at line 132 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_CLRSRC_SW   0x00000000UL

Mode SW for WDOG_CTRL

Definition at line 135 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_DEBUGRUN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CTRL

Definition at line 82 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_DEBUGRUN_MASK   0x2UL

Bit mask for WDOG_DEBUGRUN

Definition at line 81 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_DEBUGRUN_SHIFT   1

Shift value for WDOG_DEBUGRUN

Definition at line 80 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_EM2RUN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CTRL

Definition at line 87 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_EM2RUN_MASK   0x4UL

Bit mask for WDOG_EM2RUN

Definition at line 86 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_EM2RUN_SHIFT   2

Shift value for WDOG_EM2RUN

Definition at line 85 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_EM3RUN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CTRL

Definition at line 92 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_EM3RUN_MASK   0x8UL

Bit mask for WDOG_EM3RUN

Definition at line 91 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_EM3RUN_SHIFT   3

Shift value for WDOG_EM3RUN

Definition at line 90 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_EM4BLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CTRL

Definition at line 102 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_EM4BLOCK_MASK   0x20UL

Bit mask for WDOG_EM4BLOCK

Definition at line 101 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_EM4BLOCK_SHIFT   5

Shift value for WDOG_EM4BLOCK

Definition at line 100 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_EN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CTRL

Definition at line 77 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_EN_MASK   0x1UL

Bit mask for WDOG_EN

Definition at line 76 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_EN_SHIFT   0

Shift value for WDOG_EN

Definition at line 75 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Enable() .

#define _WDOG_CTRL_LOCK_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CTRL

Definition at line 97 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_LOCK_MASK   0x10UL

Bit mask for WDOG_LOCK

Definition at line 96 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_LOCK_SHIFT   4

Shift value for WDOG_LOCK

Definition at line 95 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Lock() .

#define _WDOG_CTRL_MASK   0xC7033F7FUL

Mask for WDOG_CTRL

Definition at line 73 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_PERSEL_DEFAULT   0x0000000FUL

Mode DEFAULT for WDOG_CTRL

Definition at line 111 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_PERSEL_MASK   0xF00UL

Bit mask for WDOG_PERSEL

Definition at line 110 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_PERSEL_SHIFT   8

Shift value for WDOG_PERSEL

Definition at line 109 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Init() .

#define _WDOG_CTRL_RESETVALUE   0x00000F00UL

Default value for WDOG_CTRL

Definition at line 72 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CTRL

Definition at line 107 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_SWOSCBLOCK_MASK   0x40UL

Bit mask for WDOG_SWOSCBLOCK

Definition at line 106 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_SWOSCBLOCK_SHIFT   6

Shift value for WDOG_SWOSCBLOCK

Definition at line 105 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_WARNSEL_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CTRL

Definition at line 125 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_WARNSEL_MASK   0x30000UL

Bit mask for WDOG_WARNSEL

Definition at line 124 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Init() .

#define _WDOG_CTRL_WARNSEL_SHIFT   16

Shift value for WDOG_WARNSEL

Definition at line 123 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Init() .

#define _WDOG_CTRL_WDOGRSTDIS_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CTRL

Definition at line 143 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_WDOGRSTDIS_DIS   0x00000001UL

Mode DIS for WDOG_CTRL

Definition at line 145 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_WDOGRSTDIS_EN   0x00000000UL

Mode EN for WDOG_CTRL

Definition at line 144 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_WDOGRSTDIS_MASK   0x80000000UL

Bit mask for WDOG_WDOGRSTDIS

Definition at line 142 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_WDOGRSTDIS_SHIFT   31

Shift value for WDOG_WDOGRSTDIS

Definition at line 141 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_WINSEL_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CTRL

Definition at line 129 of file efm32jg1b_wdog.h .

#define _WDOG_CTRL_WINSEL_MASK   0x7000000UL

Bit mask for WDOG_WINSEL

Definition at line 128 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Init() .

#define _WDOG_CTRL_WINSEL_SHIFT   24

Shift value for WDOG_WINSEL

Definition at line 127 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Init() .

#define _WDOG_IEN_MASK   0x0000001FUL

Mask for WDOG_IEN

Definition at line 313 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_PEM0_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IEN

Definition at line 332 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_PEM0_MASK   0x8UL

Bit mask for WDOG_PEM0

Definition at line 331 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_PEM0_SHIFT   3

Shift value for WDOG_PEM0

Definition at line 330 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_PEM1_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IEN

Definition at line 337 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_PEM1_MASK   0x10UL

Bit mask for WDOG_PEM1

Definition at line 336 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_PEM1_SHIFT   4

Shift value for WDOG_PEM1

Definition at line 335 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_RESETVALUE   0x00000000UL

Default value for WDOG_IEN

Definition at line 312 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_TOUT_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IEN

Definition at line 317 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_TOUT_MASK   0x1UL

Bit mask for WDOG_TOUT

Definition at line 316 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_TOUT_SHIFT   0

Shift value for WDOG_TOUT

Definition at line 315 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_WARN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IEN

Definition at line 322 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_WARN_MASK   0x2UL

Bit mask for WDOG_WARN

Definition at line 321 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_WARN_SHIFT   1

Shift value for WDOG_WARN

Definition at line 320 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_WIN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IEN

Definition at line 327 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_WIN_MASK   0x4UL

Bit mask for WDOG_WIN

Definition at line 326 of file efm32jg1b_wdog.h .

#define _WDOG_IEN_WIN_SHIFT   2

Shift value for WDOG_WIN

Definition at line 325 of file efm32jg1b_wdog.h .

#define _WDOG_IF_MASK   0x0000001FUL

Mask for WDOG_IF

Definition at line 226 of file efm32jg1b_wdog.h .

#define _WDOG_IF_PEM0_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IF

Definition at line 245 of file efm32jg1b_wdog.h .

#define _WDOG_IF_PEM0_MASK   0x8UL

Bit mask for WDOG_PEM0

Definition at line 244 of file efm32jg1b_wdog.h .

#define _WDOG_IF_PEM0_SHIFT   3

Shift value for WDOG_PEM0

Definition at line 243 of file efm32jg1b_wdog.h .

#define _WDOG_IF_PEM1_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IF

Definition at line 250 of file efm32jg1b_wdog.h .

#define _WDOG_IF_PEM1_MASK   0x10UL

Bit mask for WDOG_PEM1

Definition at line 249 of file efm32jg1b_wdog.h .

#define _WDOG_IF_PEM1_SHIFT   4

Shift value for WDOG_PEM1

Definition at line 248 of file efm32jg1b_wdog.h .

#define _WDOG_IF_RESETVALUE   0x00000000UL

Default value for WDOG_IF

Definition at line 225 of file efm32jg1b_wdog.h .

#define _WDOG_IF_TOUT_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IF

Definition at line 230 of file efm32jg1b_wdog.h .

#define _WDOG_IF_TOUT_MASK   0x1UL

Bit mask for WDOG_TOUT

Definition at line 229 of file efm32jg1b_wdog.h .

#define _WDOG_IF_TOUT_SHIFT   0

Shift value for WDOG_TOUT

Definition at line 228 of file efm32jg1b_wdog.h .

#define _WDOG_IF_WARN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IF

Definition at line 235 of file efm32jg1b_wdog.h .

#define _WDOG_IF_WARN_MASK   0x2UL

Bit mask for WDOG_WARN

Definition at line 234 of file efm32jg1b_wdog.h .

#define _WDOG_IF_WARN_SHIFT   1

Shift value for WDOG_WARN

Definition at line 233 of file efm32jg1b_wdog.h .

#define _WDOG_IF_WIN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IF

Definition at line 240 of file efm32jg1b_wdog.h .

#define _WDOG_IF_WIN_MASK   0x4UL

Bit mask for WDOG_WIN

Definition at line 239 of file efm32jg1b_wdog.h .

#define _WDOG_IF_WIN_SHIFT   2

Shift value for WDOG_WIN

Definition at line 238 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_MASK   0x0000001FUL

Mask for WDOG_IFC

Definition at line 284 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_PEM0_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IFC

Definition at line 303 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_PEM0_MASK   0x8UL

Bit mask for WDOG_PEM0

Definition at line 302 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_PEM0_SHIFT   3

Shift value for WDOG_PEM0

Definition at line 301 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_PEM1_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IFC

Definition at line 308 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_PEM1_MASK   0x10UL

Bit mask for WDOG_PEM1

Definition at line 307 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_PEM1_SHIFT   4

Shift value for WDOG_PEM1

Definition at line 306 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_RESETVALUE   0x00000000UL

Default value for WDOG_IFC

Definition at line 283 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_TOUT_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IFC

Definition at line 288 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_TOUT_MASK   0x1UL

Bit mask for WDOG_TOUT

Definition at line 287 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_TOUT_SHIFT   0

Shift value for WDOG_TOUT

Definition at line 286 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_WARN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IFC

Definition at line 293 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_WARN_MASK   0x2UL

Bit mask for WDOG_WARN

Definition at line 292 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_WARN_SHIFT   1

Shift value for WDOG_WARN

Definition at line 291 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_WIN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IFC

Definition at line 298 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_WIN_MASK   0x4UL

Bit mask for WDOG_WIN

Definition at line 297 of file efm32jg1b_wdog.h .

#define _WDOG_IFC_WIN_SHIFT   2

Shift value for WDOG_WIN

Definition at line 296 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_MASK   0x0000001FUL

Mask for WDOG_IFS

Definition at line 255 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_PEM0_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IFS

Definition at line 274 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_PEM0_MASK   0x8UL

Bit mask for WDOG_PEM0

Definition at line 273 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_PEM0_SHIFT   3

Shift value for WDOG_PEM0

Definition at line 272 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_PEM1_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IFS

Definition at line 279 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_PEM1_MASK   0x10UL

Bit mask for WDOG_PEM1

Definition at line 278 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_PEM1_SHIFT   4

Shift value for WDOG_PEM1

Definition at line 277 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_RESETVALUE   0x00000000UL

Default value for WDOG_IFS

Definition at line 254 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_TOUT_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IFS

Definition at line 259 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_TOUT_MASK   0x1UL

Bit mask for WDOG_TOUT

Definition at line 258 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_TOUT_SHIFT   0

Shift value for WDOG_TOUT

Definition at line 257 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_WARN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IFS

Definition at line 264 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_WARN_MASK   0x2UL

Bit mask for WDOG_WARN

Definition at line 263 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_WARN_SHIFT   1

Shift value for WDOG_WARN

Definition at line 262 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_WIN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IFS

Definition at line 269 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_WIN_MASK   0x4UL

Bit mask for WDOG_WIN

Definition at line 268 of file efm32jg1b_wdog.h .

#define _WDOG_IFS_WIN_SHIFT   2

Shift value for WDOG_WIN

Definition at line 267 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_MASK   0x0000010FUL

Mask for WDOG_PCH_PRSCTRL

Definition at line 189 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_PCH_PRSCTRL

Definition at line 221 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK   0x100UL

Bit mask for WDOG_PRSMISSRSTEN

Definition at line 220 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT   8

Shift value for WDOG_PRSMISSRSTEN

Definition at line 219 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_PCH_PRSCTRL

Definition at line 192 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_MASK   0xFUL

Bit mask for WDOG_PRSSEL

Definition at line 191 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0   0x00000000UL

Mode PRSCH0 for WDOG_PCH_PRSCTRL

Definition at line 193 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1   0x00000001UL

Mode PRSCH1 for WDOG_PCH_PRSCTRL

Definition at line 194 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10   0x0000000AUL

Mode PRSCH10 for WDOG_PCH_PRSCTRL

Definition at line 203 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11   0x0000000BUL

Mode PRSCH11 for WDOG_PCH_PRSCTRL

Definition at line 204 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2   0x00000002UL

Mode PRSCH2 for WDOG_PCH_PRSCTRL

Definition at line 195 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3   0x00000003UL

Mode PRSCH3 for WDOG_PCH_PRSCTRL

Definition at line 196 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4   0x00000004UL

Mode PRSCH4 for WDOG_PCH_PRSCTRL

Definition at line 197 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5   0x00000005UL

Mode PRSCH5 for WDOG_PCH_PRSCTRL

Definition at line 198 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6   0x00000006UL

Mode PRSCH6 for WDOG_PCH_PRSCTRL

Definition at line 199 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7   0x00000007UL

Mode PRSCH7 for WDOG_PCH_PRSCTRL

Definition at line 200 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8   0x00000008UL

Mode PRSCH8 for WDOG_PCH_PRSCTRL

Definition at line 201 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9   0x00000009UL

Mode PRSCH9 for WDOG_PCH_PRSCTRL

Definition at line 202 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT   0

Shift value for WDOG_PRSSEL

Definition at line 190 of file efm32jg1b_wdog.h .

#define _WDOG_PCH_PRSCTRL_RESETVALUE   0x00000000UL

Default value for WDOG_PCH_PRSCTRL

Definition at line 188 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_CMD_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_SYNCBUSY

Definition at line 174 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_CMD_MASK   0x2UL

Bit mask for WDOG_CMD

Definition at line 173 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_CMD_SHIFT   1

Shift value for WDOG_CMD

Definition at line 172 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_CTRL_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_SYNCBUSY

Definition at line 169 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_CTRL_MASK   0x1UL

Bit mask for WDOG_CTRL

Definition at line 168 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_CTRL_SHIFT   0

Shift value for WDOG_CTRL

Definition at line 167 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_MASK   0x0000000FUL

Mask for WDOG_SYNCBUSY

Definition at line 165 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_SYNCBUSY

Definition at line 179 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK   0x4UL

Bit mask for WDOG_PCH0_PRSCTRL

Definition at line 178 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT   2

Shift value for WDOG_PCH0_PRSCTRL

Definition at line 177 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_SYNCBUSY

Definition at line 184 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK   0x8UL

Bit mask for WDOG_PCH1_PRSCTRL

Definition at line 183 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT   3

Shift value for WDOG_PCH1_PRSCTRL

Definition at line 182 of file efm32jg1b_wdog.h .

#define _WDOG_SYNCBUSY_RESETVALUE   0x00000000UL

Default value for WDOG_SYNCBUSY

Definition at line 164 of file efm32jg1b_wdog.h .

#define WDOG_CMD_CLEAR   (0x1UL << 0)

Watchdog Timer Clear

Definition at line 153 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Feed() .

#define WDOG_CMD_CLEAR_CLEARED   ( _WDOG_CMD_CLEAR_CLEARED << 0)

Shifted mode CLEARED for WDOG_CMD

Definition at line 161 of file efm32jg1b_wdog.h .

#define WDOG_CMD_CLEAR_DEFAULT   ( _WDOG_CMD_CLEAR_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_CMD

Definition at line 159 of file efm32jg1b_wdog.h .

#define WDOG_CMD_CLEAR_UNCHANGED   ( _WDOG_CMD_CLEAR_UNCHANGED << 0)

Shifted mode UNCHANGED for WDOG_CMD

Definition at line 160 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_CLKSEL_DEFAULT   ( _WDOG_CTRL_CLKSEL_DEFAULT << 12)

Shifted mode DEFAULT for WDOG_CTRL

Definition at line 119 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_CLKSEL_LFRCO   ( _WDOG_CTRL_CLKSEL_LFRCO << 12)

Shifted mode LFRCO for WDOG_CTRL

Definition at line 121 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_CLKSEL_LFXO   ( _WDOG_CTRL_CLKSEL_LFXO << 12)

Shifted mode LFXO for WDOG_CTRL

Definition at line 122 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_CLKSEL_ULFRCO   ( _WDOG_CTRL_CLKSEL_ULFRCO << 12)

Shifted mode ULFRCO for WDOG_CTRL

Definition at line 120 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_CLRSRC   (0x1UL << 30)

Watchdog Clear Source

Definition at line 131 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_CLRSRC_DEFAULT   ( _WDOG_CTRL_CLRSRC_DEFAULT << 30)

Shifted mode DEFAULT for WDOG_CTRL

Definition at line 137 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_CLRSRC_PCH0   ( _WDOG_CTRL_CLRSRC_PCH0 << 30)

Shifted mode PCH0 for WDOG_CTRL

Definition at line 139 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_CLRSRC_SW   ( _WDOG_CTRL_CLRSRC_SW << 30)

Shifted mode SW for WDOG_CTRL

Definition at line 138 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_DEBUGRUN   (0x1UL << 1)

Debug Mode Run Enable

Definition at line 79 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Init() .

#define WDOG_CTRL_DEBUGRUN_DEFAULT   ( _WDOG_CTRL_DEBUGRUN_DEFAULT << 1)

Shifted mode DEFAULT for WDOG_CTRL

Definition at line 83 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_EM2RUN   (0x1UL << 2)

Energy Mode 2 Run Enable

Definition at line 84 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Init() .

#define WDOG_CTRL_EM2RUN_DEFAULT   ( _WDOG_CTRL_EM2RUN_DEFAULT << 2)

Shifted mode DEFAULT for WDOG_CTRL

Definition at line 88 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_EM3RUN   (0x1UL << 3)

Energy Mode 3 Run Enable

Definition at line 89 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Init() .

#define WDOG_CTRL_EM3RUN_DEFAULT   ( _WDOG_CTRL_EM3RUN_DEFAULT << 3)

Shifted mode DEFAULT for WDOG_CTRL

Definition at line 93 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_EM4BLOCK   (0x1UL << 5)

Energy Mode 4 Block

Definition at line 99 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Init() .

#define WDOG_CTRL_EM4BLOCK_DEFAULT   ( _WDOG_CTRL_EM4BLOCK_DEFAULT << 5)

Shifted mode DEFAULT for WDOG_CTRL

Definition at line 103 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_EN   (0x1UL << 0)

Watchdog Timer Enable

Definition at line 74 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Feed() , and WDOGn_Init() .

#define WDOG_CTRL_EN_DEFAULT   ( _WDOG_CTRL_EN_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_CTRL

Definition at line 78 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_LOCK   (0x1UL << 4)

Configuration Lock

Definition at line 94 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Enable() , and WDOGn_Init() .

#define WDOG_CTRL_LOCK_DEFAULT   ( _WDOG_CTRL_LOCK_DEFAULT << 4)

Shifted mode DEFAULT for WDOG_CTRL

Definition at line 98 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_PERSEL_DEFAULT   ( _WDOG_CTRL_PERSEL_DEFAULT << 8)

Shifted mode DEFAULT for WDOG_CTRL

Definition at line 112 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_SWOSCBLOCK   (0x1UL << 6)

Software Oscillator Disable Block

Definition at line 104 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Init() .

#define WDOG_CTRL_SWOSCBLOCK_DEFAULT   ( _WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6)

Shifted mode DEFAULT for WDOG_CTRL

Definition at line 108 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_WARNSEL_DEFAULT   ( _WDOG_CTRL_WARNSEL_DEFAULT << 16)

Shifted mode DEFAULT for WDOG_CTRL

Definition at line 126 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_WDOGRSTDIS   (0x1UL << 31)

Watchdog Reset Disable

Definition at line 140 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Init() .

#define WDOG_CTRL_WDOGRSTDIS_DEFAULT   ( _WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31)

Shifted mode DEFAULT for WDOG_CTRL

Definition at line 146 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_WDOGRSTDIS_DIS   ( _WDOG_CTRL_WDOGRSTDIS_DIS << 31)

Shifted mode DIS for WDOG_CTRL

Definition at line 148 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_WDOGRSTDIS_EN   ( _WDOG_CTRL_WDOGRSTDIS_EN << 31)

Shifted mode EN for WDOG_CTRL

Definition at line 147 of file efm32jg1b_wdog.h .

#define WDOG_CTRL_WINSEL_DEFAULT   ( _WDOG_CTRL_WINSEL_DEFAULT << 24)

Shifted mode DEFAULT for WDOG_CTRL

Definition at line 130 of file efm32jg1b_wdog.h .

#define WDOG_IEN_PEM0   (0x1UL << 3)

PEM0 Interrupt Enable

Definition at line 329 of file efm32jg1b_wdog.h .

#define WDOG_IEN_PEM0_DEFAULT   ( _WDOG_IEN_PEM0_DEFAULT << 3)

Shifted mode DEFAULT for WDOG_IEN

Definition at line 333 of file efm32jg1b_wdog.h .

#define WDOG_IEN_PEM1   (0x1UL << 4)

PEM1 Interrupt Enable

Definition at line 334 of file efm32jg1b_wdog.h .

#define WDOG_IEN_PEM1_DEFAULT   ( _WDOG_IEN_PEM1_DEFAULT << 4)

Shifted mode DEFAULT for WDOG_IEN

Definition at line 338 of file efm32jg1b_wdog.h .

#define WDOG_IEN_TOUT   (0x1UL << 0)

TOUT Interrupt Enable

Definition at line 314 of file efm32jg1b_wdog.h .

#define WDOG_IEN_TOUT_DEFAULT   ( _WDOG_IEN_TOUT_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_IEN

Definition at line 318 of file efm32jg1b_wdog.h .

#define WDOG_IEN_WARN   (0x1UL << 1)

WARN Interrupt Enable

Definition at line 319 of file efm32jg1b_wdog.h .

#define WDOG_IEN_WARN_DEFAULT   ( _WDOG_IEN_WARN_DEFAULT << 1)

Shifted mode DEFAULT for WDOG_IEN

Definition at line 323 of file efm32jg1b_wdog.h .

#define WDOG_IEN_WIN   (0x1UL << 2)

WIN Interrupt Enable

Definition at line 324 of file efm32jg1b_wdog.h .

#define WDOG_IEN_WIN_DEFAULT   ( _WDOG_IEN_WIN_DEFAULT << 2)

Shifted mode DEFAULT for WDOG_IEN

Definition at line 328 of file efm32jg1b_wdog.h .

#define WDOG_IF_PEM0   (0x1UL << 3)

PRS Channel Zero Event Missing Interrupt Flag

Definition at line 242 of file efm32jg1b_wdog.h .

#define WDOG_IF_PEM0_DEFAULT   ( _WDOG_IF_PEM0_DEFAULT << 3)

Shifted mode DEFAULT for WDOG_IF

Definition at line 246 of file efm32jg1b_wdog.h .

#define WDOG_IF_PEM1   (0x1UL << 4)

PRS Channel One Event Missing Interrupt Flag

Definition at line 247 of file efm32jg1b_wdog.h .

#define WDOG_IF_PEM1_DEFAULT   ( _WDOG_IF_PEM1_DEFAULT << 4)

Shifted mode DEFAULT for WDOG_IF

Definition at line 251 of file efm32jg1b_wdog.h .

#define WDOG_IF_TOUT   (0x1UL << 0)

WDOG Timeout Interrupt Flag

Definition at line 227 of file efm32jg1b_wdog.h .

#define WDOG_IF_TOUT_DEFAULT   ( _WDOG_IF_TOUT_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_IF

Definition at line 231 of file efm32jg1b_wdog.h .

#define WDOG_IF_WARN   (0x1UL << 1)

WDOG Warning Timeout Interrupt Flag

Definition at line 232 of file efm32jg1b_wdog.h .

#define WDOG_IF_WARN_DEFAULT   ( _WDOG_IF_WARN_DEFAULT << 1)

Shifted mode DEFAULT for WDOG_IF

Definition at line 236 of file efm32jg1b_wdog.h .

#define WDOG_IF_WIN   (0x1UL << 2)

WDOG Window Interrupt Flag

Definition at line 237 of file efm32jg1b_wdog.h .

#define WDOG_IF_WIN_DEFAULT   ( _WDOG_IF_WIN_DEFAULT << 2)

Shifted mode DEFAULT for WDOG_IF

Definition at line 241 of file efm32jg1b_wdog.h .

#define WDOG_IFC_PEM0   (0x1UL << 3)

Clear PEM0 Interrupt Flag

Definition at line 300 of file efm32jg1b_wdog.h .

#define WDOG_IFC_PEM0_DEFAULT   ( _WDOG_IFC_PEM0_DEFAULT << 3)

Shifted mode DEFAULT for WDOG_IFC

Definition at line 304 of file efm32jg1b_wdog.h .

#define WDOG_IFC_PEM1   (0x1UL << 4)

Clear PEM1 Interrupt Flag

Definition at line 305 of file efm32jg1b_wdog.h .

#define WDOG_IFC_PEM1_DEFAULT   ( _WDOG_IFC_PEM1_DEFAULT << 4)

Shifted mode DEFAULT for WDOG_IFC

Definition at line 309 of file efm32jg1b_wdog.h .

#define WDOG_IFC_TOUT   (0x1UL << 0)

Clear TOUT Interrupt Flag

Definition at line 285 of file efm32jg1b_wdog.h .

#define WDOG_IFC_TOUT_DEFAULT   ( _WDOG_IFC_TOUT_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_IFC

Definition at line 289 of file efm32jg1b_wdog.h .

#define WDOG_IFC_WARN   (0x1UL << 1)

Clear WARN Interrupt Flag

Definition at line 290 of file efm32jg1b_wdog.h .

#define WDOG_IFC_WARN_DEFAULT   ( _WDOG_IFC_WARN_DEFAULT << 1)

Shifted mode DEFAULT for WDOG_IFC

Definition at line 294 of file efm32jg1b_wdog.h .

#define WDOG_IFC_WIN   (0x1UL << 2)

Clear WIN Interrupt Flag

Definition at line 295 of file efm32jg1b_wdog.h .

#define WDOG_IFC_WIN_DEFAULT   ( _WDOG_IFC_WIN_DEFAULT << 2)

Shifted mode DEFAULT for WDOG_IFC

Definition at line 299 of file efm32jg1b_wdog.h .

#define WDOG_IFS_PEM0   (0x1UL << 3)

Set PEM0 Interrupt Flag

Definition at line 271 of file efm32jg1b_wdog.h .

#define WDOG_IFS_PEM0_DEFAULT   ( _WDOG_IFS_PEM0_DEFAULT << 3)

Shifted mode DEFAULT for WDOG_IFS

Definition at line 275 of file efm32jg1b_wdog.h .

#define WDOG_IFS_PEM1   (0x1UL << 4)

Set PEM1 Interrupt Flag

Definition at line 276 of file efm32jg1b_wdog.h .

#define WDOG_IFS_PEM1_DEFAULT   ( _WDOG_IFS_PEM1_DEFAULT << 4)

Shifted mode DEFAULT for WDOG_IFS

Definition at line 280 of file efm32jg1b_wdog.h .

#define WDOG_IFS_TOUT   (0x1UL << 0)

Set TOUT Interrupt Flag

Definition at line 256 of file efm32jg1b_wdog.h .

#define WDOG_IFS_TOUT_DEFAULT   ( _WDOG_IFS_TOUT_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_IFS

Definition at line 260 of file efm32jg1b_wdog.h .

#define WDOG_IFS_WARN   (0x1UL << 1)

Set WARN Interrupt Flag

Definition at line 261 of file efm32jg1b_wdog.h .

#define WDOG_IFS_WARN_DEFAULT   ( _WDOG_IFS_WARN_DEFAULT << 1)

Shifted mode DEFAULT for WDOG_IFS

Definition at line 265 of file efm32jg1b_wdog.h .

#define WDOG_IFS_WIN   (0x1UL << 2)

Set WIN Interrupt Flag

Definition at line 266 of file efm32jg1b_wdog.h .

#define WDOG_IFS_WIN_DEFAULT   ( _WDOG_IFS_WIN_DEFAULT << 2)

Shifted mode DEFAULT for WDOG_IFS

Definition at line 270 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN   (0x1UL << 8)

PRS Missing Event Will Trigger a Watchdog Reset

Definition at line 218 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT   ( _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8)

Shifted mode DEFAULT for WDOG_PCH_PRSCTRL

Definition at line 222 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT   ( _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_PCH_PRSCTRL

Definition at line 205 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0   ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0)

Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL

Definition at line 206 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1   ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0)

Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL

Definition at line 207 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10   ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0)

Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL

Definition at line 216 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11   ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0)

Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL

Definition at line 217 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2   ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0)

Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL

Definition at line 208 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3   ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0)

Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL

Definition at line 209 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4   ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0)

Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL

Definition at line 210 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5   ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0)

Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL

Definition at line 211 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6   ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0)

Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL

Definition at line 212 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7   ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0)

Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL

Definition at line 213 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8   ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0)

Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL

Definition at line 214 of file efm32jg1b_wdog.h .

#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9   ( _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0)

Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL

Definition at line 215 of file efm32jg1b_wdog.h .

#define WDOG_SYNCBUSY_CMD   (0x1UL << 1)

CMD Register Busy

Definition at line 171 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Feed() .

#define WDOG_SYNCBUSY_CMD_DEFAULT   ( _WDOG_SYNCBUSY_CMD_DEFAULT << 1)

Shifted mode DEFAULT for WDOG_SYNCBUSY

Definition at line 175 of file efm32jg1b_wdog.h .

#define WDOG_SYNCBUSY_CTRL   (0x1UL << 0)

CTRL Register Busy

Definition at line 166 of file efm32jg1b_wdog.h .

Referenced by WDOGn_Enable() , WDOGn_Feed() , WDOGn_Init() , and WDOGn_Lock() .

#define WDOG_SYNCBUSY_CTRL_DEFAULT   ( _WDOG_SYNCBUSY_CTRL_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_SYNCBUSY

Definition at line 170 of file efm32jg1b_wdog.h .

#define WDOG_SYNCBUSY_PCH0_PRSCTRL   (0x1UL << 2)

PCH0_PRSCTRL Register Busy

Definition at line 176 of file efm32jg1b_wdog.h .

#define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT   ( _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2)

Shifted mode DEFAULT for WDOG_SYNCBUSY

Definition at line 180 of file efm32jg1b_wdog.h .

#define WDOG_SYNCBUSY_PCH1_PRSCTRL   (0x1UL << 3)

PCH1_PRSCTRL Register Busy

Definition at line 181 of file efm32jg1b_wdog.h .

#define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT   ( _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3)

Shifted mode DEFAULT for WDOG_SYNCBUSY

Definition at line 185 of file efm32jg1b_wdog.h .