MSC Bit FieldsDevices > MSC

Macros

#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL
#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL
#define _MSC_ADDRB_ADDRB_SHIFT 0
#define _MSC_ADDRB_MASK 0xFFFFFFFFUL
#define _MSC_ADDRB_RESETVALUE 0x00000000UL
#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL
#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL
#define _MSC_CACHECMD_INVCACHE_SHIFT 0
#define _MSC_CACHECMD_MASK 0x00000007UL
#define _MSC_CACHECMD_RESETVALUE 0x00000000UL
#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL
#define _MSC_CACHECMD_STARTPC_MASK 0x2UL
#define _MSC_CACHECMD_STARTPC_SHIFT 1
#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL
#define _MSC_CACHECMD_STOPPC_MASK 0x4UL
#define _MSC_CACHECMD_STOPPC_SHIFT 2
#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL
#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL
#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0
#define _MSC_CACHEHITS_MASK 0x000FFFFFUL
#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL
#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL
#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL
#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0
#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL
#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL
#define _MSC_CMD_MASK 0x00000001UL
#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL
#define _MSC_CMD_PWRUP_MASK 0x1UL
#define _MSC_CMD_PWRUP_SHIFT 0
#define _MSC_CMD_RESETVALUE 0x00000000UL
#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL
#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL
#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0
#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL
#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL
#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1
#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL
#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL
#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3
#define _MSC_CTRL_MASK 0x0000000FUL
#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL
#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL
#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2
#define _MSC_CTRL_RESETVALUE 0x00000001UL
#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL
#define _MSC_IEN_CHOF_MASK 0x4UL
#define _MSC_IEN_CHOF_SHIFT 2
#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL
#define _MSC_IEN_CMOF_MASK 0x8UL
#define _MSC_IEN_CMOF_SHIFT 3
#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL
#define _MSC_IEN_ERASE_MASK 0x1UL
#define _MSC_IEN_ERASE_SHIFT 0
#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL
#define _MSC_IEN_ICACHERR_MASK 0x20UL
#define _MSC_IEN_ICACHERR_SHIFT 5
#define _MSC_IEN_MASK 0x0000003FUL
#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL
#define _MSC_IEN_PWRUPF_MASK 0x10UL
#define _MSC_IEN_PWRUPF_SHIFT 4
#define _MSC_IEN_RESETVALUE 0x00000000UL
#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL
#define _MSC_IEN_WRITE_MASK 0x2UL
#define _MSC_IEN_WRITE_SHIFT 1
#define _MSC_IF_CHOF_DEFAULT 0x00000000UL
#define _MSC_IF_CHOF_MASK 0x4UL
#define _MSC_IF_CHOF_SHIFT 2
#define _MSC_IF_CMOF_DEFAULT 0x00000000UL
#define _MSC_IF_CMOF_MASK 0x8UL
#define _MSC_IF_CMOF_SHIFT 3
#define _MSC_IF_ERASE_DEFAULT 0x00000000UL
#define _MSC_IF_ERASE_MASK 0x1UL
#define _MSC_IF_ERASE_SHIFT 0
#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL
#define _MSC_IF_ICACHERR_MASK 0x20UL
#define _MSC_IF_ICACHERR_SHIFT 5
#define _MSC_IF_MASK 0x0000003FUL
#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL
#define _MSC_IF_PWRUPF_MASK 0x10UL
#define _MSC_IF_PWRUPF_SHIFT 4
#define _MSC_IF_RESETVALUE 0x00000000UL
#define _MSC_IF_WRITE_DEFAULT 0x00000000UL
#define _MSC_IF_WRITE_MASK 0x2UL
#define _MSC_IF_WRITE_SHIFT 1
#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL
#define _MSC_IFC_CHOF_MASK 0x4UL
#define _MSC_IFC_CHOF_SHIFT 2
#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL
#define _MSC_IFC_CMOF_MASK 0x8UL
#define _MSC_IFC_CMOF_SHIFT 3
#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL
#define _MSC_IFC_ERASE_MASK 0x1UL
#define _MSC_IFC_ERASE_SHIFT 0
#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL
#define _MSC_IFC_ICACHERR_MASK 0x20UL
#define _MSC_IFC_ICACHERR_SHIFT 5
#define _MSC_IFC_MASK 0x0000003FUL
#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL
#define _MSC_IFC_PWRUPF_MASK 0x10UL
#define _MSC_IFC_PWRUPF_SHIFT 4
#define _MSC_IFC_RESETVALUE 0x00000000UL
#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL
#define _MSC_IFC_WRITE_MASK 0x2UL
#define _MSC_IFC_WRITE_SHIFT 1
#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL
#define _MSC_IFS_CHOF_MASK 0x4UL
#define _MSC_IFS_CHOF_SHIFT 2
#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL
#define _MSC_IFS_CMOF_MASK 0x8UL
#define _MSC_IFS_CMOF_SHIFT 3
#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL
#define _MSC_IFS_ERASE_MASK 0x1UL
#define _MSC_IFS_ERASE_SHIFT 0
#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL
#define _MSC_IFS_ICACHERR_MASK 0x20UL
#define _MSC_IFS_ICACHERR_SHIFT 5
#define _MSC_IFS_MASK 0x0000003FUL
#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL
#define _MSC_IFS_PWRUPF_MASK 0x10UL
#define _MSC_IFS_PWRUPF_SHIFT 4
#define _MSC_IFS_RESETVALUE 0x00000000UL
#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL
#define _MSC_IFS_WRITE_MASK 0x2UL
#define _MSC_IFS_WRITE_SHIFT 1
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL
#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL
#define _MSC_LOCK_LOCKKEY_SHIFT 0
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
#define _MSC_LOCK_MASK 0x0000FFFFUL
#define _MSC_LOCK_RESETVALUE 0x00000000UL
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL
#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL
#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL
#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL
#define _MSC_READCTRL_AIDIS_MASK 0x10UL
#define _MSC_READCTRL_AIDIS_SHIFT 4
#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL
#define _MSC_READCTRL_ICCDIS_MASK 0x20UL
#define _MSC_READCTRL_ICCDIS_SHIFT 5
#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL
#define _MSC_READCTRL_IFCDIS_MASK 0x8UL
#define _MSC_READCTRL_IFCDIS_SHIFT 3
#define _MSC_READCTRL_MASK 0x13000338UL
#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL
#define _MSC_READCTRL_MODE_MASK 0x3000000UL
#define _MSC_READCTRL_MODE_SHIFT 24
#define _MSC_READCTRL_MODE_WS0 0x00000000UL
#define _MSC_READCTRL_MODE_WS1 0x00000001UL
#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL
#define _MSC_READCTRL_PREFETCH_MASK 0x100UL
#define _MSC_READCTRL_PREFETCH_SHIFT 8
#define _MSC_READCTRL_RESETVALUE 0x01000100UL
#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL
#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL
#define _MSC_READCTRL_SCBTP_SHIFT 28
#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL
#define _MSC_READCTRL_USEHPROT_MASK 0x200UL
#define _MSC_READCTRL_USEHPROT_SHIFT 9
#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL
#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL
#define _MSC_STARTUP_ASTWAIT_SHIFT 24
#define _MSC_STARTUP_MASK 0x773FF3FFUL
#define _MSC_STARTUP_RESETVALUE 0x1300104DUL
#define _MSC_STARTUP_STDLY0_DEFAULT 0x0000004DUL
#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL
#define _MSC_STARTUP_STDLY0_SHIFT 0
#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL
#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL
#define _MSC_STARTUP_STDLY1_SHIFT 12
#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL
#define _MSC_STARTUP_STWS_MASK 0x70000000UL
#define _MSC_STARTUP_STWS_SHIFT 28
#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL
#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL
#define _MSC_STARTUP_STWSAEN_SHIFT 26
#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL
#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL
#define _MSC_STARTUP_STWSEN_SHIFT 25
#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL
#define _MSC_STATUS_BUSY_MASK 0x1UL
#define _MSC_STATUS_BUSY_SHIFT 0
#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL
#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL
#define _MSC_STATUS_ERASEABORTED_SHIFT 5
#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL
#define _MSC_STATUS_INVADDR_MASK 0x4UL
#define _MSC_STATUS_INVADDR_SHIFT 2
#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL
#define _MSC_STATUS_LOCKED_MASK 0x2UL
#define _MSC_STATUS_LOCKED_SHIFT 1
#define _MSC_STATUS_MASK 0x0000007FUL
#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL
#define _MSC_STATUS_PCRUNNING_MASK 0x40UL
#define _MSC_STATUS_PCRUNNING_SHIFT 6
#define _MSC_STATUS_RESETVALUE 0x00000008UL
#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL
#define _MSC_STATUS_WDATAREADY_MASK 0x8UL
#define _MSC_STATUS_WDATAREADY_SHIFT 3
#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL
#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL
#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4
#define _MSC_WDATA_MASK 0xFFFFFFFFUL
#define _MSC_WDATA_RESETVALUE 0x00000000UL
#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL
#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL
#define _MSC_WDATA_WDATA_SHIFT 0
#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL
#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12
#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL
#define _MSC_WRITECMD_ERASEABORT_SHIFT 5
#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL
#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8
#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL
#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1
#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL
#define _MSC_WRITECMD_LADDRIM_SHIFT 0
#define _MSC_WRITECMD_MASK 0x0000113FUL
#define _MSC_WRITECMD_RESETVALUE 0x00000000UL
#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL
#define _MSC_WRITECMD_WRITEEND_SHIFT 2
#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL
#define _MSC_WRITECMD_WRITEONCE_SHIFT 3
#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL
#define _MSC_WRITECMD_WRITETRIG_SHIFT 4
#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL
#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL
#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1
#define _MSC_WRITECTRL_MASK 0x00000003UL
#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL
#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL
#define _MSC_WRITECTRL_WREN_MASK 0x1UL
#define _MSC_WRITECTRL_WREN_SHIFT 0
#define MSC_ADDRB_ADDRB_DEFAULT ( _MSC_ADDRB_ADDRB_DEFAULT << 0)
#define MSC_CACHECMD_INVCACHE (0x1UL << 0)
#define MSC_CACHECMD_INVCACHE_DEFAULT ( _MSC_CACHECMD_INVCACHE_DEFAULT << 0)
#define MSC_CACHECMD_STARTPC (0x1UL << 1)
#define MSC_CACHECMD_STARTPC_DEFAULT ( _MSC_CACHECMD_STARTPC_DEFAULT << 1)
#define MSC_CACHECMD_STOPPC (0x1UL << 2)
#define MSC_CACHECMD_STOPPC_DEFAULT ( _MSC_CACHECMD_STOPPC_DEFAULT << 2)
#define MSC_CACHEHITS_CACHEHITS_DEFAULT ( _MSC_CACHEHITS_CACHEHITS_DEFAULT << 0)
#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT ( _MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0)
#define MSC_CMD_PWRUP (0x1UL << 0)
#define MSC_CMD_PWRUP_DEFAULT ( _MSC_CMD_PWRUP_DEFAULT << 0)
#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0)
#define MSC_CTRL_ADDRFAULTEN_DEFAULT ( _MSC_CTRL_ADDRFAULTEN_DEFAULT << 0)
#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1)
#define MSC_CTRL_CLKDISFAULTEN_DEFAULT ( _MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1)
#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3)
#define MSC_CTRL_IFCREADCLEAR_DEFAULT ( _MSC_CTRL_IFCREADCLEAR_DEFAULT << 3)
#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2)
#define MSC_CTRL_PWRUPONDEMAND_DEFAULT ( _MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2)
#define MSC_IEN_CHOF (0x1UL << 2)
#define MSC_IEN_CHOF_DEFAULT ( _MSC_IEN_CHOF_DEFAULT << 2)
#define MSC_IEN_CMOF (0x1UL << 3)
#define MSC_IEN_CMOF_DEFAULT ( _MSC_IEN_CMOF_DEFAULT << 3)
#define MSC_IEN_ERASE (0x1UL << 0)
#define MSC_IEN_ERASE_DEFAULT ( _MSC_IEN_ERASE_DEFAULT << 0)
#define MSC_IEN_ICACHERR (0x1UL << 5)
#define MSC_IEN_ICACHERR_DEFAULT ( _MSC_IEN_ICACHERR_DEFAULT << 5)
#define MSC_IEN_PWRUPF (0x1UL << 4)
#define MSC_IEN_PWRUPF_DEFAULT ( _MSC_IEN_PWRUPF_DEFAULT << 4)
#define MSC_IEN_WRITE (0x1UL << 1)
#define MSC_IEN_WRITE_DEFAULT ( _MSC_IEN_WRITE_DEFAULT << 1)
#define MSC_IF_CHOF (0x1UL << 2)
#define MSC_IF_CHOF_DEFAULT ( _MSC_IF_CHOF_DEFAULT << 2)
#define MSC_IF_CMOF (0x1UL << 3)
#define MSC_IF_CMOF_DEFAULT ( _MSC_IF_CMOF_DEFAULT << 3)
#define MSC_IF_ERASE (0x1UL << 0)
#define MSC_IF_ERASE_DEFAULT ( _MSC_IF_ERASE_DEFAULT << 0)
#define MSC_IF_ICACHERR (0x1UL << 5)
#define MSC_IF_ICACHERR_DEFAULT ( _MSC_IF_ICACHERR_DEFAULT << 5)
#define MSC_IF_PWRUPF (0x1UL << 4)
#define MSC_IF_PWRUPF_DEFAULT ( _MSC_IF_PWRUPF_DEFAULT << 4)
#define MSC_IF_WRITE (0x1UL << 1)
#define MSC_IF_WRITE_DEFAULT ( _MSC_IF_WRITE_DEFAULT << 1)
#define MSC_IFC_CHOF (0x1UL << 2)
#define MSC_IFC_CHOF_DEFAULT ( _MSC_IFC_CHOF_DEFAULT << 2)
#define MSC_IFC_CMOF (0x1UL << 3)
#define MSC_IFC_CMOF_DEFAULT ( _MSC_IFC_CMOF_DEFAULT << 3)
#define MSC_IFC_ERASE (0x1UL << 0)
#define MSC_IFC_ERASE_DEFAULT ( _MSC_IFC_ERASE_DEFAULT << 0)
#define MSC_IFC_ICACHERR (0x1UL << 5)
#define MSC_IFC_ICACHERR_DEFAULT ( _MSC_IFC_ICACHERR_DEFAULT << 5)
#define MSC_IFC_PWRUPF (0x1UL << 4)
#define MSC_IFC_PWRUPF_DEFAULT ( _MSC_IFC_PWRUPF_DEFAULT << 4)
#define MSC_IFC_WRITE (0x1UL << 1)
#define MSC_IFC_WRITE_DEFAULT ( _MSC_IFC_WRITE_DEFAULT << 1)
#define MSC_IFS_CHOF (0x1UL << 2)
#define MSC_IFS_CHOF_DEFAULT ( _MSC_IFS_CHOF_DEFAULT << 2)
#define MSC_IFS_CMOF (0x1UL << 3)
#define MSC_IFS_CMOF_DEFAULT ( _MSC_IFS_CMOF_DEFAULT << 3)
#define MSC_IFS_ERASE (0x1UL << 0)
#define MSC_IFS_ERASE_DEFAULT ( _MSC_IFS_ERASE_DEFAULT << 0)
#define MSC_IFS_ICACHERR (0x1UL << 5)
#define MSC_IFS_ICACHERR_DEFAULT ( _MSC_IFS_ICACHERR_DEFAULT << 5)
#define MSC_IFS_PWRUPF (0x1UL << 4)
#define MSC_IFS_PWRUPF_DEFAULT ( _MSC_IFS_PWRUPF_DEFAULT << 4)
#define MSC_IFS_WRITE (0x1UL << 1)
#define MSC_IFS_WRITE_DEFAULT ( _MSC_IFS_WRITE_DEFAULT << 1)
#define MSC_LOCK_LOCKKEY_DEFAULT ( _MSC_LOCK_LOCKKEY_DEFAULT << 0)
#define MSC_LOCK_LOCKKEY_LOCK ( _MSC_LOCK_LOCKKEY_LOCK << 0)
#define MSC_LOCK_LOCKKEY_LOCKED ( _MSC_LOCK_LOCKKEY_LOCKED << 0)
#define MSC_LOCK_LOCKKEY_UNLOCK ( _MSC_LOCK_LOCKKEY_UNLOCK << 0)
#define MSC_LOCK_LOCKKEY_UNLOCKED ( _MSC_LOCK_LOCKKEY_UNLOCKED << 0)
#define MSC_MASSLOCK_LOCKKEY_DEFAULT ( _MSC_MASSLOCK_LOCKKEY_DEFAULT << 0)
#define MSC_MASSLOCK_LOCKKEY_LOCK ( _MSC_MASSLOCK_LOCKKEY_LOCK << 0)
#define MSC_MASSLOCK_LOCKKEY_LOCKED ( _MSC_MASSLOCK_LOCKKEY_LOCKED << 0)
#define MSC_MASSLOCK_LOCKKEY_UNLOCK ( _MSC_MASSLOCK_LOCKKEY_UNLOCK << 0)
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED ( _MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0)
#define MSC_READCTRL_AIDIS (0x1UL << 4)
#define MSC_READCTRL_AIDIS_DEFAULT ( _MSC_READCTRL_AIDIS_DEFAULT << 4)
#define MSC_READCTRL_ICCDIS (0x1UL << 5)
#define MSC_READCTRL_ICCDIS_DEFAULT ( _MSC_READCTRL_ICCDIS_DEFAULT << 5)
#define MSC_READCTRL_IFCDIS (0x1UL << 3)
#define MSC_READCTRL_IFCDIS_DEFAULT ( _MSC_READCTRL_IFCDIS_DEFAULT << 3)
#define MSC_READCTRL_MODE_DEFAULT ( _MSC_READCTRL_MODE_DEFAULT << 24)
#define MSC_READCTRL_MODE_WS0 ( _MSC_READCTRL_MODE_WS0 << 24)
#define MSC_READCTRL_MODE_WS1 ( _MSC_READCTRL_MODE_WS1 << 24)
#define MSC_READCTRL_PREFETCH (0x1UL << 8)
#define MSC_READCTRL_PREFETCH_DEFAULT ( _MSC_READCTRL_PREFETCH_DEFAULT << 8)
#define MSC_READCTRL_SCBTP (0x1UL << 28)
#define MSC_READCTRL_SCBTP_DEFAULT ( _MSC_READCTRL_SCBTP_DEFAULT << 28)
#define MSC_READCTRL_USEHPROT (0x1UL << 9)
#define MSC_READCTRL_USEHPROT_DEFAULT ( _MSC_READCTRL_USEHPROT_DEFAULT << 9)
#define MSC_STARTUP_ASTWAIT (0x1UL << 24)
#define MSC_STARTUP_ASTWAIT_DEFAULT ( _MSC_STARTUP_ASTWAIT_DEFAULT << 24)
#define MSC_STARTUP_STDLY0_DEFAULT ( _MSC_STARTUP_STDLY0_DEFAULT << 0)
#define MSC_STARTUP_STDLY1_DEFAULT ( _MSC_STARTUP_STDLY1_DEFAULT << 12)
#define MSC_STARTUP_STWS_DEFAULT ( _MSC_STARTUP_STWS_DEFAULT << 28)
#define MSC_STARTUP_STWSAEN (0x1UL << 26)
#define MSC_STARTUP_STWSAEN_DEFAULT ( _MSC_STARTUP_STWSAEN_DEFAULT << 26)
#define MSC_STARTUP_STWSEN (0x1UL << 25)
#define MSC_STARTUP_STWSEN_DEFAULT ( _MSC_STARTUP_STWSEN_DEFAULT << 25)
#define MSC_STATUS_BUSY (0x1UL << 0)
#define MSC_STATUS_BUSY_DEFAULT ( _MSC_STATUS_BUSY_DEFAULT << 0)
#define MSC_STATUS_ERASEABORTED (0x1UL << 5)
#define MSC_STATUS_ERASEABORTED_DEFAULT ( _MSC_STATUS_ERASEABORTED_DEFAULT << 5)
#define MSC_STATUS_INVADDR (0x1UL << 2)
#define MSC_STATUS_INVADDR_DEFAULT ( _MSC_STATUS_INVADDR_DEFAULT << 2)
#define MSC_STATUS_LOCKED (0x1UL << 1)
#define MSC_STATUS_LOCKED_DEFAULT ( _MSC_STATUS_LOCKED_DEFAULT << 1)
#define MSC_STATUS_PCRUNNING (0x1UL << 6)
#define MSC_STATUS_PCRUNNING_DEFAULT ( _MSC_STATUS_PCRUNNING_DEFAULT << 6)
#define MSC_STATUS_WDATAREADY (0x1UL << 3)
#define MSC_STATUS_WDATAREADY_DEFAULT ( _MSC_STATUS_WDATAREADY_DEFAULT << 3)
#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4)
#define MSC_STATUS_WORDTIMEOUT_DEFAULT ( _MSC_STATUS_WORDTIMEOUT_DEFAULT << 4)
#define MSC_WDATA_WDATA_DEFAULT ( _MSC_WDATA_WDATA_DEFAULT << 0)
#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12)
#define MSC_WRITECMD_CLEARWDATA_DEFAULT ( _MSC_WRITECMD_CLEARWDATA_DEFAULT << 12)
#define MSC_WRITECMD_ERASEABORT (0x1UL << 5)
#define MSC_WRITECMD_ERASEABORT_DEFAULT ( _MSC_WRITECMD_ERASEABORT_DEFAULT << 5)
#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8)
#define MSC_WRITECMD_ERASEMAIN0_DEFAULT ( _MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8)
#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1)
#define MSC_WRITECMD_ERASEPAGE_DEFAULT ( _MSC_WRITECMD_ERASEPAGE_DEFAULT << 1)
#define MSC_WRITECMD_LADDRIM (0x1UL << 0)
#define MSC_WRITECMD_LADDRIM_DEFAULT ( _MSC_WRITECMD_LADDRIM_DEFAULT << 0)
#define MSC_WRITECMD_WRITEEND (0x1UL << 2)
#define MSC_WRITECMD_WRITEEND_DEFAULT ( _MSC_WRITECMD_WRITEEND_DEFAULT << 2)
#define MSC_WRITECMD_WRITEONCE (0x1UL << 3)
#define MSC_WRITECMD_WRITEONCE_DEFAULT ( _MSC_WRITECMD_WRITEONCE_DEFAULT << 3)
#define MSC_WRITECMD_WRITETRIG (0x1UL << 4)
#define MSC_WRITECMD_WRITETRIG_DEFAULT ( _MSC_WRITECMD_WRITETRIG_DEFAULT << 4)
#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1)
#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT ( _MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1)
#define MSC_WRITECTRL_WREN (0x1UL << 0)
#define MSC_WRITECTRL_WREN_DEFAULT ( _MSC_WRITECTRL_WREN_DEFAULT << 0)

Macro Definition Documentation

#define _MSC_ADDRB_ADDRB_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_ADDRB

Definition at line 215 of file efm32jg1b_msc.h .

#define _MSC_ADDRB_ADDRB_MASK   0xFFFFFFFFUL

Bit mask for MSC_ADDRB

Definition at line 214 of file efm32jg1b_msc.h .

#define _MSC_ADDRB_ADDRB_SHIFT   0

Shift value for MSC_ADDRB

Definition at line 213 of file efm32jg1b_msc.h .

#define _MSC_ADDRB_MASK   0xFFFFFFFFUL

Mask for MSC_ADDRB

Definition at line 212 of file efm32jg1b_msc.h .

#define _MSC_ADDRB_RESETVALUE   0x00000000UL

Default value for MSC_ADDRB

Definition at line 211 of file efm32jg1b_msc.h .

#define _MSC_CACHECMD_INVCACHE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CACHECMD

Definition at line 423 of file efm32jg1b_msc.h .

#define _MSC_CACHECMD_INVCACHE_MASK   0x1UL

Bit mask for MSC_INVCACHE

Definition at line 422 of file efm32jg1b_msc.h .

#define _MSC_CACHECMD_INVCACHE_SHIFT   0

Shift value for MSC_INVCACHE

Definition at line 421 of file efm32jg1b_msc.h .

#define _MSC_CACHECMD_MASK   0x00000007UL

Mask for MSC_CACHECMD

Definition at line 419 of file efm32jg1b_msc.h .

#define _MSC_CACHECMD_RESETVALUE   0x00000000UL

Default value for MSC_CACHECMD

Definition at line 418 of file efm32jg1b_msc.h .

#define _MSC_CACHECMD_STARTPC_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CACHECMD

Definition at line 428 of file efm32jg1b_msc.h .

#define _MSC_CACHECMD_STARTPC_MASK   0x2UL

Bit mask for MSC_STARTPC

Definition at line 427 of file efm32jg1b_msc.h .

#define _MSC_CACHECMD_STARTPC_SHIFT   1

Shift value for MSC_STARTPC

Definition at line 426 of file efm32jg1b_msc.h .

#define _MSC_CACHECMD_STOPPC_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CACHECMD

Definition at line 433 of file efm32jg1b_msc.h .

#define _MSC_CACHECMD_STOPPC_MASK   0x4UL

Bit mask for MSC_STOPPC

Definition at line 432 of file efm32jg1b_msc.h .

#define _MSC_CACHECMD_STOPPC_SHIFT   2

Shift value for MSC_STOPPC

Definition at line 431 of file efm32jg1b_msc.h .

#define _MSC_CACHEHITS_CACHEHITS_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CACHEHITS

Definition at line 441 of file efm32jg1b_msc.h .

#define _MSC_CACHEHITS_CACHEHITS_MASK   0xFFFFFUL

Bit mask for MSC_CACHEHITS

Definition at line 440 of file efm32jg1b_msc.h .

#define _MSC_CACHEHITS_CACHEHITS_SHIFT   0

Shift value for MSC_CACHEHITS

Definition at line 439 of file efm32jg1b_msc.h .

#define _MSC_CACHEHITS_MASK   0x000FFFFFUL

Mask for MSC_CACHEHITS

Definition at line 438 of file efm32jg1b_msc.h .

#define _MSC_CACHEHITS_RESETVALUE   0x00000000UL

Default value for MSC_CACHEHITS

Definition at line 437 of file efm32jg1b_msc.h .

#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CACHEMISSES

Definition at line 449 of file efm32jg1b_msc.h .

#define _MSC_CACHEMISSES_CACHEMISSES_MASK   0xFFFFFUL

Bit mask for MSC_CACHEMISSES

Definition at line 448 of file efm32jg1b_msc.h .

#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT   0

Shift value for MSC_CACHEMISSES

Definition at line 447 of file efm32jg1b_msc.h .

#define _MSC_CACHEMISSES_MASK   0x000FFFFFUL

Mask for MSC_CACHEMISSES

Definition at line 446 of file efm32jg1b_msc.h .

#define _MSC_CACHEMISSES_RESETVALUE   0x00000000UL

Default value for MSC_CACHEMISSES

Definition at line 445 of file efm32jg1b_msc.h .

#define _MSC_CMD_MASK   0x00000001UL

Mask for MSC_CMD

Definition at line 501 of file efm32jg1b_msc.h .

#define _MSC_CMD_PWRUP_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CMD

Definition at line 505 of file efm32jg1b_msc.h .

#define _MSC_CMD_PWRUP_MASK   0x1UL

Bit mask for MSC_PWRUP

Definition at line 504 of file efm32jg1b_msc.h .

#define _MSC_CMD_PWRUP_SHIFT   0

Shift value for MSC_PWRUP

Definition at line 503 of file efm32jg1b_msc.h .

#define _MSC_CMD_RESETVALUE   0x00000000UL

Default value for MSC_CMD

Definition at line 500 of file efm32jg1b_msc.h .

#define _MSC_CTRL_ADDRFAULTEN_DEFAULT   0x00000001UL

Mode DEFAULT for MSC_CTRL

Definition at line 92 of file efm32jg1b_msc.h .

#define _MSC_CTRL_ADDRFAULTEN_MASK   0x1UL

Bit mask for MSC_ADDRFAULTEN

Definition at line 91 of file efm32jg1b_msc.h .

#define _MSC_CTRL_ADDRFAULTEN_SHIFT   0

Shift value for MSC_ADDRFAULTEN

Definition at line 90 of file efm32jg1b_msc.h .

#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CTRL

Definition at line 97 of file efm32jg1b_msc.h .

#define _MSC_CTRL_CLKDISFAULTEN_MASK   0x2UL

Bit mask for MSC_CLKDISFAULTEN

Definition at line 96 of file efm32jg1b_msc.h .

#define _MSC_CTRL_CLKDISFAULTEN_SHIFT   1

Shift value for MSC_CLKDISFAULTEN

Definition at line 95 of file efm32jg1b_msc.h .

#define _MSC_CTRL_IFCREADCLEAR_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CTRL

Definition at line 107 of file efm32jg1b_msc.h .

#define _MSC_CTRL_IFCREADCLEAR_MASK   0x8UL

Bit mask for MSC_IFCREADCLEAR

Definition at line 106 of file efm32jg1b_msc.h .

#define _MSC_CTRL_IFCREADCLEAR_SHIFT   3

Shift value for MSC_IFCREADCLEAR

Definition at line 105 of file efm32jg1b_msc.h .

#define _MSC_CTRL_MASK   0x0000000FUL

Mask for MSC_CTRL

Definition at line 88 of file efm32jg1b_msc.h .

#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CTRL

Definition at line 102 of file efm32jg1b_msc.h .

#define _MSC_CTRL_PWRUPONDEMAND_MASK   0x4UL

Bit mask for MSC_PWRUPONDEMAND

Definition at line 101 of file efm32jg1b_msc.h .

#define _MSC_CTRL_PWRUPONDEMAND_SHIFT   2

Shift value for MSC_PWRUPONDEMAND

Definition at line 100 of file efm32jg1b_msc.h .

#define _MSC_CTRL_RESETVALUE   0x00000001UL

Default value for MSC_CTRL

Definition at line 87 of file efm32jg1b_msc.h .

#define _MSC_IEN_CHOF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 383 of file efm32jg1b_msc.h .

#define _MSC_IEN_CHOF_MASK   0x4UL

Bit mask for MSC_CHOF

Definition at line 382 of file efm32jg1b_msc.h .

#define _MSC_IEN_CHOF_SHIFT   2

Shift value for MSC_CHOF

Definition at line 381 of file efm32jg1b_msc.h .

#define _MSC_IEN_CMOF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 388 of file efm32jg1b_msc.h .

#define _MSC_IEN_CMOF_MASK   0x8UL

Bit mask for MSC_CMOF

Definition at line 387 of file efm32jg1b_msc.h .

#define _MSC_IEN_CMOF_SHIFT   3

Shift value for MSC_CMOF

Definition at line 386 of file efm32jg1b_msc.h .

#define _MSC_IEN_ERASE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 373 of file efm32jg1b_msc.h .

#define _MSC_IEN_ERASE_MASK   0x1UL

Bit mask for MSC_ERASE

Definition at line 372 of file efm32jg1b_msc.h .

#define _MSC_IEN_ERASE_SHIFT   0

Shift value for MSC_ERASE

Definition at line 371 of file efm32jg1b_msc.h .

#define _MSC_IEN_ICACHERR_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 398 of file efm32jg1b_msc.h .

#define _MSC_IEN_ICACHERR_MASK   0x20UL

Bit mask for MSC_ICACHERR

Definition at line 397 of file efm32jg1b_msc.h .

#define _MSC_IEN_ICACHERR_SHIFT   5

Shift value for MSC_ICACHERR

Definition at line 396 of file efm32jg1b_msc.h .

#define _MSC_IEN_MASK   0x0000003FUL

Mask for MSC_IEN

Definition at line 369 of file efm32jg1b_msc.h .

#define _MSC_IEN_PWRUPF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 393 of file efm32jg1b_msc.h .

#define _MSC_IEN_PWRUPF_MASK   0x10UL

Bit mask for MSC_PWRUPF

Definition at line 392 of file efm32jg1b_msc.h .

#define _MSC_IEN_PWRUPF_SHIFT   4

Shift value for MSC_PWRUPF

Definition at line 391 of file efm32jg1b_msc.h .

#define _MSC_IEN_RESETVALUE   0x00000000UL

Default value for MSC_IEN

Definition at line 368 of file efm32jg1b_msc.h .

#define _MSC_IEN_WRITE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 378 of file efm32jg1b_msc.h .

#define _MSC_IEN_WRITE_MASK   0x2UL

Bit mask for MSC_WRITE

Definition at line 377 of file efm32jg1b_msc.h .

#define _MSC_IEN_WRITE_SHIFT   1

Shift value for MSC_WRITE

Definition at line 376 of file efm32jg1b_msc.h .

#define _MSC_IF_CHOF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 281 of file efm32jg1b_msc.h .

#define _MSC_IF_CHOF_MASK   0x4UL

Bit mask for MSC_CHOF

Definition at line 280 of file efm32jg1b_msc.h .

#define _MSC_IF_CHOF_SHIFT   2

Shift value for MSC_CHOF

Definition at line 279 of file efm32jg1b_msc.h .

#define _MSC_IF_CMOF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 286 of file efm32jg1b_msc.h .

#define _MSC_IF_CMOF_MASK   0x8UL

Bit mask for MSC_CMOF

Definition at line 285 of file efm32jg1b_msc.h .

#define _MSC_IF_CMOF_SHIFT   3

Shift value for MSC_CMOF

Definition at line 284 of file efm32jg1b_msc.h .

#define _MSC_IF_ERASE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 271 of file efm32jg1b_msc.h .

#define _MSC_IF_ERASE_MASK   0x1UL

Bit mask for MSC_ERASE

Definition at line 270 of file efm32jg1b_msc.h .

#define _MSC_IF_ERASE_SHIFT   0

Shift value for MSC_ERASE

Definition at line 269 of file efm32jg1b_msc.h .

#define _MSC_IF_ICACHERR_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 296 of file efm32jg1b_msc.h .

#define _MSC_IF_ICACHERR_MASK   0x20UL

Bit mask for MSC_ICACHERR

Definition at line 295 of file efm32jg1b_msc.h .

#define _MSC_IF_ICACHERR_SHIFT   5

Shift value for MSC_ICACHERR

Definition at line 294 of file efm32jg1b_msc.h .

#define _MSC_IF_MASK   0x0000003FUL

Mask for MSC_IF

Definition at line 267 of file efm32jg1b_msc.h .

#define _MSC_IF_PWRUPF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 291 of file efm32jg1b_msc.h .

#define _MSC_IF_PWRUPF_MASK   0x10UL

Bit mask for MSC_PWRUPF

Definition at line 290 of file efm32jg1b_msc.h .

#define _MSC_IF_PWRUPF_SHIFT   4

Shift value for MSC_PWRUPF

Definition at line 289 of file efm32jg1b_msc.h .

#define _MSC_IF_RESETVALUE   0x00000000UL

Default value for MSC_IF

Definition at line 266 of file efm32jg1b_msc.h .

#define _MSC_IF_WRITE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 276 of file efm32jg1b_msc.h .

#define _MSC_IF_WRITE_MASK   0x2UL

Bit mask for MSC_WRITE

Definition at line 275 of file efm32jg1b_msc.h .

#define _MSC_IF_WRITE_SHIFT   1

Shift value for MSC_WRITE

Definition at line 274 of file efm32jg1b_msc.h .

#define _MSC_IFC_CHOF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IFC

Definition at line 349 of file efm32jg1b_msc.h .

#define _MSC_IFC_CHOF_MASK   0x4UL

Bit mask for MSC_CHOF

Definition at line 348 of file efm32jg1b_msc.h .

#define _MSC_IFC_CHOF_SHIFT   2

Shift value for MSC_CHOF

Definition at line 347 of file efm32jg1b_msc.h .

#define _MSC_IFC_CMOF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IFC

Definition at line 354 of file efm32jg1b_msc.h .

#define _MSC_IFC_CMOF_MASK   0x8UL

Bit mask for MSC_CMOF

Definition at line 353 of file efm32jg1b_msc.h .

#define _MSC_IFC_CMOF_SHIFT   3

Shift value for MSC_CMOF

Definition at line 352 of file efm32jg1b_msc.h .

#define _MSC_IFC_ERASE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IFC

Definition at line 339 of file efm32jg1b_msc.h .

#define _MSC_IFC_ERASE_MASK   0x1UL

Bit mask for MSC_ERASE

Definition at line 338 of file efm32jg1b_msc.h .

#define _MSC_IFC_ERASE_SHIFT   0

Shift value for MSC_ERASE

Definition at line 337 of file efm32jg1b_msc.h .

#define _MSC_IFC_ICACHERR_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IFC

Definition at line 364 of file efm32jg1b_msc.h .

#define _MSC_IFC_ICACHERR_MASK   0x20UL

Bit mask for MSC_ICACHERR

Definition at line 363 of file efm32jg1b_msc.h .

#define _MSC_IFC_ICACHERR_SHIFT   5

Shift value for MSC_ICACHERR

Definition at line 362 of file efm32jg1b_msc.h .

#define _MSC_IFC_MASK   0x0000003FUL

Mask for MSC_IFC

Definition at line 335 of file efm32jg1b_msc.h .

#define _MSC_IFC_PWRUPF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IFC

Definition at line 359 of file efm32jg1b_msc.h .

#define _MSC_IFC_PWRUPF_MASK   0x10UL

Bit mask for MSC_PWRUPF

Definition at line 358 of file efm32jg1b_msc.h .

#define _MSC_IFC_PWRUPF_SHIFT   4

Shift value for MSC_PWRUPF

Definition at line 357 of file efm32jg1b_msc.h .

#define _MSC_IFC_RESETVALUE   0x00000000UL

Default value for MSC_IFC

Definition at line 334 of file efm32jg1b_msc.h .

#define _MSC_IFC_WRITE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IFC

Definition at line 344 of file efm32jg1b_msc.h .

#define _MSC_IFC_WRITE_MASK   0x2UL

Bit mask for MSC_WRITE

Definition at line 343 of file efm32jg1b_msc.h .

#define _MSC_IFC_WRITE_SHIFT   1

Shift value for MSC_WRITE

Definition at line 342 of file efm32jg1b_msc.h .

#define _MSC_IFS_CHOF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IFS

Definition at line 315 of file efm32jg1b_msc.h .

#define _MSC_IFS_CHOF_MASK   0x4UL

Bit mask for MSC_CHOF

Definition at line 314 of file efm32jg1b_msc.h .

#define _MSC_IFS_CHOF_SHIFT   2

Shift value for MSC_CHOF

Definition at line 313 of file efm32jg1b_msc.h .

#define _MSC_IFS_CMOF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IFS

Definition at line 320 of file efm32jg1b_msc.h .

#define _MSC_IFS_CMOF_MASK   0x8UL

Bit mask for MSC_CMOF

Definition at line 319 of file efm32jg1b_msc.h .

#define _MSC_IFS_CMOF_SHIFT   3

Shift value for MSC_CMOF

Definition at line 318 of file efm32jg1b_msc.h .

#define _MSC_IFS_ERASE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IFS

Definition at line 305 of file efm32jg1b_msc.h .

#define _MSC_IFS_ERASE_MASK   0x1UL

Bit mask for MSC_ERASE

Definition at line 304 of file efm32jg1b_msc.h .

#define _MSC_IFS_ERASE_SHIFT   0

Shift value for MSC_ERASE

Definition at line 303 of file efm32jg1b_msc.h .

#define _MSC_IFS_ICACHERR_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IFS

Definition at line 330 of file efm32jg1b_msc.h .

#define _MSC_IFS_ICACHERR_MASK   0x20UL

Bit mask for MSC_ICACHERR

Definition at line 329 of file efm32jg1b_msc.h .

#define _MSC_IFS_ICACHERR_SHIFT   5

Shift value for MSC_ICACHERR

Definition at line 328 of file efm32jg1b_msc.h .

#define _MSC_IFS_MASK   0x0000003FUL

Mask for MSC_IFS

Definition at line 301 of file efm32jg1b_msc.h .

#define _MSC_IFS_PWRUPF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IFS

Definition at line 325 of file efm32jg1b_msc.h .

#define _MSC_IFS_PWRUPF_MASK   0x10UL

Bit mask for MSC_PWRUPF

Definition at line 324 of file efm32jg1b_msc.h .

#define _MSC_IFS_PWRUPF_SHIFT   4

Shift value for MSC_PWRUPF

Definition at line 323 of file efm32jg1b_msc.h .

#define _MSC_IFS_RESETVALUE   0x00000000UL

Default value for MSC_IFS

Definition at line 300 of file efm32jg1b_msc.h .

#define _MSC_IFS_WRITE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IFS

Definition at line 310 of file efm32jg1b_msc.h .

#define _MSC_IFS_WRITE_MASK   0x2UL

Bit mask for MSC_WRITE

Definition at line 309 of file efm32jg1b_msc.h .

#define _MSC_IFS_WRITE_SHIFT   1

Shift value for MSC_WRITE

Definition at line 308 of file efm32jg1b_msc.h .

#define _MSC_LOCK_LOCKKEY_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_LOCK

Definition at line 406 of file efm32jg1b_msc.h .

#define _MSC_LOCK_LOCKKEY_LOCK   0x00000000UL

Mode LOCK for MSC_LOCK

Definition at line 407 of file efm32jg1b_msc.h .

#define _MSC_LOCK_LOCKKEY_LOCKED   0x00000001UL

Mode LOCKED for MSC_LOCK

Definition at line 409 of file efm32jg1b_msc.h .

#define _MSC_LOCK_LOCKKEY_MASK   0xFFFFUL

Bit mask for MSC_LOCKKEY

Definition at line 405 of file efm32jg1b_msc.h .

#define _MSC_LOCK_LOCKKEY_SHIFT   0

Shift value for MSC_LOCKKEY

Definition at line 404 of file efm32jg1b_msc.h .

#define _MSC_LOCK_LOCKKEY_UNLOCK   0x00001B71UL

Mode UNLOCK for MSC_LOCK

Definition at line 410 of file efm32jg1b_msc.h .

#define _MSC_LOCK_LOCKKEY_UNLOCKED   0x00000000UL

Mode UNLOCKED for MSC_LOCK

Definition at line 408 of file efm32jg1b_msc.h .

#define _MSC_LOCK_MASK   0x0000FFFFUL

Mask for MSC_LOCK

Definition at line 403 of file efm32jg1b_msc.h .

#define _MSC_LOCK_RESETVALUE   0x00000000UL

Default value for MSC_LOCK

Definition at line 402 of file efm32jg1b_msc.h .

#define _MSC_MASSLOCK_LOCKKEY_DEFAULT   0x00000001UL

Mode DEFAULT for MSC_MASSLOCK

Definition at line 459 of file efm32jg1b_msc.h .

#define _MSC_MASSLOCK_LOCKKEY_LOCK   0x00000000UL

Mode LOCK for MSC_MASSLOCK

Definition at line 457 of file efm32jg1b_msc.h .

#define _MSC_MASSLOCK_LOCKKEY_LOCKED   0x00000001UL

Mode LOCKED for MSC_MASSLOCK

Definition at line 460 of file efm32jg1b_msc.h .

#define _MSC_MASSLOCK_LOCKKEY_MASK   0xFFFFUL

Bit mask for MSC_LOCKKEY

Definition at line 456 of file efm32jg1b_msc.h .

#define _MSC_MASSLOCK_LOCKKEY_SHIFT   0

Shift value for MSC_LOCKKEY

Definition at line 455 of file efm32jg1b_msc.h .

#define _MSC_MASSLOCK_LOCKKEY_UNLOCK   0x0000631AUL

Mode UNLOCK for MSC_MASSLOCK

Definition at line 461 of file efm32jg1b_msc.h .

#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED   0x00000000UL

Mode UNLOCKED for MSC_MASSLOCK

Definition at line 458 of file efm32jg1b_msc.h .

#define _MSC_MASSLOCK_MASK   0x0000FFFFUL

Mask for MSC_MASSLOCK

Definition at line 454 of file efm32jg1b_msc.h .

#define _MSC_MASSLOCK_RESETVALUE   0x00000001UL

Default value for MSC_MASSLOCK

Definition at line 453 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_AIDIS_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_READCTRL

Definition at line 121 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_AIDIS_MASK   0x10UL

Bit mask for MSC_AIDIS

Definition at line 120 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_AIDIS_SHIFT   4

Shift value for MSC_AIDIS

Definition at line 119 of file efm32jg1b_msc.h .

Referenced by MSC_EnableAutoCacheFlush() .

#define _MSC_READCTRL_ICCDIS_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_READCTRL

Definition at line 126 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_ICCDIS_MASK   0x20UL

Bit mask for MSC_ICCDIS

Definition at line 125 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_ICCDIS_SHIFT   5

Shift value for MSC_ICCDIS

Definition at line 124 of file efm32jg1b_msc.h .

Referenced by MSC_EnableCacheIRQs() .

#define _MSC_READCTRL_IFCDIS_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_READCTRL

Definition at line 116 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_IFCDIS_MASK   0x8UL

Bit mask for MSC_IFCDIS

Definition at line 115 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_IFCDIS_SHIFT   3

Shift value for MSC_IFCDIS

Definition at line 114 of file efm32jg1b_msc.h .

Referenced by MSC_EnableCache() .

#define _MSC_READCTRL_MASK   0x13000338UL

Mask for MSC_READCTRL

Definition at line 112 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_MODE_DEFAULT   0x00000001UL

Mode DEFAULT for MSC_READCTRL

Definition at line 141 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_MODE_MASK   0x3000000UL

Bit mask for MSC_MODE

Definition at line 139 of file efm32jg1b_msc.h .

Referenced by MSC_ExecConfigSet() .

#define _MSC_READCTRL_MODE_SHIFT   24

Shift value for MSC_MODE

Definition at line 138 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_MODE_WS0   0x00000000UL

Mode WS0 for MSC_READCTRL

Definition at line 140 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_MODE_WS1   0x00000001UL

Mode WS1 for MSC_READCTRL

Definition at line 142 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_PREFETCH_DEFAULT   0x00000001UL

Mode DEFAULT for MSC_READCTRL

Definition at line 131 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_PREFETCH_MASK   0x100UL

Bit mask for MSC_PREFETCH

Definition at line 130 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_PREFETCH_SHIFT   8

Shift value for MSC_PREFETCH

Definition at line 129 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_RESETVALUE   0x01000100UL

Default value for MSC_READCTRL

Definition at line 111 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_SCBTP_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_READCTRL

Definition at line 149 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_SCBTP_MASK   0x10000000UL

Bit mask for MSC_SCBTP

Definition at line 148 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_SCBTP_SHIFT   28

Shift value for MSC_SCBTP

Definition at line 147 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_USEHPROT_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_READCTRL

Definition at line 136 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_USEHPROT_MASK   0x200UL

Bit mask for MSC_USEHPROT

Definition at line 135 of file efm32jg1b_msc.h .

#define _MSC_READCTRL_USEHPROT_SHIFT   9

Shift value for MSC_USEHPROT

Definition at line 134 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_ASTWAIT_DEFAULT   0x00000001UL

Mode DEFAULT for MSC_STARTUP

Definition at line 482 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_ASTWAIT_MASK   0x1000000UL

Bit mask for MSC_ASTWAIT

Definition at line 481 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_ASTWAIT_SHIFT   24

Shift value for MSC_ASTWAIT

Definition at line 480 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_MASK   0x773FF3FFUL

Mask for MSC_STARTUP

Definition at line 470 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_RESETVALUE   0x1300104DUL

Default value for MSC_STARTUP

Definition at line 469 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STDLY0_DEFAULT   0x0000004DUL

Mode DEFAULT for MSC_STARTUP

Definition at line 473 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STDLY0_MASK   0x3FFUL

Bit mask for MSC_STDLY0

Definition at line 472 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STDLY0_SHIFT   0

Shift value for MSC_STDLY0

Definition at line 471 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STDLY1_DEFAULT   0x00000001UL

Mode DEFAULT for MSC_STARTUP

Definition at line 477 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STDLY1_MASK   0x3FF000UL

Bit mask for MSC_STDLY1

Definition at line 476 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STDLY1_SHIFT   12

Shift value for MSC_STDLY1

Definition at line 475 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STWS_DEFAULT   0x00000001UL

Mode DEFAULT for MSC_STARTUP

Definition at line 496 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STWS_MASK   0x70000000UL

Bit mask for MSC_STWS

Definition at line 495 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STWS_SHIFT   28

Shift value for MSC_STWS

Definition at line 494 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STWSAEN_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_STARTUP

Definition at line 492 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STWSAEN_MASK   0x4000000UL

Bit mask for MSC_STWSAEN

Definition at line 491 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STWSAEN_SHIFT   26

Shift value for MSC_STWSAEN

Definition at line 490 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STWSEN_DEFAULT   0x00000001UL

Mode DEFAULT for MSC_STARTUP

Definition at line 487 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STWSEN_MASK   0x2000000UL

Bit mask for MSC_STWSEN

Definition at line 486 of file efm32jg1b_msc.h .

#define _MSC_STARTUP_STWSEN_SHIFT   25

Shift value for MSC_STWSEN

Definition at line 485 of file efm32jg1b_msc.h .

#define _MSC_STATUS_BUSY_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_STATUS

Definition at line 232 of file efm32jg1b_msc.h .

#define _MSC_STATUS_BUSY_MASK   0x1UL

Bit mask for MSC_BUSY

Definition at line 231 of file efm32jg1b_msc.h .

#define _MSC_STATUS_BUSY_SHIFT   0

Shift value for MSC_BUSY

Definition at line 230 of file efm32jg1b_msc.h .

#define _MSC_STATUS_ERASEABORTED_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_STATUS

Definition at line 257 of file efm32jg1b_msc.h .

#define _MSC_STATUS_ERASEABORTED_MASK   0x20UL

Bit mask for MSC_ERASEABORTED

Definition at line 256 of file efm32jg1b_msc.h .

#define _MSC_STATUS_ERASEABORTED_SHIFT   5

Shift value for MSC_ERASEABORTED

Definition at line 255 of file efm32jg1b_msc.h .

#define _MSC_STATUS_INVADDR_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_STATUS

Definition at line 242 of file efm32jg1b_msc.h .

#define _MSC_STATUS_INVADDR_MASK   0x4UL

Bit mask for MSC_INVADDR

Definition at line 241 of file efm32jg1b_msc.h .

#define _MSC_STATUS_INVADDR_SHIFT   2

Shift value for MSC_INVADDR

Definition at line 240 of file efm32jg1b_msc.h .

#define _MSC_STATUS_LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_STATUS

Definition at line 237 of file efm32jg1b_msc.h .

#define _MSC_STATUS_LOCKED_MASK   0x2UL

Bit mask for MSC_LOCKED

Definition at line 236 of file efm32jg1b_msc.h .

#define _MSC_STATUS_LOCKED_SHIFT   1

Shift value for MSC_LOCKED

Definition at line 235 of file efm32jg1b_msc.h .

#define _MSC_STATUS_MASK   0x0000007FUL

Mask for MSC_STATUS

Definition at line 228 of file efm32jg1b_msc.h .

#define _MSC_STATUS_PCRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_STATUS

Definition at line 262 of file efm32jg1b_msc.h .

#define _MSC_STATUS_PCRUNNING_MASK   0x40UL

Bit mask for MSC_PCRUNNING

Definition at line 261 of file efm32jg1b_msc.h .

#define _MSC_STATUS_PCRUNNING_SHIFT   6

Shift value for MSC_PCRUNNING

Definition at line 260 of file efm32jg1b_msc.h .

#define _MSC_STATUS_RESETVALUE   0x00000008UL

Default value for MSC_STATUS

Definition at line 227 of file efm32jg1b_msc.h .

#define _MSC_STATUS_WDATAREADY_DEFAULT   0x00000001UL

Mode DEFAULT for MSC_STATUS

Definition at line 247 of file efm32jg1b_msc.h .

#define _MSC_STATUS_WDATAREADY_MASK   0x8UL

Bit mask for MSC_WDATAREADY

Definition at line 246 of file efm32jg1b_msc.h .

#define _MSC_STATUS_WDATAREADY_SHIFT   3

Shift value for MSC_WDATAREADY

Definition at line 245 of file efm32jg1b_msc.h .

#define _MSC_STATUS_WORDTIMEOUT_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_STATUS

Definition at line 252 of file efm32jg1b_msc.h .

#define _MSC_STATUS_WORDTIMEOUT_MASK   0x10UL

Bit mask for MSC_WORDTIMEOUT

Definition at line 251 of file efm32jg1b_msc.h .

#define _MSC_STATUS_WORDTIMEOUT_SHIFT   4

Shift value for MSC_WORDTIMEOUT

Definition at line 250 of file efm32jg1b_msc.h .

#define _MSC_WDATA_MASK   0xFFFFFFFFUL

Mask for MSC_WDATA

Definition at line 220 of file efm32jg1b_msc.h .

#define _MSC_WDATA_RESETVALUE   0x00000000UL

Default value for MSC_WDATA

Definition at line 219 of file efm32jg1b_msc.h .

#define _MSC_WDATA_WDATA_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_WDATA

Definition at line 223 of file efm32jg1b_msc.h .

#define _MSC_WDATA_WDATA_MASK   0xFFFFFFFFUL

Bit mask for MSC_WDATA

Definition at line 222 of file efm32jg1b_msc.h .

#define _MSC_WDATA_WDATA_SHIFT   0

Shift value for MSC_WDATA

Definition at line 221 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_CLEARWDATA_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_WRITECMD

Definition at line 207 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_CLEARWDATA_MASK   0x1000UL

Bit mask for MSC_CLEARWDATA

Definition at line 206 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_CLEARWDATA_SHIFT   12

Shift value for MSC_CLEARWDATA

Definition at line 205 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_ERASEABORT_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_WRITECMD

Definition at line 197 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_ERASEABORT_MASK   0x20UL

Bit mask for MSC_ERASEABORT

Definition at line 196 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_ERASEABORT_SHIFT   5

Shift value for MSC_ERASEABORT

Definition at line 195 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_WRITECMD

Definition at line 202 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_ERASEMAIN0_MASK   0x100UL

Bit mask for MSC_ERASEMAIN0

Definition at line 201 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_ERASEMAIN0_SHIFT   8

Shift value for MSC_ERASEMAIN0

Definition at line 200 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_ERASEPAGE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_WRITECMD

Definition at line 177 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_ERASEPAGE_MASK   0x2UL

Bit mask for MSC_ERASEPAGE

Definition at line 176 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_ERASEPAGE_SHIFT   1

Shift value for MSC_ERASEPAGE

Definition at line 175 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_LADDRIM_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_WRITECMD

Definition at line 172 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_LADDRIM_MASK   0x1UL

Bit mask for MSC_LADDRIM

Definition at line 171 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_LADDRIM_SHIFT   0

Shift value for MSC_LADDRIM

Definition at line 170 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_MASK   0x0000113FUL

Mask for MSC_WRITECMD

Definition at line 168 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_RESETVALUE   0x00000000UL

Default value for MSC_WRITECMD

Definition at line 167 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_WRITEEND_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_WRITECMD

Definition at line 182 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_WRITEEND_MASK   0x4UL

Bit mask for MSC_WRITEEND

Definition at line 181 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_WRITEEND_SHIFT   2

Shift value for MSC_WRITEEND

Definition at line 180 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_WRITEONCE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_WRITECMD

Definition at line 187 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_WRITEONCE_MASK   0x8UL

Bit mask for MSC_WRITEONCE

Definition at line 186 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_WRITEONCE_SHIFT   3

Shift value for MSC_WRITEONCE

Definition at line 185 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_WRITETRIG_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_WRITECMD

Definition at line 192 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_WRITETRIG_MASK   0x10UL

Bit mask for MSC_WRITETRIG

Definition at line 191 of file efm32jg1b_msc.h .

#define _MSC_WRITECMD_WRITETRIG_SHIFT   4

Shift value for MSC_WRITETRIG

Definition at line 190 of file efm32jg1b_msc.h .

#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_WRITECTRL

Definition at line 163 of file efm32jg1b_msc.h .

#define _MSC_WRITECTRL_IRQERASEABORT_MASK   0x2UL

Bit mask for MSC_IRQERASEABORT

Definition at line 162 of file efm32jg1b_msc.h .

#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT   1

Shift value for MSC_IRQERASEABORT

Definition at line 161 of file efm32jg1b_msc.h .

#define _MSC_WRITECTRL_MASK   0x00000003UL

Mask for MSC_WRITECTRL

Definition at line 154 of file efm32jg1b_msc.h .

#define _MSC_WRITECTRL_RESETVALUE   0x00000000UL

Default value for MSC_WRITECTRL

Definition at line 153 of file efm32jg1b_msc.h .

#define _MSC_WRITECTRL_WREN_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_WRITECTRL

Definition at line 158 of file efm32jg1b_msc.h .

#define _MSC_WRITECTRL_WREN_MASK   0x1UL

Bit mask for MSC_WREN

Definition at line 157 of file efm32jg1b_msc.h .

#define _MSC_WRITECTRL_WREN_SHIFT   0

Shift value for MSC_WREN

Definition at line 156 of file efm32jg1b_msc.h .

#define MSC_ADDRB_ADDRB_DEFAULT   ( _MSC_ADDRB_ADDRB_DEFAULT << 0)

Shifted mode DEFAULT for MSC_ADDRB

Definition at line 216 of file efm32jg1b_msc.h .

#define MSC_CACHECMD_INVCACHE   (0x1UL << 0)

Invalidate Instruction Cache

Definition at line 420 of file efm32jg1b_msc.h .

Referenced by CHIP_Init() , and MSC_FlushCache() .

#define MSC_CACHECMD_INVCACHE_DEFAULT   ( _MSC_CACHECMD_INVCACHE_DEFAULT << 0)

Shifted mode DEFAULT for MSC_CACHECMD

Definition at line 424 of file efm32jg1b_msc.h .

#define MSC_CACHECMD_STARTPC   (0x1UL << 1)

Start Performance Counters

Definition at line 425 of file efm32jg1b_msc.h .

Referenced by MSC_StartCacheMeasurement() .

#define MSC_CACHECMD_STARTPC_DEFAULT   ( _MSC_CACHECMD_STARTPC_DEFAULT << 1)

Shifted mode DEFAULT for MSC_CACHECMD

Definition at line 429 of file efm32jg1b_msc.h .

#define MSC_CACHECMD_STOPPC   (0x1UL << 2)

Stop Performance Counters

Definition at line 430 of file efm32jg1b_msc.h .

Referenced by MSC_GetCacheMeasurement() .

#define MSC_CACHECMD_STOPPC_DEFAULT   ( _MSC_CACHECMD_STOPPC_DEFAULT << 2)

Shifted mode DEFAULT for MSC_CACHECMD

Definition at line 434 of file efm32jg1b_msc.h .

#define MSC_CACHEHITS_CACHEHITS_DEFAULT   ( _MSC_CACHEHITS_CACHEHITS_DEFAULT << 0)

Shifted mode DEFAULT for MSC_CACHEHITS

Definition at line 442 of file efm32jg1b_msc.h .

#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT   ( _MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0)

Shifted mode DEFAULT for MSC_CACHEMISSES

Definition at line 450 of file efm32jg1b_msc.h .

#define MSC_CMD_PWRUP   (0x1UL << 0)

Flash Power Up Command

Definition at line 502 of file efm32jg1b_msc.h .

#define MSC_CMD_PWRUP_DEFAULT   ( _MSC_CMD_PWRUP_DEFAULT << 0)

Shifted mode DEFAULT for MSC_CMD

Definition at line 506 of file efm32jg1b_msc.h .

#define MSC_CTRL_ADDRFAULTEN   (0x1UL << 0)

Invalid Address Bus Fault Response Enable

Definition at line 89 of file efm32jg1b_msc.h .

#define MSC_CTRL_ADDRFAULTEN_DEFAULT   ( _MSC_CTRL_ADDRFAULTEN_DEFAULT << 0)

Shifted mode DEFAULT for MSC_CTRL

Definition at line 93 of file efm32jg1b_msc.h .

#define MSC_CTRL_CLKDISFAULTEN   (0x1UL << 1)

Clock-disabled Bus Fault Response Enable

Definition at line 94 of file efm32jg1b_msc.h .

#define MSC_CTRL_CLKDISFAULTEN_DEFAULT   ( _MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1)

Shifted mode DEFAULT for MSC_CTRL

Definition at line 98 of file efm32jg1b_msc.h .

#define MSC_CTRL_IFCREADCLEAR   (0x1UL << 3)

IFC Read Clears IF

Definition at line 104 of file efm32jg1b_msc.h .

#define MSC_CTRL_IFCREADCLEAR_DEFAULT   ( _MSC_CTRL_IFCREADCLEAR_DEFAULT << 3)

Shifted mode DEFAULT for MSC_CTRL

Definition at line 108 of file efm32jg1b_msc.h .

#define MSC_CTRL_PWRUPONDEMAND   (0x1UL << 2)

Power Up on Demand During Wake Up

Definition at line 99 of file efm32jg1b_msc.h .

#define MSC_CTRL_PWRUPONDEMAND_DEFAULT   ( _MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2)

Shifted mode DEFAULT for MSC_CTRL

Definition at line 103 of file efm32jg1b_msc.h .

#define MSC_IEN_CHOF   (0x1UL << 2)

CHOF Interrupt Enable

Definition at line 380 of file efm32jg1b_msc.h .

#define MSC_IEN_CHOF_DEFAULT   ( _MSC_IEN_CHOF_DEFAULT << 2)

Shifted mode DEFAULT for MSC_IEN

Definition at line 384 of file efm32jg1b_msc.h .

#define MSC_IEN_CMOF   (0x1UL << 3)

CMOF Interrupt Enable

Definition at line 385 of file efm32jg1b_msc.h .

#define MSC_IEN_CMOF_DEFAULT   ( _MSC_IEN_CMOF_DEFAULT << 3)

Shifted mode DEFAULT for MSC_IEN

Definition at line 389 of file efm32jg1b_msc.h .

#define MSC_IEN_ERASE   (0x1UL << 0)

ERASE Interrupt Enable

Definition at line 370 of file efm32jg1b_msc.h .

#define MSC_IEN_ERASE_DEFAULT   ( _MSC_IEN_ERASE_DEFAULT << 0)

Shifted mode DEFAULT for MSC_IEN

Definition at line 374 of file efm32jg1b_msc.h .

#define MSC_IEN_ICACHERR   (0x1UL << 5)

ICACHERR Interrupt Enable

Definition at line 395 of file efm32jg1b_msc.h .

#define MSC_IEN_ICACHERR_DEFAULT   ( _MSC_IEN_ICACHERR_DEFAULT << 5)

Shifted mode DEFAULT for MSC_IEN

Definition at line 399 of file efm32jg1b_msc.h .

#define MSC_IEN_PWRUPF   (0x1UL << 4)

PWRUPF Interrupt Enable

Definition at line 390 of file efm32jg1b_msc.h .

#define MSC_IEN_PWRUPF_DEFAULT   ( _MSC_IEN_PWRUPF_DEFAULT << 4)

Shifted mode DEFAULT for MSC_IEN

Definition at line 394 of file efm32jg1b_msc.h .

#define MSC_IEN_WRITE   (0x1UL << 1)

WRITE Interrupt Enable

Definition at line 375 of file efm32jg1b_msc.h .

#define MSC_IEN_WRITE_DEFAULT   ( _MSC_IEN_WRITE_DEFAULT << 1)

Shifted mode DEFAULT for MSC_IEN

Definition at line 379 of file efm32jg1b_msc.h .

#define MSC_IF_CHOF   (0x1UL << 2)

Cache Hits Overflow Interrupt Flag

Definition at line 278 of file efm32jg1b_msc.h .

Referenced by MSC_GetCacheMeasurement() , and MSC_StartCacheMeasurement() .

#define MSC_IF_CHOF_DEFAULT   ( _MSC_IF_CHOF_DEFAULT << 2)

Shifted mode DEFAULT for MSC_IF

Definition at line 282 of file efm32jg1b_msc.h .

#define MSC_IF_CMOF   (0x1UL << 3)

Cache Misses Overflow Interrupt Flag

Definition at line 283 of file efm32jg1b_msc.h .

Referenced by MSC_GetCacheMeasurement() , and MSC_StartCacheMeasurement() .

#define MSC_IF_CMOF_DEFAULT   ( _MSC_IF_CMOF_DEFAULT << 3)

Shifted mode DEFAULT for MSC_IF

Definition at line 287 of file efm32jg1b_msc.h .

#define MSC_IF_ERASE   (0x1UL << 0)

Erase Done Interrupt Read Flag

Definition at line 268 of file efm32jg1b_msc.h .

#define MSC_IF_ERASE_DEFAULT   ( _MSC_IF_ERASE_DEFAULT << 0)

Shifted mode DEFAULT for MSC_IF

Definition at line 272 of file efm32jg1b_msc.h .

#define MSC_IF_ICACHERR   (0x1UL << 5)

ICache RAM Parity Error Flag

Definition at line 293 of file efm32jg1b_msc.h .

#define MSC_IF_ICACHERR_DEFAULT   ( _MSC_IF_ICACHERR_DEFAULT << 5)

Shifted mode DEFAULT for MSC_IF

Definition at line 297 of file efm32jg1b_msc.h .

#define MSC_IF_PWRUPF   (0x1UL << 4)

Flash Power Up Sequence Complete Flag

Definition at line 288 of file efm32jg1b_msc.h .

#define MSC_IF_PWRUPF_DEFAULT   ( _MSC_IF_PWRUPF_DEFAULT << 4)

Shifted mode DEFAULT for MSC_IF

Definition at line 292 of file efm32jg1b_msc.h .

#define MSC_IF_WRITE   (0x1UL << 1)

Write Done Interrupt Read Flag

Definition at line 273 of file efm32jg1b_msc.h .

#define MSC_IF_WRITE_DEFAULT   ( _MSC_IF_WRITE_DEFAULT << 1)

Shifted mode DEFAULT for MSC_IF

Definition at line 277 of file efm32jg1b_msc.h .

#define MSC_IFC_CHOF   (0x1UL << 2)

Clear CHOF Interrupt Flag

Definition at line 346 of file efm32jg1b_msc.h .

#define MSC_IFC_CHOF_DEFAULT   ( _MSC_IFC_CHOF_DEFAULT << 2)

Shifted mode DEFAULT for MSC_IFC

Definition at line 350 of file efm32jg1b_msc.h .

#define MSC_IFC_CMOF   (0x1UL << 3)

Clear CMOF Interrupt Flag

Definition at line 351 of file efm32jg1b_msc.h .

#define MSC_IFC_CMOF_DEFAULT   ( _MSC_IFC_CMOF_DEFAULT << 3)

Shifted mode DEFAULT for MSC_IFC

Definition at line 355 of file efm32jg1b_msc.h .

#define MSC_IFC_ERASE   (0x1UL << 0)

Clear ERASE Interrupt Flag

Definition at line 336 of file efm32jg1b_msc.h .

#define MSC_IFC_ERASE_DEFAULT   ( _MSC_IFC_ERASE_DEFAULT << 0)

Shifted mode DEFAULT for MSC_IFC

Definition at line 340 of file efm32jg1b_msc.h .

#define MSC_IFC_ICACHERR   (0x1UL << 5)

Clear ICACHERR Interrupt Flag

Definition at line 361 of file efm32jg1b_msc.h .

#define MSC_IFC_ICACHERR_DEFAULT   ( _MSC_IFC_ICACHERR_DEFAULT << 5)

Shifted mode DEFAULT for MSC_IFC

Definition at line 365 of file efm32jg1b_msc.h .

#define MSC_IFC_PWRUPF   (0x1UL << 4)

Clear PWRUPF Interrupt Flag

Definition at line 356 of file efm32jg1b_msc.h .

#define MSC_IFC_PWRUPF_DEFAULT   ( _MSC_IFC_PWRUPF_DEFAULT << 4)

Shifted mode DEFAULT for MSC_IFC

Definition at line 360 of file efm32jg1b_msc.h .

#define MSC_IFC_WRITE   (0x1UL << 1)

Clear WRITE Interrupt Flag

Definition at line 341 of file efm32jg1b_msc.h .

#define MSC_IFC_WRITE_DEFAULT   ( _MSC_IFC_WRITE_DEFAULT << 1)

Shifted mode DEFAULT for MSC_IFC

Definition at line 345 of file efm32jg1b_msc.h .

#define MSC_IFS_CHOF   (0x1UL << 2)

Set CHOF Interrupt Flag

Definition at line 312 of file efm32jg1b_msc.h .

#define MSC_IFS_CHOF_DEFAULT   ( _MSC_IFS_CHOF_DEFAULT << 2)

Shifted mode DEFAULT for MSC_IFS

Definition at line 316 of file efm32jg1b_msc.h .

#define MSC_IFS_CMOF   (0x1UL << 3)

Set CMOF Interrupt Flag

Definition at line 317 of file efm32jg1b_msc.h .

#define MSC_IFS_CMOF_DEFAULT   ( _MSC_IFS_CMOF_DEFAULT << 3)

Shifted mode DEFAULT for MSC_IFS

Definition at line 321 of file efm32jg1b_msc.h .

#define MSC_IFS_ERASE   (0x1UL << 0)

Set ERASE Interrupt Flag

Definition at line 302 of file efm32jg1b_msc.h .

#define MSC_IFS_ERASE_DEFAULT   ( _MSC_IFS_ERASE_DEFAULT << 0)

Shifted mode DEFAULT for MSC_IFS

Definition at line 306 of file efm32jg1b_msc.h .

#define MSC_IFS_ICACHERR   (0x1UL << 5)

Set ICACHERR Interrupt Flag

Definition at line 327 of file efm32jg1b_msc.h .

#define MSC_IFS_ICACHERR_DEFAULT   ( _MSC_IFS_ICACHERR_DEFAULT << 5)

Shifted mode DEFAULT for MSC_IFS

Definition at line 331 of file efm32jg1b_msc.h .

#define MSC_IFS_PWRUPF   (0x1UL << 4)

Set PWRUPF Interrupt Flag

Definition at line 322 of file efm32jg1b_msc.h .

#define MSC_IFS_PWRUPF_DEFAULT   ( _MSC_IFS_PWRUPF_DEFAULT << 4)

Shifted mode DEFAULT for MSC_IFS

Definition at line 326 of file efm32jg1b_msc.h .

#define MSC_IFS_WRITE   (0x1UL << 1)

Set WRITE Interrupt Flag

Definition at line 307 of file efm32jg1b_msc.h .

#define MSC_IFS_WRITE_DEFAULT   ( _MSC_IFS_WRITE_DEFAULT << 1)

Shifted mode DEFAULT for MSC_IFS

Definition at line 311 of file efm32jg1b_msc.h .

#define MSC_LOCK_LOCKKEY_DEFAULT   ( _MSC_LOCK_LOCKKEY_DEFAULT << 0)

Shifted mode DEFAULT for MSC_LOCK

Definition at line 411 of file efm32jg1b_msc.h .

#define MSC_LOCK_LOCKKEY_LOCK   ( _MSC_LOCK_LOCKKEY_LOCK << 0)

Shifted mode LOCK for MSC_LOCK

Definition at line 412 of file efm32jg1b_msc.h .

#define MSC_LOCK_LOCKKEY_LOCKED   ( _MSC_LOCK_LOCKKEY_LOCKED << 0)

Shifted mode LOCKED for MSC_LOCK

Definition at line 414 of file efm32jg1b_msc.h .

#define MSC_LOCK_LOCKKEY_UNLOCK   ( _MSC_LOCK_LOCKKEY_UNLOCK << 0)

Shifted mode UNLOCK for MSC_LOCK

Definition at line 415 of file efm32jg1b_msc.h .

#define MSC_LOCK_LOCKKEY_UNLOCKED   ( _MSC_LOCK_LOCKKEY_UNLOCKED << 0)

Shifted mode UNLOCKED for MSC_LOCK

Definition at line 413 of file efm32jg1b_msc.h .

#define MSC_MASSLOCK_LOCKKEY_DEFAULT   ( _MSC_MASSLOCK_LOCKKEY_DEFAULT << 0)

Shifted mode DEFAULT for MSC_MASSLOCK

Definition at line 464 of file efm32jg1b_msc.h .

#define MSC_MASSLOCK_LOCKKEY_LOCK   ( _MSC_MASSLOCK_LOCKKEY_LOCK << 0)

Shifted mode LOCK for MSC_MASSLOCK

Definition at line 462 of file efm32jg1b_msc.h .

Referenced by MSC_MassErase() .

#define MSC_MASSLOCK_LOCKKEY_LOCKED   ( _MSC_MASSLOCK_LOCKKEY_LOCKED << 0)

Shifted mode LOCKED for MSC_MASSLOCK

Definition at line 465 of file efm32jg1b_msc.h .

#define MSC_MASSLOCK_LOCKKEY_UNLOCK   ( _MSC_MASSLOCK_LOCKKEY_UNLOCK << 0)

Shifted mode UNLOCK for MSC_MASSLOCK

Definition at line 466 of file efm32jg1b_msc.h .

Referenced by MSC_MassErase() .

#define MSC_MASSLOCK_LOCKKEY_UNLOCKED   ( _MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0)

Shifted mode UNLOCKED for MSC_MASSLOCK

Definition at line 463 of file efm32jg1b_msc.h .

#define MSC_READCTRL_AIDIS   (0x1UL << 4)

Automatic Invalidate Disable

Definition at line 118 of file efm32jg1b_msc.h .

Referenced by MSC_ExecConfigSet() .

#define MSC_READCTRL_AIDIS_DEFAULT   ( _MSC_READCTRL_AIDIS_DEFAULT << 4)

Shifted mode DEFAULT for MSC_READCTRL

Definition at line 122 of file efm32jg1b_msc.h .

#define MSC_READCTRL_ICCDIS   (0x1UL << 5)

Interrupt Context Cache Disable

Definition at line 123 of file efm32jg1b_msc.h .

Referenced by MSC_ExecConfigSet() .

#define MSC_READCTRL_ICCDIS_DEFAULT   ( _MSC_READCTRL_ICCDIS_DEFAULT << 5)

Shifted mode DEFAULT for MSC_READCTRL

Definition at line 127 of file efm32jg1b_msc.h .

#define MSC_READCTRL_IFCDIS   (0x1UL << 3)

Internal Flash Cache Disable

Definition at line 113 of file efm32jg1b_msc.h .

Referenced by MSC_ExecConfigSet() .

#define MSC_READCTRL_IFCDIS_DEFAULT   ( _MSC_READCTRL_IFCDIS_DEFAULT << 3)

Shifted mode DEFAULT for MSC_READCTRL

Definition at line 117 of file efm32jg1b_msc.h .

#define MSC_READCTRL_MODE_DEFAULT   ( _MSC_READCTRL_MODE_DEFAULT << 24)

Shifted mode DEFAULT for MSC_READCTRL

Definition at line 144 of file efm32jg1b_msc.h .

#define MSC_READCTRL_MODE_WS0   ( _MSC_READCTRL_MODE_WS0 << 24)

Shifted mode WS0 for MSC_READCTRL

Definition at line 143 of file efm32jg1b_msc.h .

Referenced by MSC_ExecConfigSet() .

#define MSC_READCTRL_MODE_WS1   ( _MSC_READCTRL_MODE_WS1 << 24)

Shifted mode WS1 for MSC_READCTRL

Definition at line 145 of file efm32jg1b_msc.h .

Referenced by MSC_ExecConfigSet() .

#define MSC_READCTRL_PREFETCH   (0x1UL << 8)

Prefetch Mode

Definition at line 128 of file efm32jg1b_msc.h .

Referenced by MSC_ExecConfigSet() .

#define MSC_READCTRL_PREFETCH_DEFAULT   ( _MSC_READCTRL_PREFETCH_DEFAULT << 8)

Shifted mode DEFAULT for MSC_READCTRL

Definition at line 132 of file efm32jg1b_msc.h .

#define MSC_READCTRL_SCBTP   (0x1UL << 28)

Suppress Conditional Branch Target Perfetch

Definition at line 146 of file efm32jg1b_msc.h .

Referenced by MSC_ExecConfigSet() .

#define MSC_READCTRL_SCBTP_DEFAULT   ( _MSC_READCTRL_SCBTP_DEFAULT << 28)

Shifted mode DEFAULT for MSC_READCTRL

Definition at line 150 of file efm32jg1b_msc.h .

#define MSC_READCTRL_USEHPROT   (0x1UL << 9)

AHB_HPROT Mode

Definition at line 133 of file efm32jg1b_msc.h .

Referenced by MSC_ExecConfigSet() .

#define MSC_READCTRL_USEHPROT_DEFAULT   ( _MSC_READCTRL_USEHPROT_DEFAULT << 9)

Shifted mode DEFAULT for MSC_READCTRL

Definition at line 137 of file efm32jg1b_msc.h .

#define MSC_STARTUP_ASTWAIT   (0x1UL << 24)

Active Startup Wait

Definition at line 479 of file efm32jg1b_msc.h .

#define MSC_STARTUP_ASTWAIT_DEFAULT   ( _MSC_STARTUP_ASTWAIT_DEFAULT << 24)

Shifted mode DEFAULT for MSC_STARTUP

Definition at line 483 of file efm32jg1b_msc.h .

#define MSC_STARTUP_STDLY0_DEFAULT   ( _MSC_STARTUP_STDLY0_DEFAULT << 0)

Shifted mode DEFAULT for MSC_STARTUP

Definition at line 474 of file efm32jg1b_msc.h .

#define MSC_STARTUP_STDLY1_DEFAULT   ( _MSC_STARTUP_STDLY1_DEFAULT << 12)

Shifted mode DEFAULT for MSC_STARTUP

Definition at line 478 of file efm32jg1b_msc.h .

#define MSC_STARTUP_STWS_DEFAULT   ( _MSC_STARTUP_STWS_DEFAULT << 28)

Shifted mode DEFAULT for MSC_STARTUP

Definition at line 497 of file efm32jg1b_msc.h .

#define MSC_STARTUP_STWSAEN   (0x1UL << 26)

Startup Waitstates Always Enable

Definition at line 489 of file efm32jg1b_msc.h .

#define MSC_STARTUP_STWSAEN_DEFAULT   ( _MSC_STARTUP_STWSAEN_DEFAULT << 26)

Shifted mode DEFAULT for MSC_STARTUP

Definition at line 493 of file efm32jg1b_msc.h .

#define MSC_STARTUP_STWSEN   (0x1UL << 25)

Startup Waitstates Enable

Definition at line 484 of file efm32jg1b_msc.h .

#define MSC_STARTUP_STWSEN_DEFAULT   ( _MSC_STARTUP_STWSEN_DEFAULT << 25)

Shifted mode DEFAULT for MSC_STARTUP

Definition at line 488 of file efm32jg1b_msc.h .

#define MSC_STATUS_BUSY   (0x1UL << 0)

Erase/Write Busy

Definition at line 229 of file efm32jg1b_msc.h .

Referenced by MSC_ErasePage() , and MSC_MassErase() .

#define MSC_STATUS_BUSY_DEFAULT   ( _MSC_STATUS_BUSY_DEFAULT << 0)

Shifted mode DEFAULT for MSC_STATUS

Definition at line 233 of file efm32jg1b_msc.h .

#define MSC_STATUS_ERASEABORTED   (0x1UL << 5)

The Current Flash Erase Operation Aborted

Definition at line 254 of file efm32jg1b_msc.h .

#define MSC_STATUS_ERASEABORTED_DEFAULT   ( _MSC_STATUS_ERASEABORTED_DEFAULT << 5)

Shifted mode DEFAULT for MSC_STATUS

Definition at line 258 of file efm32jg1b_msc.h .

#define MSC_STATUS_INVADDR   (0x1UL << 2)

Invalid Write Address or Erase Page

Definition at line 239 of file efm32jg1b_msc.h .

Referenced by MSC_ErasePage() .

#define MSC_STATUS_INVADDR_DEFAULT   ( _MSC_STATUS_INVADDR_DEFAULT << 2)

Shifted mode DEFAULT for MSC_STATUS

Definition at line 243 of file efm32jg1b_msc.h .

#define MSC_STATUS_LOCKED   (0x1UL << 1)

Access Locked

Definition at line 234 of file efm32jg1b_msc.h .

Referenced by MSC_ErasePage() .

#define MSC_STATUS_LOCKED_DEFAULT   ( _MSC_STATUS_LOCKED_DEFAULT << 1)

Shifted mode DEFAULT for MSC_STATUS

Definition at line 238 of file efm32jg1b_msc.h .

#define MSC_STATUS_PCRUNNING   (0x1UL << 6)

Performance Counters Running

Definition at line 259 of file efm32jg1b_msc.h .

#define MSC_STATUS_PCRUNNING_DEFAULT   ( _MSC_STATUS_PCRUNNING_DEFAULT << 6)

Shifted mode DEFAULT for MSC_STATUS

Definition at line 263 of file efm32jg1b_msc.h .

#define MSC_STATUS_WDATAREADY   (0x1UL << 3)

WDATA Write Ready

Definition at line 244 of file efm32jg1b_msc.h .

#define MSC_STATUS_WDATAREADY_DEFAULT   ( _MSC_STATUS_WDATAREADY_DEFAULT << 3)

Shifted mode DEFAULT for MSC_STATUS

Definition at line 248 of file efm32jg1b_msc.h .

#define MSC_STATUS_WORDTIMEOUT   (0x1UL << 4)

Flash Write Word Timeout

Definition at line 249 of file efm32jg1b_msc.h .

#define MSC_STATUS_WORDTIMEOUT_DEFAULT   ( _MSC_STATUS_WORDTIMEOUT_DEFAULT << 4)

Shifted mode DEFAULT for MSC_STATUS

Definition at line 253 of file efm32jg1b_msc.h .

#define MSC_WDATA_WDATA_DEFAULT   ( _MSC_WDATA_WDATA_DEFAULT << 0)

Shifted mode DEFAULT for MSC_WDATA

Definition at line 224 of file efm32jg1b_msc.h .

#define MSC_WRITECMD_CLEARWDATA   (0x1UL << 12)

Clear WDATA State

Definition at line 204 of file efm32jg1b_msc.h .

#define MSC_WRITECMD_CLEARWDATA_DEFAULT   ( _MSC_WRITECMD_CLEARWDATA_DEFAULT << 12)

Shifted mode DEFAULT for MSC_WRITECMD

Definition at line 208 of file efm32jg1b_msc.h .

#define MSC_WRITECMD_ERASEABORT   (0x1UL << 5)

Abort Erase Sequence

Definition at line 194 of file efm32jg1b_msc.h .

#define MSC_WRITECMD_ERASEABORT_DEFAULT   ( _MSC_WRITECMD_ERASEABORT_DEFAULT << 5)

Shifted mode DEFAULT for MSC_WRITECMD

Definition at line 198 of file efm32jg1b_msc.h .

#define MSC_WRITECMD_ERASEMAIN0   (0x1UL << 8)

Mass Erase Region 0

Definition at line 199 of file efm32jg1b_msc.h .

Referenced by MSC_MassErase() .

#define MSC_WRITECMD_ERASEMAIN0_DEFAULT   ( _MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8)

Shifted mode DEFAULT for MSC_WRITECMD

Definition at line 203 of file efm32jg1b_msc.h .

#define MSC_WRITECMD_ERASEPAGE   (0x1UL << 1)

Erase Page

Definition at line 174 of file efm32jg1b_msc.h .

Referenced by MSC_ErasePage() .

#define MSC_WRITECMD_ERASEPAGE_DEFAULT   ( _MSC_WRITECMD_ERASEPAGE_DEFAULT << 1)

Shifted mode DEFAULT for MSC_WRITECMD

Definition at line 178 of file efm32jg1b_msc.h .

#define MSC_WRITECMD_LADDRIM   (0x1UL << 0)

Load MSC_ADDRB Into ADDR

Definition at line 169 of file efm32jg1b_msc.h .

Referenced by MSC_ErasePage() .

#define MSC_WRITECMD_LADDRIM_DEFAULT   ( _MSC_WRITECMD_LADDRIM_DEFAULT << 0)

Shifted mode DEFAULT for MSC_WRITECMD

Definition at line 173 of file efm32jg1b_msc.h .

#define MSC_WRITECMD_WRITEEND   (0x1UL << 2)

End Write Mode

Definition at line 179 of file efm32jg1b_msc.h .

#define MSC_WRITECMD_WRITEEND_DEFAULT   ( _MSC_WRITECMD_WRITEEND_DEFAULT << 2)

Shifted mode DEFAULT for MSC_WRITECMD

Definition at line 183 of file efm32jg1b_msc.h .

#define MSC_WRITECMD_WRITEONCE   (0x1UL << 3)

Word Write-Once Trigger

Definition at line 184 of file efm32jg1b_msc.h .

#define MSC_WRITECMD_WRITEONCE_DEFAULT   ( _MSC_WRITECMD_WRITEONCE_DEFAULT << 3)

Shifted mode DEFAULT for MSC_WRITECMD

Definition at line 188 of file efm32jg1b_msc.h .

#define MSC_WRITECMD_WRITETRIG   (0x1UL << 4)

Word Write Sequence Trigger

Definition at line 189 of file efm32jg1b_msc.h .

#define MSC_WRITECMD_WRITETRIG_DEFAULT   ( _MSC_WRITECMD_WRITETRIG_DEFAULT << 4)

Shifted mode DEFAULT for MSC_WRITECMD

Definition at line 193 of file efm32jg1b_msc.h .

#define MSC_WRITECTRL_IRQERASEABORT   (0x1UL << 1)

Abort Page Erase on Interrupt

Definition at line 160 of file efm32jg1b_msc.h .

#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT   ( _MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1)

Shifted mode DEFAULT for MSC_WRITECTRL

Definition at line 164 of file efm32jg1b_msc.h .

#define MSC_WRITECTRL_WREN   (0x1UL << 0)

Enable Write/Erase Controller

Definition at line 155 of file efm32jg1b_msc.h .

Referenced by MSC_Deinit() , MSC_ErasePage() , MSC_Init() , and MSC_MassErase() .

#define MSC_WRITECTRL_WREN_DEFAULT   ( _MSC_WRITECTRL_WREN_DEFAULT << 0)

Shifted mode DEFAULT for MSC_WRITECTRL

Definition at line 159 of file efm32jg1b_msc.h .