EFM32G_DMAREQ_BitFieldsDevices
Macros |
|
| #define | DMAREQ_ADC0_SCAN ((8 << 16) + 1) |
| #define | DMAREQ_ADC0_SINGLE ((8 << 16) + 0) |
| #define | DMAREQ_AES_DATARD ((49 << 16) + 2) |
| #define | DMAREQ_AES_DATAWR ((49 << 16) + 0) |
| #define | DMAREQ_AES_KEYWR ((49 << 16) + 3) |
| #define | DMAREQ_AES_XORDATAWR ((49 << 16) + 1) |
| #define | DMAREQ_DAC0_CH0 ((10 << 16) + 0) |
| #define | DMAREQ_DAC0_CH1 ((10 << 16) + 1) |
| #define | DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) |
| #define | DMAREQ_I2C0_TXBL ((20 << 16) + 1) |
| #define | DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) |
| #define | DMAREQ_LEUART0_TXBL ((16 << 16) + 1) |
| #define | DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) |
| #define | DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) |
| #define | DMAREQ_LEUART1_TXBL ((17 << 16) + 1) |
| #define | DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) |
| #define | DMAREQ_MSC_WDATA ((48 << 16) + 0) |
| #define | DMAREQ_TIMER0_CC0 ((24 << 16) + 1) |
| #define | DMAREQ_TIMER0_CC1 ((24 << 16) + 2) |
| #define | DMAREQ_TIMER0_CC2 ((24 << 16) + 3) |
| #define | DMAREQ_TIMER0_UFOF ((24 << 16) + 0) |
| #define | DMAREQ_TIMER1_CC0 ((25 << 16) + 1) |
| #define | DMAREQ_TIMER1_CC1 ((25 << 16) + 2) |
| #define | DMAREQ_TIMER1_CC2 ((25 << 16) + 3) |
| #define | DMAREQ_TIMER1_UFOF ((25 << 16) + 0) |
| #define | DMAREQ_TIMER2_CC0 ((26 << 16) + 1) |
| #define | DMAREQ_TIMER2_CC1 ((26 << 16) + 2) |
| #define | DMAREQ_TIMER2_CC2 ((26 << 16) + 3) |
| #define | DMAREQ_TIMER2_UFOF ((26 << 16) + 0) |
| #define | DMAREQ_UART0_RXDATAV ((44 << 16) + 0) |
| #define | DMAREQ_UART0_TXBL ((44 << 16) + 1) |
| #define | DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) |
| #define | DMAREQ_USART0_RXDATAV ((12 << 16) + 0) |
| #define | DMAREQ_USART0_TXBL ((12 << 16) + 1) |
| #define | DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) |
| #define | DMAREQ_USART1_RXDATAV ((13 << 16) + 0) |
| #define | DMAREQ_USART1_TXBL ((13 << 16) + 1) |
| #define | DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) |
| #define | DMAREQ_USART2_RXDATAV ((14 << 16) + 0) |
| #define | DMAREQ_USART2_TXBL ((14 << 16) + 1) |
| #define | DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) |
Macro Definition Documentation
| #define DMAREQ_ADC0_SCAN ((8 << 16) + 1) |
DMA channel select for ADC0_SCAN
Definition at line
48
of file
efm32g_dmareq.h
.
| #define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) |
DMA channel select for ADC0_SINGLE
Definition at line
47
of file
efm32g_dmareq.h
.
| #define DMAREQ_AES_DATARD ((49 << 16) + 2) |
DMA channel select for AES_DATARD
Definition at line
86
of file
efm32g_dmareq.h
.
| #define DMAREQ_AES_DATAWR ((49 << 16) + 0) |
DMA channel select for AES_DATAWR
Definition at line
84
of file
efm32g_dmareq.h
.
| #define DMAREQ_AES_KEYWR ((49 << 16) + 3) |
DMA channel select for AES_KEYWR
Definition at line
87
of file
efm32g_dmareq.h
.
| #define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) |
DMA channel select for AES_XORDATAWR
Definition at line
85
of file
efm32g_dmareq.h
.
| #define DMAREQ_DAC0_CH0 ((10 << 16) + 0) |
DMA channel select for DAC0_CH0
Definition at line
49
of file
efm32g_dmareq.h
.
| #define DMAREQ_DAC0_CH1 ((10 << 16) + 1) |
DMA channel select for DAC0_CH1
Definition at line
50
of file
efm32g_dmareq.h
.
| #define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) |
DMA channel select for I2C0_RXDATAV
Definition at line
66
of file
efm32g_dmareq.h
.
| #define DMAREQ_I2C0_TXBL ((20 << 16) + 1) |
DMA channel select for I2C0_TXBL
Definition at line
67
of file
efm32g_dmareq.h
.
| #define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) |
DMA channel select for LEUART0_RXDATAV
Definition at line
60
of file
efm32g_dmareq.h
.
| #define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) |
DMA channel select for LEUART0_TXBL
Definition at line
61
of file
efm32g_dmareq.h
.
| #define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) |
DMA channel select for LEUART0_TXEMPTY
Definition at line
62
of file
efm32g_dmareq.h
.
| #define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) |
DMA channel select for LEUART1_RXDATAV
Definition at line
63
of file
efm32g_dmareq.h
.
| #define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) |
DMA channel select for LEUART1_TXBL
Definition at line
64
of file
efm32g_dmareq.h
.
| #define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) |
DMA channel select for LEUART1_TXEMPTY
Definition at line
65
of file
efm32g_dmareq.h
.
| #define DMAREQ_MSC_WDATA ((48 << 16) + 0) |
DMA channel select for MSC_WDATA
Definition at line
83
of file
efm32g_dmareq.h
.
| #define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) |
DMA channel select for TIMER0_CC0
Definition at line
69
of file
efm32g_dmareq.h
.
| #define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) |
DMA channel select for TIMER0_CC1
Definition at line
70
of file
efm32g_dmareq.h
.
| #define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) |
DMA channel select for TIMER0_CC2
Definition at line
71
of file
efm32g_dmareq.h
.
| #define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) |
DMA channel select for TIMER0_UFOF
Definition at line
68
of file
efm32g_dmareq.h
.
| #define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) |
DMA channel select for TIMER1_CC0
Definition at line
73
of file
efm32g_dmareq.h
.
| #define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) |
DMA channel select for TIMER1_CC1
Definition at line
74
of file
efm32g_dmareq.h
.
| #define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) |
DMA channel select for TIMER1_CC2
Definition at line
75
of file
efm32g_dmareq.h
.
| #define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) |
DMA channel select for TIMER1_UFOF
Definition at line
72
of file
efm32g_dmareq.h
.
| #define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) |
DMA channel select for TIMER2_CC0
Definition at line
77
of file
efm32g_dmareq.h
.
| #define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) |
DMA channel select for TIMER2_CC1
Definition at line
78
of file
efm32g_dmareq.h
.
| #define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) |
DMA channel select for TIMER2_CC2
Definition at line
79
of file
efm32g_dmareq.h
.
| #define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) |
DMA channel select for TIMER2_UFOF
Definition at line
76
of file
efm32g_dmareq.h
.
| #define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) |
DMA channel select for UART0_RXDATAV
Definition at line
80
of file
efm32g_dmareq.h
.
| #define DMAREQ_UART0_TXBL ((44 << 16) + 1) |
DMA channel select for UART0_TXBL
Definition at line
81
of file
efm32g_dmareq.h
.
| #define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) |
DMA channel select for UART0_TXEMPTY
Definition at line
82
of file
efm32g_dmareq.h
.
| #define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) |
DMA channel select for USART0_RXDATAV
Definition at line
51
of file
efm32g_dmareq.h
.
| #define DMAREQ_USART0_TXBL ((12 << 16) + 1) |
DMA channel select for USART0_TXBL
Definition at line
52
of file
efm32g_dmareq.h
.
| #define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) |
DMA channel select for USART0_TXEMPTY
Definition at line
53
of file
efm32g_dmareq.h
.
| #define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) |
DMA channel select for USART1_RXDATAV
Definition at line
54
of file
efm32g_dmareq.h
.
| #define DMAREQ_USART1_TXBL ((13 << 16) + 1) |
DMA channel select for USART1_TXBL
Definition at line
55
of file
efm32g_dmareq.h
.
| #define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) |
DMA channel select for USART1_TXEMPTY
Definition at line
56
of file
efm32g_dmareq.h
.
| #define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) |
DMA channel select for USART2_RXDATAV
Definition at line
57
of file
efm32g_dmareq.h
.
| #define DMAREQ_USART2_TXBL ((14 << 16) + 1) |
DMA channel select for USART2_TXBL
Definition at line
58
of file
efm32g_dmareq.h
.
| #define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) |
DMA channel select for USART2_TXEMPTY
Definition at line
59
of file
efm32g_dmareq.h
.