CoreDevices > EFR32FG1P133F256GM48
Detailed Description
Processor and Core Peripheral Section.
Macros |
|
| #define | __FPU_PRESENT 1U |
| #define | __MPU_PRESENT 1U |
| #define | __NVIC_PRIO_BITS 3U |
| #define | __Vendor_SysTickConfig 0U |
| #define | __VTOR_PRESENT 1U |
Macro Definition Documentation
| #define __FPU_PRESENT 1U |
Presence of FPU
Definition at line
113
of file
efr32fg1p133f256gm48.h
.
| #define __MPU_PRESENT 1U |
Presence of MPU
Definition at line
112
of file
efr32fg1p133f256gm48.h
.
| #define __NVIC_PRIO_BITS 3U |
NVIC interrupt priority bits
Definition at line
115
of file
efr32fg1p133f256gm48.h
.
Referenced by CORE_AtomicDisableIrq() , CORE_EnterAtomic() , CORE_IrqIsBlocked() , CORE_IrqIsDisabled() , CORE_YieldAtomic() , and LDMA_Init() .
| #define __Vendor_SysTickConfig 0U |
Is 1 if different SysTick counter is used
Definition at line
116
of file
efr32fg1p133f256gm48.h
.
| #define __VTOR_PRESENT 1U |
Presence of VTOR register in SCB
Definition at line
114
of file
efr32fg1p133f256gm48.h
.