EUSART - Extended USART

Description

Extended Universal Synchronous/Asynchronous Receiver/Transmitter.

Data Structures

struct EUSART_AdvancedInit_TypeDef
Advanced initialization structure.
struct EUSART_UartInit_TypeDef
Initialization structure.
struct EUSART_IrDAInit_TypeDef
IrDA Initialization structure.
struct EUSART_PrsTriggerInit_TypeDef
PRS Trigger initialization structure.

Functions

void EUSART_UartInitHf (EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init)
Initializes the EUSART when used in UART mode with the high frequency clock.
void EUSART_UartInitLf (EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init)
Initializes the EUSART when used in UART mode with the low frequency clock.
void EUSART_IrDAInit (EUSART_TypeDef *eusart, const EUSART_IrDAInit_TypeDef *irdaInit)
Initializes the EUSART when used in IrDA mode with the high or low frequency clock.
void EUSART_Reset (EUSART_TypeDef *eusart)
Configures the EUSART to its reset state.
void EUSART_Enable (EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable)
Enables/disables the EUSART receiver and/or transmitter.
uint8_t EUSART_Rx (EUSART_TypeDef *eusart)
Receives one 8 bit frame, (or part of 9 bit frame).
uint16_t EUSART_RxExt (EUSART_TypeDef *eusart)
Receives one 8-9 bit frame with extended information.
void EUSART_Tx (EUSART_TypeDef *eusart, uint8_t data)
Transmits one frame.
void EUSART_TxExt (EUSART_TypeDef *eusart, uint16_t data)
Transmits one 8-9 bit frame with extended control.
void EUSART_BaudrateSet (EUSART_TypeDef *eusart, uint32_t refFreq, uint32_t baudrate)
Configures the baudrate (or as close as possible to a specified baudrate).
uint32_t EUSART_BaudrateGet (EUSART_TypeDef *eusart)
Gets the current baudrate.
void EUSART_RxBlock (EUSART_TypeDef *eusart, EUSART_BlockRx_TypeDef enable)
Enables/Disables reception operation until the configured start frame is received.
void EUSART_TxTristateSet (EUSART_TypeDef *eusart, EUSART_TristateTx_TypeDef enable)
Enables/Disables the tristating of the transmitter output.
void EUSART_PrsTriggerEnable (EUSART_TypeDef *eusart, const EUSART_PrsTriggerInit_TypeDef *init)
Initializes the automatic enabling of transmissions and/or reception using the PRS as a trigger.
uint32_t EUSART_StatusGet (EUSART_TypeDef *eusart)
Gets EUSART STATUS register.
void EUSART_IntClear (EUSART_TypeDef *eusart, uint32_t flags)
Clears one or more pending EUSART interrupts.
void EUSART_IntDisable (EUSART_TypeDef *eusart, uint32_t flags)
Disables one or more EUSART interrupts.
void EUSART_IntEnable (EUSART_TypeDef *eusart, uint32_t flags)
Enables one or more EUSART interrupts.
uint32_t EUSART_IntGet (EUSART_TypeDef *eusart)
Gets pending EUSART interrupt flags.
uint32_t EUSART_IntGetEnabled (EUSART_TypeDef *eusart)
Gets enabled and pending EUSART interrupt flags.
void EUSART_IntSet (EUSART_TypeDef *eusart, uint32_t flags)
Sets one or more pending EUSART interrupts from SW.

Macros

#define EUSART_UART_INIT_DEFAULT_HF
Default configuration for EUSART initialization structure in UART mode with high-frequency clock.
#define EUSART_DEFAULT_START_FRAME 0x00u
Default start frame configuration, i.e. feature disabled.
#define EUSART_ADVANCED_INIT_DEFAULT
Default configuration for EUSART advanced initialization structure.
#define EUSART_UART_INIT_DEFAULT_LF
Default configuration for EUSART initialization structure in UART mode with low-frequency clock.
#define EUSART_IRDA_INIT_DEFAULT_HF
Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock.
#define EUSART_IRDA_INIT_DEFAULT_LF
Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock.

Typedefs

typedef uint8_t EUSART_PrsChannel_TypeDef
PRS Channel type.

Enumerations

enum EUSART_Enable_TypeDef {
eusartDisable = 0x0,
eusartEnableRx = (EUSART_CMD_RXEN | EUSART_CMD_TXDIS),
eusartEnableTx = (EUSART_CMD_TXEN | EUSART_CMD_RXDIS),
eusartEnable = (EUSART_CMD_RXEN | EUSART_CMD_TXEN)
}
Enable selection.
enum EUSART_Databits_TypeDef {
eusartDataBits7 = EUSART_FRAMECFG_DATABITS_SEVEN,
eusartDataBits8 = EUSART_FRAMECFG_DATABITS_EIGHT,
eusartDataBits9 = EUSART_FRAMECFG_DATABITS_NINE
}
Data bit selection.
enum EUSART_Parity_TypeDef {
eusartNoParity = EUSART_FRAMECFG_PARITY_NONE,
eusartEvenParity = EUSART_FRAMECFG_PARITY_EVEN,
eusartOddParity = EUSART_FRAMECFG_PARITY_ODD
}
Parity selection.
enum EUSART_Stopbits_TypeDef {
eusartStopbits0p5 = EUSART_FRAMECFG_STOPBITS_HALF,
eusartStopbits1p5 = EUSART_FRAMECFG_STOPBITS_ONEANDAHALF,
eusartStopbits1 = EUSART_FRAMECFG_STOPBITS_ONE,
eusartStopbits2 = EUSART_FRAMECFG_STOPBITS_TWO
}
Stop bits selection.
enum EUSART_OVS_TypeDef {
eusartOVS16 = EUSART_CFG0_OVS_X16,
eusartOVS8 = EUSART_CFG0_OVS_X8,
eusartOVS6 = EUSART_CFG0_OVS_X6,
eusartOVS4 = EUSART_CFG0_OVS_X4,
eusartOVS0 = EUSART_CFG0_OVS_DISABLE
}
Oversampling selection, used for asynchronous operation.
enum EUSART_HwFlowControl_TypeDef {
eusartHwFlowControlNone = 0,
eusartHwFlowControlCts ,
eusartHwFlowControlRts ,
eusartHwFlowControlCtsAndRts
}
HW flow control config.
enum EUSART_LoopbackEnable_TypeDef {
eusartLoopbackEnable = EUSART_CFG0_LOOPBK,
eusartLoopbackDisable = _EUSART_CFG0_RESETVALUE
}
Loopback enable.
enum EUSART_MajorityVote_TypeDef {
eusartMajorityVoteEnable = EUSART_CFG0_MVDIS_DEFAULT,
eusartMajorityVoteDisable = EUSART_CFG0_MVDIS
}
Majority vote enable.
enum EUSART_BlockRx_TypeDef {
eusartBlockRxEnable = EUSART_CMD_RXBLOCKEN,
eusartBlockRxDisable = EUSART_CMD_RXBLOCKDIS
}
Block reception enable.
enum EUSART_TristateTx_TypeDef {
eusartTristateTxEnable = EUSART_CMD_TXTRIEN,
eusartTristateTxDisable = EUSART_CMD_TXTRIDIS
}
Tx output tristate enable.
enum EUSART_IrDARxFilterEnable_TypeDef {
eusartIrDARxFilterEnable = EUSART_IRHFCFG_IRHFFILT_ENABLE,
eusartIrDARxFilterDisable = EUSART_IRHFCFG_IRHFFILT_DISABLE
}
IrDA filter enable.
enum EUSART_IrDAPulseWidth_Typedef {
eusartIrDAPulseWidthOne = EUSART_IRHFCFG_IRHFPW_ONE,
eusartIrDAPulseWidthTwo = EUSART_IRHFCFG_IRHFPW_TWO,
eusartIrDAPulseWidthThree = EUSART_IRHFCFG_IRHFPW_THREE,
eusartIrDAPulseWidthFour = EUSART_IRHFCFG_IRHFPW_FOUR
}
Pulse width selection for IrDA mode.
enum EUSART_PrsTriggerEnable_TypeDef {
eusartPrsTriggerDisable = 0x0,
eusartPrsTriggerEnableRx = EUSART_TRIGCTRL_RXTEN,
eusartPrsTriggerEnableTx = EUSART_TRIGCTRL_TXTEN,
eusartPrsTriggerEnableRxTx = (EUSART_TRIGCTRL_RXTEN | EUSART_TRIGCTRL_TXTEN)
}
PRS trigger enable.
enum EUSART_InvertIO_TypeDef {
eusartInvertIODisable = (EUSART_CFG0_RXINV_DISABLE | EUSART_CFG0_TXINV_DISABLE),
eusartInvertRxEnable = EUSART_CFG0_RXINV_ENABLE,
eusartInvertTxEnable = EUSART_CFG0_TXINV_ENABLE,
eusartInvertIOEnable = (EUSART_CFG0_RXINV_ENABLE | EUSART_CFG0_TXINV_ENABLE)
}
IO polarity selection.

Function Documentation

EUSART_UartInitHf()

void EUSART_UartInitHf ( EUSART_TypeDef * eusart,
const EUSART_UartInit_TypeDef * init
)

Initializes the EUSART when used in UART mode with the high frequency clock.

Parameters
eusart Pointer to the EUSART peripheral register block.
init A pointer to the initialization structure.

Initializes the EUSART when used in UART mode with the high frequency clock.

EUSART_UartInitLf()

void EUSART_UartInitLf ( EUSART_TypeDef * eusart,
const EUSART_UartInit_TypeDef * init
)

Initializes the EUSART when used in UART mode with the low frequency clock.

Parameters
eusart Pointer to the EUSART peripheral register block.
init A pointer to the initialization structure.

Initializes the EUSART when used in UART mode with the low frequency clock.

Note
(1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral clock frequency must be at least three times higher than the chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), thus 32768 / 3 ~ 9600 baudrate.

EUSART_IrDAInit()

void EUSART_IrDAInit ( EUSART_TypeDef * eusart,
const EUSART_IrDAInit_TypeDef * irdaInit
)

Initializes the EUSART when used in IrDA mode with the high or low frequency clock.

Parameters
eusart Pointer to the EUSART peripheral register block.
irdaInit A pointer to the initialization structure.

EUSART_Reset()

void EUSART_Reset ( EUSART_TypeDef * eusart )

Configures the EUSART to its reset state.

Parameters
eusart Pointer to the EUSART peripheral register block.

Configures the EUSART to its reset state.

EUSART_Enable()

void EUSART_Enable ( EUSART_TypeDef * eusart,
EUSART_Enable_TypeDef enable
)

Enables/disables the EUSART receiver and/or transmitter.

Parameters
eusart Pointer to the EUSART peripheral register block.
enable Select the status for the receiver and transmitter.

EUSART_Rx()

uint8_t EUSART_Rx ( EUSART_TypeDef * eusart )

Receives one 8 bit frame, (or part of 9 bit frame).

Parameters
eusart Pointer to the EUSART peripheral register block.
Note
This function is normally used to receive one frame when operating with frame length of 8 bits. See EUSART_RxExt() for reception of 9 bit frames. Notice that possible parity/stop bits are not considered a part of the specified frame bit length.
This function will stall if buffer is empty until data is received.
Returns
Data received.

EUSART_RxExt()

uint16_t EUSART_RxExt ( EUSART_TypeDef * eusart )

Receives one 8-9 bit frame with extended information.

Parameters
eusart Pointer to the EUSART peripheral register block.
Note
This function is normally used to receive one frame and additional RX status information.
This function will stall if buffer is empty until data is received.
Returns
Data received and receive status.

EUSART_Tx()

void EUSART_Tx ( EUSART_TypeDef * eusart,
uint8_t data
)

Transmits one frame.

Parameters
eusart Pointer to the EUSART peripheral register block.
data Data to transmit.
Note
Depending on the frame length configuration, 8 (least significant) bits from data are transmitted. If the frame length is 9, 8 bits are transmitted from data . See EUSART_TxExt() for transmitting 9 bit frame with full control of all 9 bits.
This function will stall if the 4 frame FIFO is full, until the buffer becomes available.

EUSART_TxExt()

void EUSART_TxExt ( EUSART_TypeDef * eusart,
uint16_t data
)

Transmits one 8-9 bit frame with extended control.

Parameters
eusart Pointer to the EUSART peripheral register block.
data Data to transmit.
Note
Possible parity/stop bits in asynchronous mode are not considered part of a specified frame bit length.
This function will stall if buffer is full until the buffer becomes available.

EUSART_BaudrateSet()

void EUSART_BaudrateSet ( EUSART_TypeDef * eusart,
uint32_t refFreq,
uint32_t baudrate
)

Configures the baudrate (or as close as possible to a specified baudrate).

Parameters
eusart Pointer to the EUSART peripheral register block.
refFreq The EUSART reference clock frequency in Hz that will be used. If set to 0, the currently configured peripheral clock is used.
baudrate A baudrate to try to achieve.
Note
(1) When the oversampling is disabled, the peripheral clock frequency must be at least three times higher than the chosen baud rate.

EUSART_BaudrateGet()

uint32_t EUSART_BaudrateGet ( EUSART_TypeDef * eusart )

Gets the current baudrate.

Parameters
eusart Pointer to the EUSART peripheral register block.
Returns
The current baudrate.

EUSART_RxBlock()

void EUSART_RxBlock ( EUSART_TypeDef * eusart,
EUSART_BlockRx_TypeDef enable
)

Enables/Disables reception operation until the configured start frame is received.

Parameters
eusart Pointer to the EUSART peripheral register block.
enable Select the receiver blocking status.

Enables/Disables reception operation until the configured start frame is received.

EUSART_TxTristateSet()

void EUSART_TxTristateSet ( EUSART_TypeDef * eusart,
EUSART_TristateTx_TypeDef enable
)

Enables/Disables the tristating of the transmitter output.

Parameters
eusart Pointer to the EUSART peripheral register block.
enable Select the transmitter tristate status.

EUSART_PrsTriggerEnable()

void EUSART_PrsTriggerEnable ( EUSART_TypeDef * eusart,
const EUSART_PrsTriggerInit_TypeDef * init
)

Initializes the automatic enabling of transmissions and/or reception using the PRS as a trigger.

Note
Initialize EUSART with sl_eusart_initHf() or sl_eusart_initLf() before enabling the PRS trigger.
Parameters
eusart Pointer to the EUSART peripheral register block.
init Pointer to the initialization structure.

EUSART_StatusGet()

uint32_t EUSART_StatusGet ( EUSART_TypeDef * eusart )
inline

Gets EUSART STATUS register.

Parameters
eusart Pointer to the EUSART peripheral register block.
Returns
STATUS register value.

EUSART_IntClear()

void EUSART_IntClear ( EUSART_TypeDef * eusart,
uint32_t flags
)
inline

Clears one or more pending EUSART interrupts.

Parameters
eusart Pointer to the EUSART peripheral register block.
flags Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

EUSART_IntDisable()

void EUSART_IntDisable ( EUSART_TypeDef * eusart,
uint32_t flags
)
inline

Disables one or more EUSART interrupts.

Parameters
eusart Pointer to the EUSART peripheral register block.
flags Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

EUSART_IntEnable()

void EUSART_IntEnable ( EUSART_TypeDef * eusart,
uint32_t flags
)
inline

Enables one or more EUSART interrupts.

Parameters
eusart Pointer to the EUSART peripheral register block.
flags Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

EUSART_IntGet()

uint32_t EUSART_IntGet ( EUSART_TypeDef * eusart )
inline

Gets pending EUSART interrupt flags.

Parameters
eusart Pointer to the EUSART peripheral register block.
Returns
Pending EUSART interrupt sources.

EUSART_IntGetEnabled()

uint32_t EUSART_IntGetEnabled ( EUSART_TypeDef * eusart )
inline

Gets enabled and pending EUSART interrupt flags.

Useful for handling more interrupt sources in the same interrupt handler.

Parameters
eusart Pointer to the EUSART peripheral register block.
Returns
Pending and enabled EUSART interrupt sources.

EUSART_IntSet()

void EUSART_IntSet ( EUSART_TypeDef * eusart,
uint32_t flags
)
inline

Sets one or more pending EUSART interrupts from SW.

Parameters
eusart Pointer to the EUSART peripheral register block.
flags Interrupt source(s) to set to pending. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

Macro Definition Documentation

EUSART_UART_INIT_DEFAULT_HF

#define EUSART_UART_INIT_DEFAULT_HF
Value:
{ \
eusartEnable, /* Enable RX/TX when initialization completed. */ \
0, /* Use current configured reference clock for configuring baud rate.*/ \
115200, /* 115200 bits/s. */ \
eusartOVS16, /* Oversampling x16. */ \
eusartDataBits8, /* 8 data bits. */ \
eusartNoParity, /* No parity. */ \
eusartStopbits1, /* 1 stop bit. */ \
eusartMajorityVoteEnable, /* Majority vote enabled. */ \
eusartLoopbackDisable, /* Loop back disabled. */ \
NULL, /* Default advanced settings. */ \
}

Default configuration for EUSART initialization structure in UART mode with high-frequency clock.

EUSART_DEFAULT_START_FRAME

#define EUSART_DEFAULT_START_FRAME   0x00u

Default start frame configuration, i.e. feature disabled.

EUSART_ADVANCED_INIT_DEFAULT

#define EUSART_ADVANCED_INIT_DEFAULT
Value:
{ \
eusartHwFlowControlNone, /* Flow control disabled. */ \
false, /* Collision dectection disabled. */ \
false, /* Data is sent with the least significant bit first. */ \
eusartInvertIODisable, /* Rx and Tx signal active high. */ \
false, /* No DMA wake up on reception. */ \
false, /* No DMA wake up on transmission. */ \
false, /* Halt DMA on error disabled. */ \
EUSART_DEFAULT_START_FRAME, /* No start frame. */ \
false, /* Tx auto tristate disabled. */ \
false, /* Do not use PRS signal as Rx signal.*/ \
( EUSART_PrsChannel_TypeDef ) 0u, /* EUSART Rx connected to prs channel 0. */ \
false , /* Multiprocessor mode disabled. */ \
false , /* Multiprocessor address bit : 0.*/ \
}

Default configuration for EUSART advanced initialization structure.

EUSART_UART_INIT_DEFAULT_LF

#define EUSART_UART_INIT_DEFAULT_LF
Value:
{ \
eusartEnable, /* Enable RX/TX when initialization completed. */ \
0, /* Use current configured reference clock for configuring baud rate.*/ \
9600, /* 9600 bits/s. */ \
eusartOVS0, /* Oversampling disabled. */ \
eusartDataBits8, /* 8 data bits. */ \
eusartNoParity, /* No parity. */ \
eusartStopbits1, /* 1 stop bit. */ \
eusartMajorityVoteDisable, /* Majority vote enabled. */ \
eusartLoopbackDisable, /* Loop back disabled. */ \
NULL, /* Default advanced settings. */ \
}

Default configuration for EUSART initialization structure in UART mode with low-frequency clock.

EUSART_IRDA_INIT_DEFAULT_HF

#define EUSART_IRDA_INIT_DEFAULT_HF
Value:
{ \
EUSART_UART_INIT_DEFAULT_HF, /* Default high frequency configuration. */ \
false, /* Disable IrDA low frequency mode. */ \
eusartIrDARxFilterDisable, /* Rx Filter disabled. */ \
eusartIrDAPulseWidthOne, /* Pulse width is set to 1/16. */ \
}

Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock.

EUSART_IRDA_INIT_DEFAULT_LF

#define EUSART_IRDA_INIT_DEFAULT_LF
Value:
{ \
{ \
eusartEnableRx, /* Enable RX when initialization completed (Tx not allowed). */ \
0, /* Use current configured reference clock for configuring baud rate.*/ \
9600, /* 9600 bits/s. */ \
eusartOVS0, /* Oversampling disabled. */ \
eusartDataBits8, /* 8 data bits. */ \
eusartNoParity, /* No parity. */ \
eusartStopbits1, /* 1 stop bit. */ \
eusartMajorityVoteDisable, /* Majority vote enabled. */ \
eusartLoopbackDisable, /* Loop back disabled. */ \
NULL, /* Default advanced settings. */ \
}, \
true, /* Enable IrDA low frequency mode. */ \
eusartIrDARxFilterDisable, /* Rx Filter disabled. */ \
eusartIrDAPulseWidthOne, /* Pulse width is set to 1. */ \
}

Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock.

Typedef Documentation

EUSART_PrsChannel_TypeDef

PRS Channel type.

Enumeration Type Documentation

EUSART_Enable_TypeDef

Enable selection.

Enumerator
eusartDisable

Disable the peripheral.

eusartEnableRx

Enable receiver only, transmitter disabled.

eusartEnableTx

Enable transmitter only, receiver disabled.

eusartEnable

Enable both receiver and transmitter.

EUSART_Databits_TypeDef

Data bit selection.

Enumerator
eusartDataBits7

7 data bits.

eusartDataBits8

8 data bits.

eusartDataBits9

9 data bits.

EUSART_Parity_TypeDef

Parity selection.

Enumerator
eusartNoParity

No parity.

eusartEvenParity

Even parity.

eusartOddParity

Odd parity.

EUSART_Stopbits_TypeDef

Stop bits selection.

Enumerator
eusartStopbits0p5

0.5 stop bits.

eusartStopbits1p5

1.5 stop bits.

eusartStopbits1

1 stop bits.

eusartStopbits2

2 stop bits.

EUSART_OVS_TypeDef

Oversampling selection, used for asynchronous operation.

Enumerator
eusartOVS16

16x oversampling (normal).

eusartOVS8

8x oversampling.

eusartOVS6

6x oversampling.

eusartOVS4

4x oversampling.

eusartOVS0

Oversampling disabled.

EUSART_HwFlowControl_TypeDef

HW flow control config.

Enumerator
eusartHwFlowControlNone

No HW Flow Control.

eusartHwFlowControlCts

CTS HW Flow Control.

eusartHwFlowControlRts

RTS HW Flow Control.

eusartHwFlowControlCtsAndRts

CTS and RTS HW Flow Control.

EUSART_LoopbackEnable_TypeDef

Loopback enable.

EUSART_MajorityVote_TypeDef

Majority vote enable.

EUSART_BlockRx_TypeDef

Block reception enable.

EUSART_TristateTx_TypeDef

Tx output tristate enable.

EUSART_IrDARxFilterEnable_TypeDef

IrDA filter enable.

EUSART_IrDAPulseWidth_Typedef

Pulse width selection for IrDA mode.

Enumerator
eusartIrDAPulseWidthOne

IrDA pulse width is 1/16 for OVS=X16 and 1/8 for OVS=X8.

eusartIrDAPulseWidthTwo

IrDA pulse width is 2/16 for OVS=X16 and 2/8 for OVS=X8.

eusartIrDAPulseWidthThree

IrDA pulse width is 3/16 for OVS=X16 and 3/8 for OVS=X8.

eusartIrDAPulseWidthFour

IrDA pulse width is 4/16 for OVS=X16 and 4/8 for OVS=X8.

EUSART_PrsTriggerEnable_TypeDef

PRS trigger enable.

Enumerator
eusartPrsTriggerDisable

Disable trigger on both receiver and transmitter.

eusartPrsTriggerEnableRx

Enable receive trigger only, transmit disabled.

eusartPrsTriggerEnableTx

Enable transmit trigger only, receive disabled.

eusartPrsTriggerEnableRxTx

Enable trigger on both receive and transmit.

EUSART_InvertIO_TypeDef

IO polarity selection.

Enumerator
eusartInvertIODisable

Disable inversion on both Rx and Tx signals.

eusartInvertRxEnable

Invert Rx signal, before receiver.

eusartInvertTxEnable

Invert Tx signal, after transmitter.

eusartInvertIOEnable

Enable trigger on both receive and transmit.