DEVINFO Bit FieldsDevices > Device Information and Calibration

Macros

#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL
#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8
#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL
#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24
#define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL
#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL
#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4
#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL
#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20
#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL
#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0
#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL
#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16
#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL
#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24
#define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL
#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8
#define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL
#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL
#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20
#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL
#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4
#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL
#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16
#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL
#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0
#define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL
#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL
#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4
#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL
#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0
#define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL
#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL
#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4
#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25
#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21
#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8
#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27
#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16
#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL
#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24
#define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL
#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL
#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0
#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28
#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25
#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21
#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8
#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27
#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16
#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL
#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24
#define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL
#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL
#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0
#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28
#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25
#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21
#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8
#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27
#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16
#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL
#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24
#define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL
#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL
#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0
#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28
#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25
#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21
#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8
#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27
#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16
#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL
#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24
#define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL
#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL
#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0
#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28
#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25
#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21
#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8
#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27
#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16
#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL
#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24
#define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL
#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL
#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0
#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28
#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25
#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21
#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8
#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27
#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16
#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL
#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24
#define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL
#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL
#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0
#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28
#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25
#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21
#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8
#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27
#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16
#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL
#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24
#define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL
#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL
#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0
#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28
#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25
#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21
#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8
#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27
#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16
#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL
#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24
#define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL
#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL
#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0
#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28
#define _DEVINFO_CAL_CRC_MASK 0xFFFFUL
#define _DEVINFO_CAL_CRC_SHIFT 0
#define _DEVINFO_CAL_MASK 0x00FFFFFFUL
#define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL
#define _DEVINFO_CAL_TEMP_SHIFT 16
#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL
#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL
#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16
#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL
#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0
#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL
#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8
#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL
#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16
#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL
#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24
#define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL
#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL
#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0
#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL
#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8
#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24
#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL
#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL
#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0
#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL
#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16
#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL
#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8
#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL
#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24
#define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL
#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL
#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0
#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL
#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16
#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL
#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8
#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL
#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24
#define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL
#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL
#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0
#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL
#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16
#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL
#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8
#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL
#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24
#define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL
#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL
#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0
#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL
#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16
#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL
#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8
#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL
#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24
#define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL
#define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL
#define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0
#define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL
#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL
#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0
#define _DEVINFO_EMUTEMP_MASK 0x000000FFUL
#define _DEVINFO_EUI48H_MASK 0x0000FFFFUL
#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL
#define _DEVINFO_EUI48H_OUI48H_SHIFT 0
#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL
#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL
#define _DEVINFO_EUI48L_OUI48L_SHIFT 24
#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL
#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0
#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL
#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL
#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8
#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL
#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL
#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL
#define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL
#define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL
#define _DEVINFO_EXTINFO_REV_SHIFT 16
#define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL
#define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL
#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL
#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL
#define _DEVINFO_EXTINFO_TYPE_SHIFT 0
#define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25
#define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21
#define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8
#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27
#define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16
#define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL
#define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24
#define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL
#define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL
#define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0
#define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28
#define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25
#define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21
#define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8
#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27
#define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16
#define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL
#define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24
#define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL
#define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL
#define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0
#define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28
#define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25
#define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21
#define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8
#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27
#define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16
#define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL
#define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24
#define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL
#define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL
#define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0
#define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28
#define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25
#define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21
#define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8
#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27
#define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16
#define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL
#define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24
#define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL
#define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL
#define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0
#define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28
#define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25
#define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21
#define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8
#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27
#define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16
#define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL
#define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24
#define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL
#define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL
#define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0
#define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28
#define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25
#define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21
#define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8
#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27
#define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16
#define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL
#define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24
#define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL
#define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL
#define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0
#define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28
#define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25
#define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21
#define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8
#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27
#define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16
#define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL
#define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24
#define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL
#define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL
#define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0
#define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28
#define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL
#define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25
#define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL
#define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21
#define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL
#define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8
#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL
#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27
#define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL
#define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16
#define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL
#define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24
#define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL
#define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL
#define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0
#define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL
#define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28
#define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL
#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL
#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0
#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL
#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8
#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL
#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16
#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL
#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24
#define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL
#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL
#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0
#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL
#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8
#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL
#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16
#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL
#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24
#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL
#define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL
#define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16
#define _DEVINFO_MEMINFO_PKGTYPE_KGD 0x00000044UL
#define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL
#define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL
#define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL
#define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8
#define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL
#define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL
#define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL
#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL
#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL
#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL
#define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0
#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL
#define _DEVINFO_MSIZE_FLASH_SHIFT 0
#define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL
#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL
#define _DEVINFO_MSIZE_SRAM_SHIFT 16
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B 0x00000064UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B 0x00000067UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B 0x00000038UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P 0x00000037UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V 0x00000039UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B 0x0000003EUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P 0x0000003DUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V 0x0000003FUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B 0x00000035UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P 0x00000034UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V 0x00000036UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL
#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL
#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL
#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL
#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL
#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL
#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16
#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL
#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL
#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL
#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL
#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0
#define _DEVINFO_PART_MASK 0xFFFFFFFFUL
#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL
#define _DEVINFO_PART_PROD_REV_SHIFT 24
#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL
#define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL
#define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0
#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL
#define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL
#define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0
#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL
#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20
#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL
#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16
#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL
#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28
#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL
#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24
#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL
#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4
#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL
#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0
#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL
#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12
#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL
#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8
#define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL
#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL
#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4
#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL
#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0
#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL
#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12
#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL
#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8
#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL
#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20
#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL
#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16
#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL
#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28
#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL
#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24
#define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL
#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL
#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20
#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL
#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16
#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL
#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28
#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL
#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24
#define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL
#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL
#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4
#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL
#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0
#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL
#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12
#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL
#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8
#define DEVINFO_EXTINFO_CONNECTION_NONE ( _DEVINFO_EXTINFO_CONNECTION_NONE << 8)
#define DEVINFO_EXTINFO_CONNECTION_SPI ( _DEVINFO_EXTINFO_CONNECTION_SPI << 8)
#define DEVINFO_EXTINFO_REV_NONE ( _DEVINFO_EXTINFO_REV_NONE << 16)
#define DEVINFO_EXTINFO_REV_REV1 ( _DEVINFO_EXTINFO_REV_REV1 << 16)
#define DEVINFO_EXTINFO_TYPE_AT25S041 ( _DEVINFO_EXTINFO_TYPE_AT25S041 << 0)
#define DEVINFO_EXTINFO_TYPE_IS25LQ040B ( _DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0)
#define DEVINFO_EXTINFO_TYPE_NONE ( _DEVINFO_EXTINFO_TYPE_NONE << 0)
#define DEVINFO_MEMINFO_PKGTYPE_KGD ( _DEVINFO_MEMINFO_PKGTYPE_KGD << 8)
#define DEVINFO_MEMINFO_PKGTYPE_QFN ( _DEVINFO_MEMINFO_PKGTYPE_QFN << 8)
#define DEVINFO_MEMINFO_PKGTYPE_QFP ( _DEVINFO_MEMINFO_PKGTYPE_QFP << 8)
#define DEVINFO_MEMINFO_PKGTYPE_WLCSP ( _DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8)
#define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 ( _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0)
#define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 ( _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0)
#define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 ( _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0)
#define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 ( _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0)
#define DEVINFO_PART_DEVICE_FAMILY_EFM32G ( _DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG ( _DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B ( _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG ( _DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B ( _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B ( _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG ( _DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B ( _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B ( _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG ( _DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B ( _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG ( _DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG ( _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EZR32HG ( _DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EZR32LG ( _DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_EZR32WG ( _DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_G ( _DEVINFO_PART_DEVICE_FAMILY_G << 16)
#define DEVINFO_PART_DEVICE_FAMILY_GG ( _DEVINFO_PART_DEVICE_FAMILY_GG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_HG ( _DEVINFO_PART_DEVICE_FAMILY_HG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_LG ( _DEVINFO_PART_DEVICE_FAMILY_LG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_TG ( _DEVINFO_PART_DEVICE_FAMILY_TG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_WG ( _DEVINFO_PART_DEVICE_FAMILY_WG << 16)
#define DEVINFO_PART_DEVICE_FAMILY_ZG ( _DEVINFO_PART_DEVICE_FAMILY_ZG << 16)

Macro Definition Documentation

#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK   0x7F00UL

Bit mask for GAIN1V25

Definition at line 353 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT   8

Shift value for GAIN1V25

Definition at line 352 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK   0x7F000000UL

Bit mask for GAIN2V5

Definition at line 359 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT   24

Shift value for GAIN2V5

Definition at line 358 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL0_MASK   0x7FFF7FFFUL

Mask for DEVINFO_ADC0CAL0

Definition at line 347 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK   0xF0UL

Bit mask for NEGSEOFFSET1V25

Definition at line 351 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT   4

Shift value for NEGSEOFFSET1V25

Definition at line 350 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK   0xF00000UL

Bit mask for NEGSEOFFSET2V5

Definition at line 357 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT   20

Shift value for NEGSEOFFSET2V5

Definition at line 356 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK   0xFUL

Bit mask for OFFSET1V25

Definition at line 349 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT   0

Shift value for OFFSET1V25

Definition at line 348 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK   0xF0000UL

Bit mask for OFFSET2V5

Definition at line 355 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT   16

Shift value for OFFSET2V5

Definition at line 354 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK   0x7F000000UL

Bit mask for GAIN5VDIFF

Definition at line 374 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT   24

Shift value for GAIN5VDIFF

Definition at line 373 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL1_GAINVDD_MASK   0x7F00UL

Bit mask for GAINVDD

Definition at line 368 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT   8

Shift value for GAINVDD

Definition at line 367 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL1_MASK   0x7FFF7FFFUL

Mask for DEVINFO_ADC0CAL1

Definition at line 362 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK   0xF00000UL

Bit mask for NEGSEOFFSET5VDIFF

Definition at line 372 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT   20

Shift value for NEGSEOFFSET5VDIFF

Definition at line 371 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK   0xF0UL

Bit mask for NEGSEOFFSETVDD

Definition at line 366 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT   4

Shift value for NEGSEOFFSETVDD

Definition at line 365 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK   0xF0000UL

Bit mask for OFFSET5VDIFF

Definition at line 370 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT   16

Shift value for OFFSET5VDIFF

Definition at line 369 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK   0xFUL

Bit mask for OFFSETVDD

Definition at line 364 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT   0

Shift value for OFFSETVDD

Definition at line 363 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL2_MASK   0x000000FFUL

Mask for DEVINFO_ADC0CAL2

Definition at line 377 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK   0xF0UL

Bit mask for NEGSEOFFSET2XVDD

Definition at line 381 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT   4

Shift value for NEGSEOFFSET2XVDD

Definition at line 380 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK   0xFUL

Bit mask for OFFSET2XVDD

Definition at line 379 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT   0

Shift value for OFFSET2XVDD

Definition at line 378 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL3_MASK   0x0000FFF0UL

Mask for DEVINFO_ADC0CAL3

Definition at line 384 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK   0xFFF0UL

Bit mask for TEMPREAD1V25

Definition at line 386 of file efr32bg1p_devinfo.h .

#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT   4

Shift value for TEMPREAD1V25

Definition at line 385 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 553 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 552 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 549 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 548 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 545 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 544 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 555 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 554 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 547 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 546 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 551 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 550 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL0

Definition at line 541 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 543 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 542 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 557 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 556 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 648 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 647 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 644 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 643 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 640 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 639 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 650 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 649 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 642 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 641 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 646 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 645 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL10

Definition at line 636 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 638 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 637 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 652 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 651 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 667 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 666 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 663 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 662 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 659 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 658 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 669 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 668 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 661 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 660 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 665 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 664 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL11

Definition at line 655 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 657 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 656 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 671 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 670 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 686 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 685 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 682 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 681 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 678 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 677 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 688 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 687 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 680 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 679 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 684 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 683 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL12

Definition at line 674 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 676 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 675 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 690 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 689 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 572 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 571 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 568 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 567 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 564 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 563 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 574 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 573 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 566 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 565 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 570 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 569 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL3

Definition at line 560 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 562 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 561 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 576 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 575 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 591 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 590 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 587 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 586 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 583 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 582 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 593 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 592 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 585 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 584 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 589 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 588 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL6

Definition at line 579 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 581 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 580 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 595 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 594 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 610 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 609 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 606 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 605 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 602 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 601 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 612 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 611 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 604 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 603 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 608 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 607 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL7

Definition at line 598 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 600 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 599 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 614 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 613 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 629 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 628 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 625 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 624 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 621 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 620 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 631 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 630 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 623 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 622 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 627 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 626 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL8

Definition at line 617 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 619 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 618 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 633 of file efr32bg1p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 632 of file efr32bg1p_devinfo.h .

#define _DEVINFO_CAL_CRC_MASK   0xFFFFUL

Bit mask for CRC

Definition at line 121 of file efr32bg1p_devinfo.h .

#define _DEVINFO_CAL_CRC_SHIFT   0

Shift value for CRC

Definition at line 120 of file efr32bg1p_devinfo.h .

#define _DEVINFO_CAL_MASK   0x00FFFFFFUL

Mask for DEVINFO_CAL

Definition at line 119 of file efr32bg1p_devinfo.h .

#define _DEVINFO_CAL_TEMP_MASK   0xFF0000UL

Bit mask for TEMP

Definition at line 123 of file efr32bg1p_devinfo.h .

Referenced by SYSTEM_GetCalibrationTemperature() , and TEMPDRV_Init() .

#define _DEVINFO_CAL_TEMP_SHIFT   16

Shift value for TEMP

Definition at line 122 of file efr32bg1p_devinfo.h .

Referenced by SYSTEM_GetCalibrationTemperature() , and TEMPDRV_Init() .

#define _DEVINFO_CUSTOMINFO_MASK   0xFFFF0000UL

Mask for DEVINFO_CUSTOMINFO

Definition at line 161 of file efr32bg1p_devinfo.h .

#define _DEVINFO_CUSTOMINFO_PARTNO_MASK   0xFFFF0000UL

Bit mask for PARTNO

Definition at line 163 of file efr32bg1p_devinfo.h .

#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT   16

Shift value for PARTNO

Definition at line 162 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK   0xFFUL

Bit mask for 1V2LNATT0

Definition at line 774 of file efr32bg1p_devinfo.h .

Referenced by EMU_DCDCOutputVoltageSet() .

#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT   0

Shift value for 1V2LNATT0

Definition at line 773 of file efr32bg1p_devinfo.h .

Referenced by EMU_DCDCOutputVoltageSet() .

#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK   0xFF00UL

Bit mask for 1V8LNATT0

Definition at line 776 of file efr32bg1p_devinfo.h .

Referenced by EMU_DCDCOutputVoltageSet() .

#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT   8

Shift value for 1V8LNATT0

Definition at line 775 of file efr32bg1p_devinfo.h .

Referenced by EMU_DCDCOutputVoltageSet() .

#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK   0xFF0000UL

Bit mask for 1V8LNATT1

Definition at line 778 of file efr32bg1p_devinfo.h .

Referenced by EMU_DCDCOutputVoltageSet() .

#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT   16

Shift value for 1V8LNATT1

Definition at line 777 of file efr32bg1p_devinfo.h .

Referenced by EMU_DCDCOutputVoltageSet() .

#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK   0xFF000000UL

Bit mask for 3V0LNATT1

Definition at line 780 of file efr32bg1p_devinfo.h .

Referenced by EMU_DCDCOutputVoltageSet() .

#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT   24

Shift value for 3V0LNATT1

Definition at line 779 of file efr32bg1p_devinfo.h .

Referenced by EMU_DCDCOutputVoltageSet() .

#define _DEVINFO_DCDCLNVCTRL0_MASK   0xFFFFFFFFUL

Mask for DEVINFO_DCDCLNVCTRL0

Definition at line 772 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK   0xFFUL

Bit mask for LPCMPHYSSELLPATT0

Definition at line 829 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT   0

Shift value for LPCMPHYSSELLPATT0

Definition at line 828 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK   0xFF00UL

Bit mask for LPCMPHYSSELLPATT1

Definition at line 831 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT   8

Shift value for LPCMPHYSSELLPATT1

Definition at line 830 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK   0x0000FFFFUL

Mask for DEVINFO_DCDCLPCMPHYSSEL0

Definition at line 827 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK   0xFFUL

Bit mask for LPCMPHYSSELLPCMPBIAS0

Definition at line 836 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT   0

Shift value for LPCMPHYSSELLPCMPBIAS0

Definition at line 835 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK   0xFF00UL

Bit mask for LPCMPHYSSELLPCMPBIAS1

Definition at line 838 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT   8

Shift value for LPCMPHYSSELLPCMPBIAS1

Definition at line 837 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK   0xFF0000UL

Bit mask for LPCMPHYSSELLPCMPBIAS2

Definition at line 840 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT   16

Shift value for LPCMPHYSSELLPCMPBIAS2

Definition at line 839 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK   0xFF000000UL

Bit mask for LPCMPHYSSELLPCMPBIAS3

Definition at line 842 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT   24

Shift value for LPCMPHYSSELLPCMPBIAS3

Definition at line 841 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK   0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPCMPHYSSEL1

Definition at line 834 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK   0xFFUL

Bit mask for 1V2LPATT0LPCMPBIAS0

Definition at line 785 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT   0

Shift value for 1V2LPATT0LPCMPBIAS0

Definition at line 784 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK   0xFF0000UL

Bit mask for 1V2LPATT0LPCMPBIAS1

Definition at line 789 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT   16

Shift value for 1V2LPATT0LPCMPBIAS1

Definition at line 788 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK   0xFF00UL

Bit mask for 1V8LPATT0LPCMPBIAS0

Definition at line 787 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT   8

Shift value for 1V8LPATT0LPCMPBIAS0

Definition at line 786 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK   0xFF000000UL

Bit mask for 1V8LPATT0LPCMPBIAS1

Definition at line 791 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT   24

Shift value for 1V8LPATT0LPCMPBIAS1

Definition at line 790 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_MASK   0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPVCTRL0

Definition at line 783 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK   0xFFUL

Bit mask for 1V2LPATT0LPCMPBIAS2

Definition at line 796 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT   0

Shift value for 1V2LPATT0LPCMPBIAS2

Definition at line 795 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK   0xFF0000UL

Bit mask for 1V2LPATT0LPCMPBIAS3

Definition at line 800 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT   16

Shift value for 1V2LPATT0LPCMPBIAS3

Definition at line 799 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK   0xFF00UL

Bit mask for 1V8LPATT0LPCMPBIAS2

Definition at line 798 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT   8

Shift value for 1V8LPATT0LPCMPBIAS2

Definition at line 797 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK   0xFF000000UL

Bit mask for 1V8LPATT0LPCMPBIAS3

Definition at line 802 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT   24

Shift value for 1V8LPATT0LPCMPBIAS3

Definition at line 801 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_MASK   0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPVCTRL1

Definition at line 794 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK   0xFFUL

Bit mask for 1V8LPATT1LPCMPBIAS0

Definition at line 807 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT   0

Shift value for 1V8LPATT1LPCMPBIAS0

Definition at line 806 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK   0xFF0000UL

Bit mask for 1V8LPATT1LPCMPBIAS1

Definition at line 811 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT   16

Shift value for 1V8LPATT1LPCMPBIAS1

Definition at line 810 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK   0xFF00UL

Bit mask for 3V0LPATT1LPCMPBIAS0

Definition at line 809 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT   8

Shift value for 3V0LPATT1LPCMPBIAS0

Definition at line 808 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK   0xFF000000UL

Bit mask for 3V0LPATT1LPCMPBIAS1

Definition at line 813 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT   24

Shift value for 3V0LPATT1LPCMPBIAS1

Definition at line 812 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_MASK   0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPVCTRL2

Definition at line 805 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK   0xFFUL

Bit mask for 1V8LPATT1LPCMPBIAS2

Definition at line 818 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT   0

Shift value for 1V8LPATT1LPCMPBIAS2

Definition at line 817 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK   0xFF0000UL

Bit mask for 1V8LPATT1LPCMPBIAS3

Definition at line 822 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT   16

Shift value for 1V8LPATT1LPCMPBIAS3

Definition at line 821 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK   0xFF00UL

Bit mask for 3V0LPATT1LPCMPBIAS2

Definition at line 820 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT   8

Shift value for 3V0LPATT1LPCMPBIAS2

Definition at line 819 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK   0xFF000000UL

Bit mask for 3V0LPATT1LPCMPBIAS3

Definition at line 824 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT   24

Shift value for 3V0LPATT1LPCMPBIAS3

Definition at line 823 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_MASK   0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPVCTRL3

Definition at line 816 of file efr32bg1p_devinfo.h .

#define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK   0xFFUL

Bit mask for DEVINFOREV

Definition at line 339 of file efr32bg1p_devinfo.h .

Referenced by SYSTEM_GetDevinfoRev() .