LESENSE_TypeDef Struct ReferenceDevices > EFM32WG_LESENSE

Definition at line 47 of file efm32wg_lesense.h .

Data Fields

__IOM uint32_t ALTEXCONF
__IOM uint32_t BIASCTRL
LESENSE_BUF_TypeDef BUF [16U]
__IM uint32_t BUFDATA
LESENSE_CH_TypeDef CH [16U]
__IOM uint32_t CHEN
__IOM uint32_t CMD
__IOM uint32_t CTRL
__IM uint32_t CURCH
__IOM uint32_t DECCTRL
__IOM uint32_t DECSTATE
__IOM uint32_t IDLECONF
__IOM uint32_t IEN
__IM uint32_t IF
__IOM uint32_t IFC
__IOM uint32_t IFS
__IOM uint32_t PERCTRL
__IOM uint32_t POWERDOWN
__IM uint32_t PTR
uint32_t RESERVED0 [105U]
__IOM uint32_t ROUTE
__IM uint32_t SCANRES
__IOM uint32_t SENSORSTATE
LESENSE_ST_TypeDef ST [16U]
__IM uint32_t STATUS
__IM uint32_t SYNCBUSY
__IOM uint32_t TIMCTRL

Field Documentation

__IOM uint32_t LESENSE_TypeDef::ALTEXCONF

Alternative excite pin configuration

Definition at line 63 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::BIASCTRL

Bias Control Register

Definition at line 52 of file efm32wg_lesense.h .

LESENSE_BUF_TypeDef LESENSE_TypeDef::BUF[16U]

Scanresult

Definition at line 75 of file efm32wg_lesense.h .

__IM uint32_t LESENSE_TypeDef::BUFDATA

Result buffer data register

Definition at line 58 of file efm32wg_lesense.h .

LESENSE_CH_TypeDef LESENSE_TypeDef::CH[16U]

Scanconfig

Definition at line 77 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::CHEN

Channel enable Register

Definition at line 54 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::CMD

Command Register

Definition at line 53 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::CTRL

Control Register

Definition at line 48 of file efm32wg_lesense.h .

__IM uint32_t LESENSE_TypeDef::CURCH

Current channel index

Definition at line 59 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::DECCTRL

Decoder control Register

Definition at line 51 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::DECSTATE

Current decoder state

Definition at line 60 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::IDLECONF

GPIO Idle phase configuration

Definition at line 62 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::IEN

Interrupt Enable Register

Definition at line 67 of file efm32wg_lesense.h .

__IM uint32_t LESENSE_TypeDef::IF

Interrupt Flag Register

Definition at line 64 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::IFC

Interrupt Flag Clear Register

Definition at line 65 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::IFS

Interrupt Flag Set Register

Definition at line 66 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::PERCTRL

Peripheral Control Register

Definition at line 50 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::POWERDOWN

LESENSE RAM power-down register

Definition at line 70 of file efm32wg_lesense.h .

__IM uint32_t LESENSE_TypeDef::PTR

Result buffer pointers

Definition at line 57 of file efm32wg_lesense.h .

uint32_t LESENSE_TypeDef::RESERVED0[105U]

Reserved registers

Definition at line 72 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::ROUTE

I/O Routing Register

Definition at line 69 of file efm32wg_lesense.h .

__IM uint32_t LESENSE_TypeDef::SCANRES

Scan result register

Definition at line 55 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::SENSORSTATE

Decoder input register

Definition at line 61 of file efm32wg_lesense.h .

LESENSE_ST_TypeDef LESENSE_TypeDef::ST[16U]

Decoding states

Definition at line 73 of file efm32wg_lesense.h .

__IM uint32_t LESENSE_TypeDef::STATUS

Status Register

Definition at line 56 of file efm32wg_lesense.h .

__IM uint32_t LESENSE_TypeDef::SYNCBUSY

Synchronization Busy Register

Definition at line 68 of file efm32wg_lesense.h .

__IOM uint32_t LESENSE_TypeDef::TIMCTRL

Timing Control Register

Definition at line 49 of file efm32wg_lesense.h .

The documentation for this struct was generated from the following file:
  • C:/repos/super_h1/platform/Device/SiliconLabs/EFM32WG/Include/ efm32wg_lesense.h