EFM32JG12B500F1024GL125Devices

Modules

Bit Fields
Core
Processor and Core Peripheral Section.
Part
Peripheral Declarations
Peripheral Memory Map
Peripheral Offsets
Peripheral TypeDefs
Device Specific Peripheral Register Structures.

Macros

#define CRYPTO_IRQn CRYPTO0_IRQn

Typedefs

typedef enum IRQn IRQn_Type

Enumerations

enum IRQn {
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
EMU_IRQn = 0,
WDOG0_IRQn = 2,
WDOG1_IRQn = 3,
LDMA_IRQn = 9,
GPIO_EVEN_IRQn = 10,
TIMER0_IRQn = 11,
USART0_RX_IRQn = 12,
USART0_TX_IRQn = 13,
ACMP0_IRQn = 14,
ADC0_IRQn = 15,
IDAC0_IRQn = 16,
I2C0_IRQn = 17,
GPIO_ODD_IRQn = 18,
TIMER1_IRQn = 19,
USART1_RX_IRQn = 20,
USART1_TX_IRQn = 21,
LEUART0_IRQn = 22,
PCNT0_IRQn = 23,
CMU_IRQn = 24,
MSC_IRQn = 25,
CRYPTO0_IRQn = 26,
LETIMER0_IRQn = 27,
RTCC_IRQn = 30,
CRYOTIMER_IRQn = 32,
SMU_IRQn = 35,
WTIMER0_IRQn = 36,
WTIMER1_IRQn = 37,
PCNT1_IRQn = 38,
PCNT2_IRQn = 39,
USART2_RX_IRQn = 40,
USART2_TX_IRQn = 41,
I2C1_IRQn = 42,
USART3_RX_IRQn = 43,
USART3_TX_IRQn = 44,
VDAC0_IRQn = 45,
CSEN_IRQn = 46,
LESENSE_IRQn = 47,
CRYPTO1_IRQn = 48,
TRNG0_IRQn = 49
}

Macro Definition Documentation

#define CRYPTO_IRQn CRYPTO0_IRQn

Alias for CRYPTO0_IRQn

Definition at line 112 of file efm32jg12b500f1024gl125.h .

Typedef Documentation

typedef enum IRQn IRQn_Type

Interrupt Number Definition

Enumeration Type Documentation

enum IRQn

Interrupt Number Definition

Enumerator
NonMaskableInt_IRQn

2 Cortex-M3 Non Maskable Interrupt

HardFault_IRQn

3 Cortex-M3 Hard Fault Interrupt

MemoryManagement_IRQn

4 Cortex-M3 Memory Management Interrupt

BusFault_IRQn

5 Cortex-M3 Bus Fault Interrupt

UsageFault_IRQn

6 Cortex-M3 Usage Fault Interrupt

SVCall_IRQn

11 Cortex-M3 SV Call Interrupt

DebugMonitor_IRQn

12 Cortex-M3 Debug Monitor Interrupt

PendSV_IRQn

14 Cortex-M3 Pend SV Interrupt

SysTick_IRQn

15 Cortex-M3 System Tick Interrupt

EMU_IRQn

16+0 EFM32 EMU Interrupt

WDOG0_IRQn

16+2 EFM32 WDOG0 Interrupt

WDOG1_IRQn

16+3 EFM32 WDOG1 Interrupt

LDMA_IRQn

16+9 EFM32 LDMA Interrupt

GPIO_EVEN_IRQn

16+10 EFM32 GPIO_EVEN Interrupt

TIMER0_IRQn

16+11 EFM32 TIMER0 Interrupt

USART0_RX_IRQn

16+12 EFM32 USART0_RX Interrupt

USART0_TX_IRQn

16+13 EFM32 USART0_TX Interrupt

ACMP0_IRQn

16+14 EFM32 ACMP0 Interrupt

ADC0_IRQn

16+15 EFM32 ADC0 Interrupt

IDAC0_IRQn

16+16 EFM32 IDAC0 Interrupt

I2C0_IRQn

16+17 EFM32 I2C0 Interrupt

GPIO_ODD_IRQn

16+18 EFM32 GPIO_ODD Interrupt

TIMER1_IRQn

16+19 EFM32 TIMER1 Interrupt

USART1_RX_IRQn

16+20 EFM32 USART1_RX Interrupt

USART1_TX_IRQn

16+21 EFM32 USART1_TX Interrupt

LEUART0_IRQn

16+22 EFM32 LEUART0 Interrupt

PCNT0_IRQn

16+23 EFM32 PCNT0 Interrupt

CMU_IRQn

16+24 EFM32 CMU Interrupt

MSC_IRQn

16+25 EFM32 MSC Interrupt

CRYPTO0_IRQn

16+26 EFM32 CRYPTO0 Interrupt

LETIMER0_IRQn

16+27 EFM32 LETIMER0 Interrupt

RTCC_IRQn

16+30 EFM32 RTCC Interrupt

CRYOTIMER_IRQn

16+32 EFM32 CRYOTIMER Interrupt

SMU_IRQn

16+35 EFM32 SMU Interrupt

WTIMER0_IRQn

16+36 EFM32 WTIMER0 Interrupt

WTIMER1_IRQn

16+37 EFM32 WTIMER1 Interrupt

PCNT1_IRQn

16+38 EFM32 PCNT1 Interrupt

PCNT2_IRQn

16+39 EFM32 PCNT2 Interrupt

USART2_RX_IRQn

16+40 EFM32 USART2_RX Interrupt

USART2_TX_IRQn

16+41 EFM32 USART2_TX Interrupt

I2C1_IRQn

16+42 EFM32 I2C1 Interrupt

USART3_RX_IRQn

16+43 EFM32 USART3_RX Interrupt

USART3_TX_IRQn

16+44 EFM32 USART3_TX Interrupt

VDAC0_IRQn

16+45 EFM32 VDAC0 Interrupt

CSEN_IRQn

16+46 EFM32 CSEN Interrupt

LESENSE_IRQn

16+47 EFM32 LESENSE Interrupt

CRYPTO1_IRQn

16+48 EFM32 CRYPTO1 Interrupt

TRNG0_IRQn

16+49 EFM32 TRNG0 Interrupt

Definition at line 57 of file efm32jg12b500f1024gl125.h .