EFM32JG12B500F1024GL125Devices
Modules |
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Bit Fields | |
Core | |
Processor and Core Peripheral Section.
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Part | |
Peripheral Declarations | |
Peripheral Memory Map | |
Peripheral Offsets | |
Peripheral TypeDefs | |
Device Specific Peripheral Register Structures.
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Macros |
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#define | CRYPTO_IRQn CRYPTO0_IRQn |
Typedefs |
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typedef enum IRQn | IRQn_Type |
Enumerations |
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enum |
IRQn
{
NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, EMU_IRQn = 0, WDOG0_IRQn = 2, WDOG1_IRQn = 3, LDMA_IRQn = 9, GPIO_EVEN_IRQn = 10, TIMER0_IRQn = 11, USART0_RX_IRQn = 12, USART0_TX_IRQn = 13, ACMP0_IRQn = 14, ADC0_IRQn = 15, IDAC0_IRQn = 16, I2C0_IRQn = 17, GPIO_ODD_IRQn = 18, TIMER1_IRQn = 19, USART1_RX_IRQn = 20, USART1_TX_IRQn = 21, LEUART0_IRQn = 22, PCNT0_IRQn = 23, CMU_IRQn = 24, MSC_IRQn = 25, CRYPTO0_IRQn = 26, LETIMER0_IRQn = 27, RTCC_IRQn = 30, CRYOTIMER_IRQn = 32, SMU_IRQn = 35, WTIMER0_IRQn = 36, WTIMER1_IRQn = 37, PCNT1_IRQn = 38, PCNT2_IRQn = 39, USART2_RX_IRQn = 40, USART2_TX_IRQn = 41, I2C1_IRQn = 42, USART3_RX_IRQn = 43, USART3_TX_IRQn = 44, VDAC0_IRQn = 45, CSEN_IRQn = 46, LESENSE_IRQn = 47, CRYPTO1_IRQn = 48, TRNG0_IRQn = 49 } |
Macro Definition Documentation
#define CRYPTO_IRQn CRYPTO0_IRQn |
Alias for CRYPTO0_IRQn
Definition at line
112
of file
efm32jg12b500f1024gl125.h
.
Typedef Documentation
Enumeration Type Documentation
enum IRQn |
Interrupt Number Definition
Definition at line
57
of file
efm32jg12b500f1024gl125.h
.