Configures the automatic PRS LNA bypass.
Public Attributes#
Maximum time in microseconds to wait for frame detection after the LNA has been bypassed.
Threshold (without unit) from which LNA bypass is turned on.
Compensation in dB applied by RAIL to RSSI during LNA bypass.
PRS Channel used for the bypass.
PRS signal polarity for bypass.
Public Attribute Documentation#
timeout_us#
uint32_t sl_rail_prs_lna_bypass_config_t::timeout_us
Maximum time in microseconds to wait for frame detection after the LNA has been bypassed.
It must be greater than 0 to enable automatic PRS LNA bypass with sl_rail_enable_prs_lna_bypass().
threshold#
uint8_t sl_rail_prs_lna_bypass_config_t::threshold
Threshold (without unit) from which LNA bypass is turned on.
The table below shows EFR32XG25 treshold corresponding to received power level without the LNA gain.
Level dBm | FSK_1a | FSK_1b | FSK_2a | FSK_2b | FSK_3 | FSK_4a | FSK_4b | FSK_5 | OFDM1 | OFDM2 | OFDM3 | OFDM4 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
-25 | 9 | 9 | 9 | 10 | ||||||||
-20 | 7 | 7 | 7 | 8 | 8 | 7 | 8 | 11 | 12 | 12 | 12 | |
-15 | 7 | 10 | 10 | 10 | 9 | 9 | 10 | 10 | 14 | 14 | 14 | 15 |
-10 | 9 | 12 | 12 | 12 | 12 | 12 | 12 | 12 | 16 | 16 | 16 | 16 |
-5 | 11 | 14 | 14 | 14 | 16 | 16 | 14 | 16 | ||||
0 | 14 | 17 | 18 | 17 | 17 | 18 | 18 | 18 |
For example, with OFDM1 PHY, setting the threshold to 11 will turn on the bypass when the power level at EFR32XG25 input is greater than -20 dBm.
delta_rssi_db#
uint8_t sl_rail_prs_lna_bypass_config_t::delta_rssi_db
Compensation in dB applied by RAIL to RSSI during LNA bypass.
The RSSI offset set using sl_rail_set_rssi_offset() must corespond to the case with FEM LNA not bypassed. delta_rssi_db is typically the FEM LNA gain value.
prs_channel#
uint8_t sl_rail_prs_lna_bypass_config_t::prs_channel
PRS Channel used for the bypass.
PRS_GetFreeChannel() can be use to find a free channel. Then the signal can be routed to GPIO pin and port using PRS_PinOutput(). This allows logical operations with other PRS channels and so to adapt to the FEM control logic table. Any call to PRS_Combine() with sl_rail_prs_lna_bypass_config_t::prs_channel as chA must be done after the sl_rail_enable_prs_lna_bypass() call.
polarity#
bool sl_rail_prs_lna_bypass_config_t::polarity
PRS signal polarity for bypass.
With a polarity of 1, PRS signal is set to 1 for bypass and 0 for un-bypass. with a polarity of 0, PRS signal is set to 0 for bypass and 1 for un-bypass.