Host Interface (HIF)

1. Introduction

The Host Interface (HIF) is used to connect the WF200 Wi-Fi transceiver to the host system. The HIF works in a variety of modes and supports both SPI and SDIO communication protocols. This document is designed to be a useful guide to the HIF.

2. Hardware Overview

The WF200 can be connected to a host using two different buses, SPI or SDIO. The selected bus has implications on the physical connections between the Host and the WF200. The two standard connection patterns for each bus configuration are described in the WF200 Hardware Overview page.

3 Serial Communication Interfaces

The HIF supports the following communication protocols:

  • SDIO (SD mode), SDIO in 1 and 4 bit mode up to 25 MHz (default) and 50 MHz (high speed), full protocol @ version 2.0 of SDIO spec.
  • SPI, 1 bit from 1 KHz to 50 MHz.

The protocol used is given by the HIF_SEL pin state during the WF200 reset:

  • HIF_SEL pin low => SPI used
  • HIF_SEL pin high => SDIO used

To change the bus used by the HIF, the Host has to change the HIF_SEL pin state and reset the WF200.

3.1 SPI protocol

In the SPI mode, the WF200 HIF acts as an SPI slave. The SPI commands are constructed as follow:

  • Each data sequence can be bounded by a chip select (active low)
  • Each data sequence starts with a command word (16 bits). Below is the structure of those 16 bits.
Bit number 15 14 - 12 11 - 0
Function 0: Write; 1: Read Address Length

The "Address" field can take below values:

Address Addressed
"000" config register
"001" control register
"010" Input/Output queue
"011" AHB direct access channel
"100" Memory address register
"101" Shared RAM direct access channel
"110" General purpose register

The "Length" field is the number of 16 bit data words which follow the command word.

Each command for this operational mode is formatted as described below.

spi-register-communication.png
SPI access to the WF200 registers

For each command, there can be data in or data out, and data can be any multiple of 16 bit blocks.

3.1.1 SPI Byte Order

The config register has 2 word_mode bits that allow the host to program the SPI interface for different byte ordering on the line.

  • word_mode = "00" is the default behavior. All data is sent as 16-bits, most significant bit first. The bytes appear in following order:
    • For 16-bit access: B1(first), B0 (last)
    • For 32-bit access: B1(first),B0,B3,B2(last)
  • word_mode = "01" sends the data as 32-bits, most significant bit first. 16-bit accesses should not be used in this mode. The bytes appear in following order:
    • For 32-bit access: B3(first),B2,B1,B0(last)
  • word_mode = "10" sends the data as 8-bits, mode significant bit first. The bytes appear in following order:
    • For a 16-bit access: B0(first),B1(last)
    • For a 32-bit access: B0(first),B1,B2,B3(last)

The config register access is always in word_mode 0, independent of the real value of the word mode.

3.1.2 SPI Chip Select Framing

Optionally a chip select framing can be enabled as an extra security. The feature can be enabled/disabled using the bit 7 in the config register. Together with the length-field, a complete transaction is now also bound by the chip select edges. This means, the falling edge of a chip select is always followed by a command. The chip select must stay low until the last data has been transferred. For the next transfer, the chip select may first go up and then go low again (preferred for framing), or stay low and immediately proceed to the next command (more efficient if next transfer is already scheduled). An error (Error 0 flag in the config register) occurs when the chip select goes high before the last data (detected based on length) is transferred. The advantage of using the chip select framing is that the SPI can still transfer information after a length error occurred. Without the chip select framing such an error would be fatal for the interface synchronization and no SPI transfer is possible anymore (hard reset required).

3.2 SDIO Protocol

The HIF allows the Host to communicate with the WF200 using the SDIO bus. The WF200 SDIO is based on two different functions: Function 0 and Function 1.

3.2.1 Function 0

Function 0 gives access to the following SDIO registers:

In the WF200 context, the Function 0 is used after the SDIO bus standard initialization to configure the SDIO Function 1 settings (block size, bus width, interrupt...). The Function 0 uses SDIO Command 52 to communicate with the WF200. The command 52 is sent by the Host on the SDIO CMD line and expects an acknowledgement from the WF200.

Bit number 31 30 - 28 27 26 25 - 9 8 7 - 0
Function Read/Write Function Unused Unused Address Unused Data (Write only)

The command 52 is a write command if Bit 31 is equal to '1', read if '0'. The Host can write 8 bits (Bits 7 - 0) to the WF200 using one command 52.

3.2.2 Function 1

The SDIO Function 1 is meant to transfer large amounts of data between the Host and the WF200. The Function 1 relies on SDIO command 53 for communications.

Bit number 31 30 - 28 27 26 25 - 9 8 - 0
Function Read/Write Function Block Mode Address Inc Address Block Size/Buffer Size

The command 53 is a write command if Bit 31 is equal to '1', read if '0'. There are two ways to send data over the SDIO communication lines using the Function 1:

  • Stream mode
  • Block mode
3.2.2.1 SDIO Stream Mode

In the "Stream Mode", the message is sent in one chunk appended with a CRC. This mode is suitable for messages under 512 bytes. The Function 1 command has to have its Bit 27 "Block Mode" set to '0' and the size of the message set in the "Buffer Size" (Bit 0 - 8). In this mode, the SDIO data length sent is equal to the size of the API message (+ 2 bytes in case of a read command).

3.2.2.2 SDIO Block Mode

In the "Block Mode", the message is sent in several blocks of equal size each appended with its own CRC. The size of those blocks is specified by the Host to the WF200 through the Function 1 command (cf. 3.2.2 Function 1) and using the Function 0 to write in the FBR1 register (cf. 3.2.1 Function 0). The "Block Mode" can be used when a message size is too big to be sent in "Stream Mode". The size of the blocks is left to the Host choice. Keep in mind that padding is added if a message size is not a multiple of the block size.

When reading in block mode, The piggy-backed value is appended at the end of the last block after potential padding and not at the end of the message where it sits in other configurations.

3.2.2.3 Acknowledging Read Commands

When using the Function 1 and the command 53, the Host needs to acknowledge read operations in the Output queue (message received and CRC OK). To do so, another SDIO operation has to be performed. This action can be reading/writing another Input/Output queue message or reading/writing in a register. If no message are scheduled to be sent or received, it is recommended to read the config register to check if an error flag has been raised by the HIF block.

3.2.3 SDIO Input/Output Queue Buffers

To be able to handle CRC errors, each Input/Output queue message is identified with an ID. In the case of an error, the message can be resent using the same ID. Each queue has its own buffer number:

  • Input queue (e.g., Host write command), buffer number goes from 0 to 31.
  • Output queue (e.g., Host read command), buffer number goes from 1 to 4.

Once a message has been successfully sent, the ID is incremented and used in the next message. Once the ID has reached the maximum possible value, the ID is reset to its initial value (0 or 1 depending on the queue).

The ID is part of the Function 1 command "Address" field (Bit 16 - 20).

3.3 Register Access Size

Following registers can be accessed as 16-bit or 32-bit (based on length-field):

When accessing the control register as 32-bit, the highest 2 bytes (B2, B3) are put to '0' (it is 16 bits register).

The Input/Output queue (0x02) can be accessed with any multiple of 16-bit legal length.

4 WF200/Host Data Transfer

4.1 Interrupt Control

The data interrupt can be enabled/disabled using the bit 16 in the config register. When the control register is read (by a register-read or as a result of appending the info after an output queue item has been transferred, cf. piggy-back value), the interrupt source gets auto-cleared.

The hardware interrupt is issued only if the number of messages available on the WF200 side goes from 0 to 1. Additional messages do not trigger a new interruption.

4.2 Input/Output Queue Mechanisms

4.2.1 Output Queue

When the Host sees the interrupt, it reads the control register. Afterwards the interrupt is de-asserted by the HIF. At this moment the Host knows if there is an item pending in the Input/Output queue and also the size of the data to be received. The control register includes the length of the next available data expressed in half-word.

The control register can only be read safely when the interrupt is asserted. the content of the register is not guaranteed otherwise.

From this point on, the Host sends a command to request the data in the output queue. The data sent from the HIF to the Host has the control register appended to the end of each packet (called piggy-backed value), thus allowing the Host to know if there are more data pending or not. If the “next output queue item length” field of the piggy-backed value is set to 0, it means that the output queue is empty. Otherwise, the Host sends another command to request the additional data. This continues until the piggy-backed value has its “next output queue item length” field set to 0.

To take into account the piggy-backed value at the end of each message, the Host has to read a size equal to "next output queue item length field + 1". This length is expressed in half-word.

4.2.2 Input Queue

There is a limited number of input queues defined in the HIF implementation. The exact number of input queues is sent by the WF200 after a boot in the start-up indication. The Input Queue is a list of buffer space available for the Host to write to.

In addition to the input queue number, the start-up indication contains the maximum size of each buffer. The Host can prefer to write less data than defined here, which is allowed. When the host tries to write more data than defined, an error is encountered. (See Section 3.2.3 Catching Communication Errors).

4.2.3 Catching Communication Errors

The HIF exposes several error flags in its config register. The available flags are listed below.

Bit Error
7 Error 7 (SDIO only, 1: host misses CRC error, 0: no error)
6 Error 6 (1: host tries to send data with no hif input queue entry programmed, 0: no error)
5 Error 5 (1: host tries to send data larger than HIF input buffer, 0: no error)
4 Error 4 (1: host tries to send data when HIF buffers overrun, 0: no error)
3 Error 3 (1: host tries to read data with no HIF output queue entry programmed, 0: no error)
2 Error 2 (1: host tries to read data less than output message length, 0: no error)
1 Error 1 (1: host tries to read data when HIF buffers underrun, 0: no error)
0 SPI: Err 0 (1: chip select Framing error, 0: no error)
SDIO: Err 0 (1: Buffer number mismatch, 0: no error)

4.3 HIF Access mode

The Host can communicate with the WF200 using two modes:

  • Direct mode, by setting the Bit 10 in the config register to '1'. This mode is only used to download the firmware in the WF200. Once done, the host has to switch to the queue mode.
  • Queue mode, by setting the Bit 10 in the config register to '0'. This mode is used to exchange data with the WF200 firmware.

The HIF defaults to operate in direct mode from reset/system start.

4.3.1 Direct mode

When using the direct mode, the Host must set the config register Bit 10 to '1'.

In this mode of operation the queue structure and mechanisms are not used. The Host initiates direct read or write access to WF200 shared RAM. This mode is used to transfer the WF200 firmware from the host to the WF200 RAM memory.

4.3.1.1 Write in Direct Mode

A write in direct mode needs to be done in several steps:

  1. Set the "Address" register to the desired location in shared RAM to start the write process
  2. Write the data in the "Shared RAM direct access channel" register ("101")

The "Address" register needs to be updated for each write operation otherwise it writes to the same address every time.

4.3.1.2 Read in Direct Mode

A read in direct mode needs to be done in several steps:

  1. Set the "Address" register to the desired location in shared RAM to start the read process
  2. Set the config register Bit 10 to '1', this puts the HIF into direct access mode
  3. Set the config register Bit 13, this initiates a pre-fetch of data from the shared RAM by the DMA engine from the start address
  4. Read the config register, if the Bit 13 is at '0', then the data pre-fetch is complete. If this is not the case, the Host has to keep pulling the bit 13 in the config register.
  5. Once data is available, send a read command on the "Shared RAM direct access channel" register ("101").

The order of step 1 and step 2 can be changed but both must be done before step 3.

4.3.2 Queue mode

When using the queue mechanisms, the Host must set the config register Bit 10 to '0'.

In this mode of operation the data which is transferred from Host to HIF and HIF to Host is always defined in queue items. These buffers form the definitions for the transfer. The direct mode memory access cannot be used and only the following registers can be accessed:

When the Host is writing data to the HIF:

  • The read/write bit is set to '0'
  • The address of the command word is "010" (e.g., Input/Output queue)

When the host is reading data from the HIF:

  • The read/write bit is set to '1'
  • The address of the command word is "010" (e.g., Input/Output queue)