|
#define
|
_DEVINFO_ADC0CAL0_GAIN1V25_MASK
0x7F00UL
|
|
#define
|
_DEVINFO_ADC0CAL0_GAIN1V25_SHIFT
8
|
|
#define
|
_DEVINFO_ADC0CAL0_GAIN2V5_MASK
0x7F000000UL
|
|
#define
|
_DEVINFO_ADC0CAL0_GAIN2V5_SHIFT
24
|
|
#define
|
_DEVINFO_ADC0CAL0_MASK
0x7FFF7FFFUL
|
|
#define
|
_DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK
0xF0UL
|
|
#define
|
_DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT
4
|
|
#define
|
_DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK
0xF00000UL
|
|
#define
|
_DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT
20
|
|
#define
|
_DEVINFO_ADC0CAL0_OFFSET1V25_MASK
0xFUL
|
|
#define
|
_DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT
0
|
|
#define
|
_DEVINFO_ADC0CAL0_OFFSET2V5_MASK
0xF0000UL
|
|
#define
|
_DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT
16
|
|
#define
|
_DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK
0x7F000000UL
|
|
#define
|
_DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT
24
|
|
#define
|
_DEVINFO_ADC0CAL1_GAINVDD_MASK
0x7F00UL
|
|
#define
|
_DEVINFO_ADC0CAL1_GAINVDD_SHIFT
8
|
|
#define
|
_DEVINFO_ADC0CAL1_MASK
0x7FFF7FFFUL
|
|
#define
|
_DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK
0xF00000UL
|
|
#define
|
_DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT
20
|
|
#define
|
_DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK
0xF0UL
|
|
#define
|
_DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT
4
|
|
#define
|
_DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK
0xF0000UL
|
|
#define
|
_DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT
16
|
|
#define
|
_DEVINFO_ADC0CAL1_OFFSETVDD_MASK
0xFUL
|
|
#define
|
_DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT
0
|
|
#define
|
_DEVINFO_ADC0CAL2_MASK
0x000000FFUL
|
|
#define
|
_DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK
0xF0UL
|
|
#define
|
_DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT
4
|
|
#define
|
_DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK
0xFUL
|
|
#define
|
_DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT
0
|
|
#define
|
_DEVINFO_ADC0CAL3_MASK
0x0000FFF0UL
|
|
#define
|
_DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK
0xFFF0UL
|
|
#define
|
_DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT
4
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_CAL_CRC_MASK
0xFFFFUL
|
|
#define
|
_DEVINFO_CAL_CRC_SHIFT
0
|
|
#define
|
_DEVINFO_CAL_MASK
0x00FFFFFFUL
|
|
#define
|
_DEVINFO_CAL_TEMP_MASK
0xFF0000UL
|
|
#define
|
_DEVINFO_CAL_TEMP_SHIFT
16
|
|
#define
|
_DEVINFO_CSENGAINCAL_GAINCAL_MASK
0xFFUL
|
|
#define
|
_DEVINFO_CSENGAINCAL_GAINCAL_SHIFT
0
|
|
#define
|
_DEVINFO_CSENGAINCAL_MASK
0x000000FFUL
|
|
#define
|
_DEVINFO_CUSTOMINFO_MASK
0xFFFF0000UL
|
|
#define
|
_DEVINFO_CUSTOMINFO_PARTNO_MASK
0xFFFF0000UL
|
|
#define
|
_DEVINFO_CUSTOMINFO_PARTNO_SHIFT
16
|
|
#define
|
_DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK
0xFFUL
|
|
#define
|
_DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT
0
|
|
#define
|
_DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK
0xFF00UL
|
|
#define
|
_DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT
8
|
|
#define
|
_DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK
0xFF0000UL
|
|
#define
|
_DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT
16
|
|
#define
|
_DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK
0xFF000000UL
|
|
#define
|
_DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT
24
|
|
#define
|
_DEVINFO_DCDCLNVCTRL0_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK
0xFFUL
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT
0
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK
0xFF00UL
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT
8
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL0_MASK
0x0000FFFFUL
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK
0xFFUL
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT
0
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK
0xFF00UL
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT
8
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK
0xFF0000UL
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT
16
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK
0xFF000000UL
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT
24
|
|
#define
|
_DEVINFO_DCDCLPCMPHYSSEL1_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK
0xFFUL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT
0
|
|
#define
|
_DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK
0xFF0000UL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT
16
|
|
#define
|
_DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK
0xFF00UL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT
8
|
|
#define
|
_DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK
0xFF000000UL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT
24
|
|
#define
|
_DEVINFO_DCDCLPVCTRL0_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK
0xFFUL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT
0
|
|
#define
|
_DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK
0xFF0000UL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT
16
|
|
#define
|
_DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK
0xFF00UL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT
8
|
|
#define
|
_DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK
0xFF000000UL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT
24
|
|
#define
|
_DEVINFO_DCDCLPVCTRL1_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK
0xFFUL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT
0
|
|
#define
|
_DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK
0xFF0000UL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT
16
|
|
#define
|
_DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK
0xFF00UL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT
8
|
|
#define
|
_DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK
0xFF000000UL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT
24
|
|
#define
|
_DEVINFO_DCDCLPVCTRL2_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK
0xFFUL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT
0
|
|
#define
|
_DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK
0xFF0000UL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT
16
|
|
#define
|
_DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK
0xFF00UL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT
8
|
|
#define
|
_DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK
0xFF000000UL
|
|
#define
|
_DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT
24
|
|
#define
|
_DEVINFO_DCDCLPVCTRL3_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_DEVINFOREV_DEVINFOREV_MASK
0xFFUL
|
|
#define
|
_DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT
0
|
|
#define
|
_DEVINFO_DEVINFOREV_MASK
0x000000FFUL
|
|
#define
|
_DEVINFO_EMUTEMP_EMUTEMPROOM_MASK
0xFFUL
|
|
#define
|
_DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT
0
|
|
#define
|
_DEVINFO_EMUTEMP_MASK
0x000000FFUL
|
|
#define
|
_DEVINFO_EUI48H_MASK
0x0000FFFFUL
|
|
#define
|
_DEVINFO_EUI48H_OUI48H_MASK
0xFFFFUL
|
|
#define
|
_DEVINFO_EUI48H_OUI48H_SHIFT
0
|
|
#define
|
_DEVINFO_EUI48L_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_EUI48L_OUI48L_MASK
0xFF000000UL
|
|
#define
|
_DEVINFO_EUI48L_OUI48L_SHIFT
24
|
|
#define
|
_DEVINFO_EUI48L_UNIQUEID_MASK
0xFFFFFFUL
|
|
#define
|
_DEVINFO_EUI48L_UNIQUEID_SHIFT
0
|
|
#define
|
_DEVINFO_HFRCOCAL0_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL0_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_HFRCOCAL0_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_HFRCOCAL0_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_HFRCOCAL0_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_HFRCOCAL0_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_HFRCOCAL0_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL0_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_HFRCOCAL0_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL0_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL0_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_HFRCOCAL0_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL0_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_HFRCOCAL10_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL10_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_HFRCOCAL10_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_HFRCOCAL10_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_HFRCOCAL10_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_HFRCOCAL10_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_HFRCOCAL10_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL10_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_HFRCOCAL10_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL10_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL10_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_HFRCOCAL10_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL10_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_HFRCOCAL11_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL11_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_HFRCOCAL11_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_HFRCOCAL11_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_HFRCOCAL11_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_HFRCOCAL11_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_HFRCOCAL11_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL11_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_HFRCOCAL11_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL11_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL11_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_HFRCOCAL11_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL11_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_HFRCOCAL12_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL12_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_HFRCOCAL12_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_HFRCOCAL12_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_HFRCOCAL12_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_HFRCOCAL12_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_HFRCOCAL12_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL12_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_HFRCOCAL12_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL12_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL12_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_HFRCOCAL12_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL12_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_HFRCOCAL3_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL3_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_HFRCOCAL3_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_HFRCOCAL3_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_HFRCOCAL3_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_HFRCOCAL3_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_HFRCOCAL3_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL3_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_HFRCOCAL3_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL3_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL3_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_HFRCOCAL3_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL3_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_HFRCOCAL6_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL6_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_HFRCOCAL6_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_HFRCOCAL6_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_HFRCOCAL6_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_HFRCOCAL6_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_HFRCOCAL6_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL6_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_HFRCOCAL6_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL6_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL6_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_HFRCOCAL6_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL6_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_HFRCOCAL7_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL7_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_HFRCOCAL7_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_HFRCOCAL7_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_HFRCOCAL7_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_HFRCOCAL7_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_HFRCOCAL7_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL7_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_HFRCOCAL7_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL7_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL7_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_HFRCOCAL7_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL7_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_HFRCOCAL8_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL8_CLKDIV_SHIFT
25
|
|
#define
|
_DEVINFO_HFRCOCAL8_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT
21
|
|
#define
|
_DEVINFO_HFRCOCAL8_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_DEVINFO_HFRCOCAL8_FINETUNING_SHIFT
8
|
|
#define
|
_DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT
27
|
|
#define
|
_DEVINFO_HFRCOCAL8_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT
16
|
|
#define
|
_DEVINFO_HFRCOCAL8_LDOHP_MASK
0x1000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL8_LDOHP_SHIFT
24
|
|
#define
|
_DEVINFO_HFRCOCAL8_MASK
0xFFFF3F7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL8_TUNING_MASK
0x7FUL
|
|
#define
|
_DEVINFO_HFRCOCAL8_TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_HFRCOCAL8_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_HFRCOCAL8_VREFTC_SHIFT
28
|
|
#define
|
_DEVINFO_IDAC0CAL0_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK
0xFFUL
|
|
#define
|
_DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK
0xFF00UL
|
|
#define
|
_DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT
8
|
|
#define
|
_DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK
0xFF0000UL
|
|
#define
|
_DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT
16
|
|
#define
|
_DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK
0xFF000000UL
|
|
#define
|
_DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT
24
|
|
#define
|
_DEVINFO_IDAC0CAL1_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK
0xFFUL
|
|
#define
|
_DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT
0
|
|
#define
|
_DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK
0xFF00UL
|
|
#define
|
_DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT
8
|
|
#define
|
_DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK
0xFF0000UL
|
|
#define
|
_DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT
16
|
|
#define
|
_DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK
0xFF000000UL
|
|
#define
|
_DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT
24
|
|
#define
|
_DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK
0xFF000000UL
|
|
#define
|
_DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT
24
|
|
#define
|
_DEVINFO_MEMINFO_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_MEMINFO_PINCOUNT_MASK
0xFF0000UL
|
|
#define
|
_DEVINFO_MEMINFO_PINCOUNT_SHIFT
16
|
|
#define
|
_DEVINFO_MEMINFO_PKGTYPE_BGA
0x0000004CUL
|
|
#define
|
_DEVINFO_MEMINFO_PKGTYPE_MASK
0xFF00UL
|
|
#define
|
_DEVINFO_MEMINFO_PKGTYPE_QFN
0x0000004DUL
|
|
#define
|
_DEVINFO_MEMINFO_PKGTYPE_QFP
0x00000051UL
|
|
#define
|
_DEVINFO_MEMINFO_PKGTYPE_SHIFT
8
|
|
#define
|
_DEVINFO_MEMINFO_PKGTYPE_WLCSP
0x0000004AUL
|
|
#define
|
_DEVINFO_MEMINFO_TEMPGRADE_MASK
0xFFUL
|
|
#define
|
_DEVINFO_MEMINFO_TEMPGRADE_N0TO70
0x00000003UL
|
|
#define
|
_DEVINFO_MEMINFO_TEMPGRADE_N40TO105
0x00000002UL
|
|
#define
|
_DEVINFO_MEMINFO_TEMPGRADE_N40TO125
0x00000001UL
|
|
#define
|
_DEVINFO_MEMINFO_TEMPGRADE_N40TO85
0x00000000UL
|
|
#define
|
_DEVINFO_MEMINFO_TEMPGRADE_SHIFT
0
|
|
#define
|
_DEVINFO_MSIZE_FLASH_MASK
0xFFFFUL
|
|
#define
|
_DEVINFO_MSIZE_FLASH_SHIFT
0
|
|
#define
|
_DEVINFO_MSIZE_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_MSIZE_SRAM_MASK
0xFFFF0000UL
|
|
#define
|
_DEVINFO_MSIZE_SRAM_SHIFT
16
|
|
#define
|
_DEVINFO_OPA0CAL0_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA0CAL0_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA0CAL0_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA0CAL0_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA0CAL0_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA0CAL0_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA0CAL0_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA0CAL0_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA0CAL0_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA0CAL0_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA0CAL0_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA0CAL0_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA0CAL0_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA0CAL0_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA0CAL0_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA0CAL1_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA0CAL1_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA0CAL1_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA0CAL1_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA0CAL1_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA0CAL1_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA0CAL1_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA0CAL1_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA0CAL1_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA0CAL1_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA0CAL1_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA0CAL1_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA0CAL1_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA0CAL1_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA0CAL1_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA0CAL2_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA0CAL2_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA0CAL2_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA0CAL2_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA0CAL2_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA0CAL2_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA0CAL2_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA0CAL2_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA0CAL2_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA0CAL2_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA0CAL2_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA0CAL2_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA0CAL2_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA0CAL2_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA0CAL2_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA0CAL3_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA0CAL3_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA0CAL3_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA0CAL3_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA0CAL3_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA0CAL3_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA0CAL3_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA0CAL3_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA0CAL3_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA0CAL3_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA0CAL3_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA0CAL3_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA0CAL3_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA0CAL3_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA0CAL3_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA0CAL4_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA0CAL4_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA0CAL4_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA0CAL4_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA0CAL4_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA0CAL4_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA0CAL4_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA0CAL4_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA0CAL4_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA0CAL4_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA0CAL4_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA0CAL4_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA0CAL4_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA0CAL4_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA0CAL4_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA0CAL5_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA0CAL5_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA0CAL5_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA0CAL5_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA0CAL5_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA0CAL5_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA0CAL5_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA0CAL5_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA0CAL5_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA0CAL5_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA0CAL5_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA0CAL5_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA0CAL5_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA0CAL5_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA0CAL5_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA0CAL6_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA0CAL6_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA0CAL6_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA0CAL6_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA0CAL6_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA0CAL6_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA0CAL6_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA0CAL6_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA0CAL6_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA0CAL6_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA0CAL6_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA0CAL6_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA0CAL6_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA0CAL6_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA0CAL6_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA0CAL7_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA0CAL7_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA0CAL7_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA0CAL7_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA0CAL7_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA0CAL7_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA0CAL7_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA0CAL7_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA0CAL7_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA0CAL7_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA0CAL7_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA0CAL7_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA0CAL7_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA0CAL7_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA0CAL7_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA1CAL0_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA1CAL0_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA1CAL0_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA1CAL0_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA1CAL0_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA1CAL0_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA1CAL0_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA1CAL0_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA1CAL0_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA1CAL0_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA1CAL0_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA1CAL0_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA1CAL0_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA1CAL0_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA1CAL0_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA1CAL1_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA1CAL1_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA1CAL1_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA1CAL1_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA1CAL1_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA1CAL1_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA1CAL1_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA1CAL1_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA1CAL1_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA1CAL1_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA1CAL1_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA1CAL1_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA1CAL1_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA1CAL1_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA1CAL1_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA1CAL2_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA1CAL2_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA1CAL2_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA1CAL2_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA1CAL2_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA1CAL2_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA1CAL2_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA1CAL2_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA1CAL2_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA1CAL2_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA1CAL2_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA1CAL2_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA1CAL2_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA1CAL2_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA1CAL2_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA1CAL3_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA1CAL3_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA1CAL3_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA1CAL3_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA1CAL3_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA1CAL3_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA1CAL3_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA1CAL3_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA1CAL3_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA1CAL3_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA1CAL3_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA1CAL3_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA1CAL3_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA1CAL3_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA1CAL3_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA1CAL4_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA1CAL4_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA1CAL4_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA1CAL4_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA1CAL4_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA1CAL4_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA1CAL4_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA1CAL4_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA1CAL4_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA1CAL4_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA1CAL4_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA1CAL4_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA1CAL4_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA1CAL4_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA1CAL4_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA1CAL5_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA1CAL5_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA1CAL5_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA1CAL5_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA1CAL5_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA1CAL5_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA1CAL5_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA1CAL5_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA1CAL5_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA1CAL5_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA1CAL5_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA1CAL5_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA1CAL5_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA1CAL5_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA1CAL5_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA1CAL6_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA1CAL6_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA1CAL6_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA1CAL6_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA1CAL6_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA1CAL6_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA1CAL6_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA1CAL6_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA1CAL6_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA1CAL6_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA1CAL6_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA1CAL6_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA1CAL6_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA1CAL6_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA1CAL6_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA1CAL7_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA1CAL7_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA1CAL7_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA1CAL7_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA1CAL7_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA1CAL7_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA1CAL7_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA1CAL7_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA1CAL7_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA1CAL7_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA1CAL7_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA1CAL7_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA1CAL7_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA1CAL7_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA1CAL7_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA2CAL0_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA2CAL0_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA2CAL0_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA2CAL0_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA2CAL0_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA2CAL0_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA2CAL0_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA2CAL0_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA2CAL0_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA2CAL0_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA2CAL0_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA2CAL0_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA2CAL0_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA2CAL0_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA2CAL0_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA2CAL1_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA2CAL1_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA2CAL1_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA2CAL1_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA2CAL1_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA2CAL1_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA2CAL1_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA2CAL1_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA2CAL1_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA2CAL1_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA2CAL1_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA2CAL1_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA2CAL1_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA2CAL1_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA2CAL1_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA2CAL2_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA2CAL2_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA2CAL2_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA2CAL2_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA2CAL2_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA2CAL2_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA2CAL2_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA2CAL2_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA2CAL2_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA2CAL2_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA2CAL2_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA2CAL2_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA2CAL2_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA2CAL2_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA2CAL2_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA2CAL3_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA2CAL3_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA2CAL3_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA2CAL3_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA2CAL3_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA2CAL3_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA2CAL3_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA2CAL3_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA2CAL3_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA2CAL3_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA2CAL3_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA2CAL3_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA2CAL3_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA2CAL3_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA2CAL3_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA2CAL4_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA2CAL4_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA2CAL4_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA2CAL4_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA2CAL4_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA2CAL4_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA2CAL4_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA2CAL4_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA2CAL4_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA2CAL4_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA2CAL4_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA2CAL4_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA2CAL4_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA2CAL4_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA2CAL4_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA2CAL5_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA2CAL5_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA2CAL5_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA2CAL5_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA2CAL5_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA2CAL5_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA2CAL5_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA2CAL5_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA2CAL5_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA2CAL5_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA2CAL5_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA2CAL5_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA2CAL5_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA2CAL5_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA2CAL5_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA2CAL6_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA2CAL6_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA2CAL6_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA2CAL6_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA2CAL6_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA2CAL6_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA2CAL6_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA2CAL6_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA2CAL6_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA2CAL6_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA2CAL6_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA2CAL6_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA2CAL6_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA2CAL6_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA2CAL6_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_OPA2CAL7_CM1_MASK
0xFUL
|
|
#define
|
_DEVINFO_OPA2CAL7_CM1_SHIFT
0
|
|
#define
|
_DEVINFO_OPA2CAL7_CM2_MASK
0x1E0UL
|
|
#define
|
_DEVINFO_OPA2CAL7_CM2_SHIFT
5
|
|
#define
|
_DEVINFO_OPA2CAL7_CM3_MASK
0xC00UL
|
|
#define
|
_DEVINFO_OPA2CAL7_CM3_SHIFT
10
|
|
#define
|
_DEVINFO_OPA2CAL7_GM3_MASK
0x60000UL
|
|
#define
|
_DEVINFO_OPA2CAL7_GM3_SHIFT
17
|
|
#define
|
_DEVINFO_OPA2CAL7_GM_MASK
0xE000UL
|
|
#define
|
_DEVINFO_OPA2CAL7_GM_SHIFT
13
|
|
#define
|
_DEVINFO_OPA2CAL7_MASK
0x7DF6EDEFUL
|
|
#define
|
_DEVINFO_OPA2CAL7_OFFSETN_MASK
0x7C000000UL
|
|
#define
|
_DEVINFO_OPA2CAL7_OFFSETN_SHIFT
26
|
|
#define
|
_DEVINFO_OPA2CAL7_OFFSETP_MASK
0x1F00000UL
|
|
#define
|
_DEVINFO_OPA2CAL7_OFFSETP_SHIFT
20
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFM32G
0x00000047UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFM32GG
0x00000048UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B
0x00000064UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFM32HG
0x0000004DUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B
0x00000057UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B
0x00000053UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFM32LG
0x0000004AUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B
0x00000055UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B
0x00000051UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFM32TG
0x00000049UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B
0x00000067UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFM32WG
0x0000004BUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG
0x0000004CUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B
0x00000020UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P
0x0000001FUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V
0x00000021UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B
0x0000002CUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P
0x0000002BUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V
0x0000002DUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B
0x00000038UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P
0x00000037UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V
0x00000039UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B
0x00000014UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P
0x00000013UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V
0x00000015UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B
0x00000026UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P
0x00000025UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V
0x00000027UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B
0x00000032UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P
0x00000031UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V
0x00000033UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B
0x0000003EUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P
0x0000003DUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V
0x0000003FUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B
0x0000001AUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P
0x00000019UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V
0x0000001BUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B
0x0000001DUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P
0x0000001CUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V
0x0000001EUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B
0x00000029UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P
0x00000028UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V
0x0000002AUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B
0x00000035UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P
0x00000034UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V
0x00000036UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B
0x00000011UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P
0x00000010UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V
0x00000012UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EZR32HG
0x0000007AUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EZR32LG
0x00000078UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_EZR32WG
0x00000079UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_G
0x00000047UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_GG
0x00000048UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_HG
0x0000004DUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_LG
0x0000004AUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_MASK
0xFF0000UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_SHIFT
16
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_TG
0x00000049UL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_WG
0x0000004BUL
|
|
#define
|
_DEVINFO_PART_DEVICE_FAMILY_ZG
0x0000004CUL
|
|
#define
|
_DEVINFO_PART_DEVICE_NUMBER_MASK
0xFFFFUL
|
|
#define
|
_DEVINFO_PART_DEVICE_NUMBER_SHIFT
0
|
|
#define
|
_DEVINFO_PART_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_PART_PROD_REV_MASK
0xFF000000UL
|
|
#define
|
_DEVINFO_PART_PROD_REV_SHIFT
24
|
|
#define
|
_DEVINFO_UNIQUEH_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_UNIQUEH_UNIQUEH_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_UNIQUEH_UNIQUEH_SHIFT
0
|
|
#define
|
_DEVINFO_UNIQUEL_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_UNIQUEL_UNIQUEL_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_UNIQUEL_UNIQUEL_SHIFT
0
|
|
#define
|
_DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK
0x3F000UL
|
|
#define
|
_DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT
12
|
|
#define
|
_DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK
0x3FUL
|
|
#define
|
_DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT
0
|
|
#define
|
_DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK
0xFC0000UL
|
|
#define
|
_DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT
18
|
|
#define
|
_DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK
0xFC0UL
|
|
#define
|
_DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT
6
|
|
#define
|
_DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK
0x3F000000UL
|
|
#define
|
_DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT
24
|
|
#define
|
_DEVINFO_VDAC0ALTCAL_MASK
0x3FFFFFFFUL
|
|
#define
|
_DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK
0xF0UL
|
|
#define
|
_DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT
4
|
|
#define
|
_DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK
0xF00UL
|
|
#define
|
_DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT
8
|
|
#define
|
_DEVINFO_VDAC0CH1CAL_MASK
0x00000FF7UL
|
|
#define
|
_DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK
0x7UL
|
|
#define
|
_DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT
0
|
|
#define
|
_DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK
0x3F000UL
|
|
#define
|
_DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT
12
|
|
#define
|
_DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK
0x3FUL
|
|
#define
|
_DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT
0
|
|
#define
|
_DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK
0xFC0000UL
|
|
#define
|
_DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT
18
|
|
#define
|
_DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK
0xFC0UL
|
|
#define
|
_DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT
6
|
|
#define
|
_DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK
0x3F000000UL
|
|
#define
|
_DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT
24
|
|
#define
|
_DEVINFO_VDAC0MAINCAL_MASK
0x3FFFFFFFUL
|
|
#define
|
_DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK
0xF00000UL
|
|
#define
|
_DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT
20
|
|
#define
|
_DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK
0xF0000UL
|
|
#define
|
_DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT
16
|
|
#define
|
_DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT
28
|
|
#define
|
_DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK
0xF000000UL
|
|
#define
|
_DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT
24
|
|
#define
|
_DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK
0xF0UL
|
|
#define
|
_DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT
4
|
|
#define
|
_DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK
0xFUL
|
|
#define
|
_DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT
0
|
|
#define
|
_DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK
0xF000UL
|
|
#define
|
_DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT
12
|
|
#define
|
_DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK
0xF00UL
|
|
#define
|
_DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT
8
|
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#define
|
_DEVINFO_VMONCAL0_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK
0xF0UL
|
|
#define
|
_DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT
4
|
|
#define
|
_DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK
0xFUL
|
|
#define
|
_DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT
0
|
|
#define
|
_DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK
0xF000UL
|
|
#define
|
_DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT
12
|
|
#define
|
_DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK
0xF00UL
|
|
#define
|
_DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT
8
|
|
#define
|
_DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK
0xF00000UL
|
|
#define
|
_DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT
20
|
|
#define
|
_DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK
0xF0000UL
|
|
#define
|
_DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT
16
|
|
#define
|
_DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT
28
|
|
#define
|
_DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK
0xF000000UL
|
|
#define
|
_DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT
24
|
|
#define
|
_DEVINFO_VMONCAL1_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK
0xF00000UL
|
|
#define
|
_DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT
20
|
|
#define
|
_DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK
0xF0000UL
|
|
#define
|
_DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT
16
|
|
#define
|
_DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK
0xF0000000UL
|
|
#define
|
_DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT
28
|
|
#define
|
_DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK
0xF000000UL
|
|
#define
|
_DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT
24
|
|
#define
|
_DEVINFO_VMONCAL2_MASK
0xFFFFFFFFUL
|
|
#define
|
_DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK
0xF0UL
|
|
#define
|
_DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT
4
|
|
#define
|
_DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK
0xFUL
|
|
#define
|
_DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT
0
|
|
#define
|
_DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK
0xF000UL
|
|
#define
|
_DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT
12
|
|
#define
|
_DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK
0xF00UL
|
|
#define
|
_DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT
8
|
|
#define
|
DEVINFO_MEMINFO_PKGTYPE_BGA
(
_DEVINFO_MEMINFO_PKGTYPE_BGA
<< 8)
|
|
#define
|
DEVINFO_MEMINFO_PKGTYPE_QFN
(
_DEVINFO_MEMINFO_PKGTYPE_QFN
<< 8)
|
|
#define
|
DEVINFO_MEMINFO_PKGTYPE_QFP
(
_DEVINFO_MEMINFO_PKGTYPE_QFP
<< 8)
|
|
#define
|
DEVINFO_MEMINFO_PKGTYPE_WLCSP
(
_DEVINFO_MEMINFO_PKGTYPE_WLCSP
<< 8)
|
|
#define
|
DEVINFO_MEMINFO_TEMPGRADE_N0TO70
(
_DEVINFO_MEMINFO_TEMPGRADE_N0TO70
<< 0)
|
|
#define
|
DEVINFO_MEMINFO_TEMPGRADE_N40TO105
(
_DEVINFO_MEMINFO_TEMPGRADE_N40TO105
<< 0)
|
|
#define
|
DEVINFO_MEMINFO_TEMPGRADE_N40TO125
(
_DEVINFO_MEMINFO_TEMPGRADE_N40TO125
<< 0)
|
|
#define
|
DEVINFO_MEMINFO_TEMPGRADE_N40TO85
(
_DEVINFO_MEMINFO_TEMPGRADE_N40TO85
<< 0)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFM32G
(
_DEVINFO_PART_DEVICE_FAMILY_EFM32G
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFM32GG
(
_DEVINFO_PART_DEVICE_FAMILY_EFM32GG
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B
(
_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFM32HG
(
_DEVINFO_PART_DEVICE_FAMILY_EFM32HG
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B
(
_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B
(
_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFM32LG
(
_DEVINFO_PART_DEVICE_FAMILY_EFM32LG
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B
(
_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B
(
_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFM32TG
(
_DEVINFO_PART_DEVICE_FAMILY_EFM32TG
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B
(
_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFM32WG
(
_DEVINFO_PART_DEVICE_FAMILY_EFM32WG
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFM32ZG
(
_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B
<< 16)
|
|
#define
|
DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P
(
_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P
<< 16)
|
|
|