CoreDevices > EFM32JG12B500F1024GL125
Detailed Description
Processor and Core Peripheral Section.
Macros |
|
| #define | __MPU_PRESENT 1 |
| #define | __NVIC_PRIO_BITS 3 |
| #define | __Vendor_SysTickConfig 0 |
| #define | __VTOR_PRESENT 1 |
Macro Definition Documentation
| #define __MPU_PRESENT 1 |
Presence of MPU
Definition at line
120
of file
efm32jg12b500f1024gl125.h
.
| #define __NVIC_PRIO_BITS 3 |
NVIC interrupt priority bits
Definition at line
122
of file
efm32jg12b500f1024gl125.h
.
Referenced by CORE_AtomicDisableIrq() , CORE_EnterAtomic() , CORE_IrqIsBlocked() , CORE_IrqIsDisabled() , CORE_YieldAtomic() , and LDMA_Init() .
| #define __Vendor_SysTickConfig 0 |
Is 1 if different SysTick counter is used
Definition at line
123
of file
efm32jg12b500f1024gl125.h
.
| #define __VTOR_PRESENT 1 |
Presence of VTOR register in SCB
Definition at line
121
of file
efm32jg12b500f1024gl125.h
.