CoreDevices > EFM32JG12B500F1024GL125

Detailed Description

Processor and Core Peripheral Section.

Macros

#define __MPU_PRESENT   1U
 
#define __NVIC_PRIO_BITS   3U
 
#define __Vendor_SysTickConfig   0U
 
#define __VTOR_PRESENT   1U
 

Macro Definition Documentation

#define __MPU_PRESENT   1U

Presence of MPU

Definition at line 119 of file efm32jg12b500f1024gl125.h.

#define __NVIC_PRIO_BITS   3U

NVIC interrupt priority bits

Definition at line 121 of file efm32jg12b500f1024gl125.h.

Referenced by CORE_AtomicDisableIrq(), CORE_EnterAtomic(), CORE_IrqIsBlocked(), CORE_IrqIsDisabled(), CORE_YieldAtomic(), and LDMA_Init().

#define __Vendor_SysTickConfig   0U

Is 1 if different SysTick counter is used

Definition at line 122 of file efm32jg12b500f1024gl125.h.

#define __VTOR_PRESENT   1U

Presence of VTOR register in SCB

Definition at line 120 of file efm32jg12b500f1024gl125.h.