Detailed Description

Security Management Unit (SMU) Peripheral API.

SMU forms the control and status/reporting component of bus-level security in EFM32/EFR32 devices.

Peripheral-level protection is provided via the peripheral protection unit (PPU). PPU provides hardware access barrier to any peripheral that is configured to be protected. When an attempt is made to access a peripheral without the required privilege/security level, PPU detects the fault and intercepts the access. No write or read of the peripheral register space occurs, and an all-zero value is returned if the access is a read.

       
        // SMU is always clocked, so no call to CMU_ClockEnable() is necessary
       
        // Initialize SMU to prevent access to CMU, EMU, SMU and GPIO
       
        SMU_Init_TypeDef
       
       init =
       
        SMU_INIT_DEFAULT
       
       ;
      
       init.ppu.
       
        access
       
       .
       
        privilegedCMU
       
       =
       
        true
       
       ;
      
       init.ppu.
       
        access
       
       .
       
        privilegedEMU
       
       =
       
        true
       
       ;
      
       init.ppu.
       
        access
       
       .
       
        privilegedSMU
       
       =
       
        true
       
       ;
      
       init.ppu.
       
        access
       
       .
       
        privilegedGPIO
       
       =
       
        true
       
       ;
      
        SMU_Init
       
       (&init);

Data Structures
struct	SMU_Init_TypeDef

struct	SMU_PrivilegedAccess_TypeDef

Macros
#define	SMU_INIT_DEFAULT

Enumerations
enum	SMU_Peripheral_TypeDef { smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, smuPeripheralHFXO = _SMU_PPUPATD0_HFXO0_SHIFT, smuPeripheralHFRCO0 = _SMU_PPUPATD0_HFRCO0_SHIFT, smuPeripheralFSRCO = _SMU_PPUPATD0_FSRCO_SHIFT, smuPeripheralDPLL0 = _SMU_PPUPATD0_DPLL0_SHIFT, smuPeripheralLFXO = _SMU_PPUPATD0_LFXO_SHIFT, smuPeripheralLFRCO = _SMU_PPUPATD0_LFRCO_SHIFT, smuPeripheralULFRCO = _SMU_PPUPATD0_ULFRCO_SHIFT, smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, smuPeripheralICACHE0 = _SMU_PPUPATD0_ICACHE0_SHIFT, smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, smuPeripheralLDMAXBAR = _SMU_PPUPATD0_LDMAXBAR_SHIFT, smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, smuPeripheralTIMER2 = _SMU_PPUPATD0_TIMER2_SHIFT, smuPeripheralTIMER3 = _SMU_PPUPATD0_TIMER3_SHIFT, smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, smuPeripheralBURTC = _SMU_PPUPATD0_BURTC_SHIFT, smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, smuPeripheralCHIPTESTCTRL = _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT, smuPeripheralSYSCFG = _SMU_PPUPATD0_SYSCFG_SHIFT, smuPeripheralBURAM = _SMU_PPUPATD0_BURAM_SHIFT, smuPeripheralIFADCDEBUG = _SMU_PPUPATD0_IFADCDEBUG_SHIFT, smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, smuPeripheralDCDC = 32 + _SMU_PPUPATD1_DCDC_SHIFT, smuPeripheralPDM = 32 + _SMU_PPUPATD1_PDM_SHIFT, smuPeripheralRFSENSE = 32 + _SMU_PPUPATD1_RFSENSE_SHIFT, smuPeripheralLETIMER0 = 32 + _SMU_PPUPATD1_LETIMER0_SHIFT, smuPeripheralIADC0 = 32 + _SMU_PPUPATD1_IADC0_SHIFT, smuPeripheralI2C0 = 32 + _SMU_PPUPATD1_I2C0_SHIFT, smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, smuPeripheralAMUXCP0 = 32 + _SMU_PPUPATD1_AMUXCP0_SHIFT, smuPeripheralRADIOAES = 32 + _SMU_PPUPATD1_RADIOAES_SHIFT, smuPeripheralEUART0 = 32 + _SMU_PPUPATD1_EUART0_SHIFT, smuPeripheralBUFC = 32 + _SMU_PPUPATD1_BUFC_SHIFT, smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, smuPeripheralSMUCFGNS = 32 + _SMU_PPUPATD1_SMUCFGNS_SHIFT, smuPeripheralAHBRADIO = 32 + _SMU_PPUPATD1_AHBRADIO_SHIFT, smuPeripheralCRYPTOACC = 32 + _SMU_PPUPATD1_CRYPTOACC_SHIFT, smuPeripheralEnd }

Functions
__STATIC_INLINE void	SMU_EnablePPU (bool enable)
	Enable or disable PPU of SMU.

__STATIC_INLINE SMU_Peripheral_TypeDef	SMU_GetFaultingPeripheral (void)
	Get ID of the peripheral that caused an access fault.

__STATIC_INLINE void	SMU_Init (const SMU_Init_TypeDef *init)
	Initialize PPU of SMU.

__STATIC_INLINE void	SMU_IntClear (uint32_t flags)
	Clear one or more pending SMU interrupts.

__STATIC_INLINE void	SMU_IntDisable (uint32_t flags)
	Disable one or more SMU interrupts.

__STATIC_INLINE void	SMU_IntEnable (uint32_t flags)
	Enable one or more SMU interrupts.

__STATIC_INLINE uint32_t	SMU_IntGet (void)
	Get pending SMU interrupts.

__STATIC_INLINE uint32_t	SMU_IntGetEnabled (void)
	Get enabled and pending SMU interrupt flags. Useful for handling more interrupt sources in the same interrupt handler.

__STATIC_INLINE void	SMU_IntSet (uint32_t flags)
	Set one or more pending SMU interrupts from SW.

__STATIC_INLINE void	SMU_SetPrivilegedAccess ( SMU_Peripheral_TypeDef peripheral, bool privileged)
	Change access settings for a peripheral.

Macro Definition Documentation

#define SMU_INIT_DEFAULT

Value:

         { \
        
         { { 0 } },
         
          /* No peripherals access protected. */
         
         \
        
         true
         
          /* Enable SMU.*/
         
         \
        
         }

Default SMU initialization structure settings.

Definition at line 910 of file em_smu.h .

Enumeration Type Documentation

enum SMU_Peripheral_TypeDef

SMU peripheral identifiers.

Enumerator
smuPeripheralEMU	SMU peripheral identifier for EMU
smuPeripheralCMU	SMU peripheral identifier for CMU
smuPeripheralHFXO	SMU peripheral identifier for HFXO0
smuPeripheralHFRCO0	SMU peripheral identifier for HFRCO0
smuPeripheralFSRCO	SMU peripheral identifier for FSRCO
smuPeripheralDPLL0	SMU peripheral identifier for DPLL0
smuPeripheralLFXO	SMU peripheral identifier for LFXO
smuPeripheralLFRCO	SMU peripheral identifier for LFRCO
smuPeripheralULFRCO	SMU peripheral identifier for ULFRCO
smuPeripheralMSC	SMU peripheral identifier for MSC
smuPeripheralICACHE0	SMU peripheral identifier for ICACHE0
smuPeripheralPRS	SMU peripheral identifier for PRS
smuPeripheralGPIO	SMU peripheral identifier for GPIO
smuPeripheralLDMA	SMU peripheral identifier for LDMA
smuPeripheralLDMAXBAR	SMU peripheral identifier for LDMAXBAR
smuPeripheralTIMER0	SMU peripheral identifier for TIMER0
smuPeripheralTIMER1	SMU peripheral identifier for TIMER1
smuPeripheralTIMER2	SMU peripheral identifier for TIMER2
smuPeripheralTIMER3	SMU peripheral identifier for TIMER3
smuPeripheralUSART0	SMU peripheral identifier for USART0
smuPeripheralUSART1	SMU peripheral identifier for USART1
smuPeripheralBURTC	SMU peripheral identifier for BURTC
smuPeripheralI2C1	SMU peripheral identifier for I2C1
smuPeripheralCHIPTESTCTRL	SMU peripheral identifier for CHIPTESTCTRL
smuPeripheralSYSCFG	SMU peripheral identifier for SYSCFG
smuPeripheralBURAM	SMU peripheral identifier for BURAM
smuPeripheralIFADCDEBUG	SMU peripheral identifier for IFADCDEBUG
smuPeripheralGPCRC	SMU peripheral identifier for GPCRC
smuPeripheralRTCC	SMU peripheral identifier for RTCC
smuPeripheralDCDC	SMU peripheral identifier for DCDC
smuPeripheralPDM	SMU peripheral identifier for PDM
smuPeripheralRFSENSE	SMU peripheral identifier for RFSENSE
smuPeripheralLETIMER0	SMU peripheral identifier for LETIMER
smuPeripheralIADC0	SMU peripheral identifier for IADC0
smuPeripheralI2C0	SMU peripheral identifier for I2C0
smuPeripheralWDOG0	SMU peripheral identifier for WDOG0
smuPeripheralAMUXCP0	SMU peripheral identifier for AMUXCP0
smuPeripheralRADIOAES	SMU peripheral identifier for RADIOAES
smuPeripheralEUART0	SMU peripheral identifier for EUART0
smuPeripheralBUFC	SMU peripheral identifier for BUFC
smuPeripheralSMU	SMU peripheral identifier for SMU
smuPeripheralSMUCFGNS	SMU peripheral identifier for SMUCFGNS
smuPeripheralAHBRADIO	SMU peripheral identifier for AHBRADIO
smuPeripheralCRYPTOACC	SMU peripheral identifier for CRYPTOACC

Definition at line 77 of file em_smu.h .

Function Documentation

__STATIC_INLINE void SMU_EnablePPU ( bool enable )

Enable or disable PPU of SMU.

Parameters

[in] enable Set to true to enable PPU; set to false otherwise.

Definition at line 926 of file em_smu.h .

References BUS_RegBitWrite() .

Referenced by SMU_Init() .

__STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral ( void )

Get ID of the peripheral that caused an access fault.

Note: The return value is only valid if SMU_IF_PPUPRIV interrupt flag is set.

Returns: ID of the peripheral that caused an access fault.

Definition at line 988 of file em_smu.h .

__STATIC_INLINE void SMU_Init ( const SMU_Init_TypeDef * init )

Initialize PPU of SMU.

Parameters

[in] init Pointer to initialization structure that defines which peripherals should only be accessed from privileged mode, and if PPU should be enabled.

Definition at line 943 of file em_smu.h .

References SMU_Init_TypeDef::enable , SMU_Init_TypeDef::reg , and SMU_EnablePPU() .

__STATIC_INLINE void SMU_IntClear ( uint32_t flags )

Clear one or more pending SMU interrupts.

Parameters

[in] flags Bitwise logic OR of SMU interrupt sources to clear.

Definition at line 1000 of file em_smu.h .

__STATIC_INLINE void SMU_IntDisable ( uint32_t flags )

Disable one or more SMU interrupts.

Parameters

[in] flags SMU interrupt sources to disable.

Definition at line 1016 of file em_smu.h .

__STATIC_INLINE void SMU_IntEnable ( uint32_t flags )

Enable one or more SMU interrupts.

Note: Depending on the use, a pending interrupt may already be set prior to enabling the interrupt. To ignore a pending interrupt, consider using SMU_IntClear() prior to enabling the interrupt.

Parameters

[in] flags SMU interrupt sources to enable.

Definition at line 1037 of file em_smu.h .

__STATIC_INLINE uint32_t SMU_IntGet ( void )

Get pending SMU interrupts.

Returns: SMU interrupt sources pending.

Definition at line 1053 of file em_smu.h .

__STATIC_INLINE uint32_t SMU_IntGetEnabled ( void )

Get enabled and pending SMU interrupt flags. Useful for handling more interrupt sources in the same interrupt handler.

Note: Interrupt flags are not cleared by this function.

Returns

Pending and enabled SMU interrupt sources. The return value is the bitwise AND combination of

the OR combination of enabled interrupt sources in SMU_IEN register and
the OR combination of valid interrupt flags in SMU_IF register.

Definition at line 1073 of file em_smu.h .

__STATIC_INLINE void SMU_IntSet ( uint32_t flags )

Set one or more pending SMU interrupts from SW.

Parameters

[in] flags SMU interrupt sources to set to pending.

Definition at line 1092 of file em_smu.h .

__STATIC_INLINE void SMU_SetPrivilegedAccess	(	SMU_Peripheral_TypeDef	`peripheral,`
		bool	`privileged`
	)

Change access settings for a peripheral.

Set to limit access of a peripheral from privileged mode.

Parameters

[in]	`peripheral`	ID of the peripheral to change access settings for.
[in]	`privileged`	Set to true if the peripheral should only be accessed from privileged mode; set to false otherwise.

Definition at line 965 of file em_smu.h .

References BUS_RegBitWrite() .

SMUEMLIB

Detailed Description

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation