Macros
#define	_CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL

#define	_CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL

#define	_CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL

#define	_CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL

#define	_CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL

#define	_CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL

#define	_CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL

#define	_CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL

#define	_CMU_AUXHFRCOCTRL_BAND_SHIFT 8

#define	_CMU_AUXHFRCOCTRL_MASK 0x000007FFUL

#define	_CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL

#define	_CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL

#define	_CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL

#define	_CMU_AUXHFRCOCTRL_TUNING_SHIFT 0

#define	_CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL

#define	_CMU_CALCNT_CALCNT_MASK 0xFFFFFUL

#define	_CMU_CALCNT_CALCNT_SHIFT 0

#define	_CMU_CALCNT_MASK 0x000FFFFFUL

#define	_CMU_CALCNT_RESETVALUE 0x00000000UL

#define	_CMU_CALCTRL_CONT_DEFAULT 0x00000000UL

#define	_CMU_CALCTRL_CONT_MASK 0x40UL

#define	_CMU_CALCTRL_CONT_SHIFT 6

#define	_CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL

#define	_CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL

#define	_CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL

#define	_CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL

#define	_CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL

#define	_CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL

#define	_CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL

#define	_CMU_CALCTRL_DOWNSEL_MASK 0x38UL

#define	_CMU_CALCTRL_DOWNSEL_SHIFT 3

#define	_CMU_CALCTRL_MASK 0x0000007FUL

#define	_CMU_CALCTRL_RESETVALUE 0x00000000UL

#define	_CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL

#define	_CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL

#define	_CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL

#define	_CMU_CALCTRL_UPSEL_HFXO 0x00000000UL

#define	_CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL

#define	_CMU_CALCTRL_UPSEL_LFXO 0x00000001UL

#define	_CMU_CALCTRL_UPSEL_MASK 0x7UL

#define	_CMU_CALCTRL_UPSEL_SHIFT 0

#define	_CMU_CMD_CALSTART_DEFAULT 0x00000000UL

#define	_CMU_CMD_CALSTART_MASK 0x8UL

#define	_CMU_CMD_CALSTART_SHIFT 3

#define	_CMU_CMD_CALSTOP_DEFAULT 0x00000000UL

#define	_CMU_CMD_CALSTOP_MASK 0x10UL

#define	_CMU_CMD_CALSTOP_SHIFT 4

#define	_CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL

#define	_CMU_CMD_HFCLKSEL_HFXO 0x00000002UL

#define	_CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL

#define	_CMU_CMD_HFCLKSEL_LFXO 0x00000004UL

#define	_CMU_CMD_HFCLKSEL_MASK 0x7UL

#define	_CMU_CMD_HFCLKSEL_SHIFT 0

#define	_CMU_CMD_MASK 0x000000FFUL

#define	_CMU_CMD_RESETVALUE 0x00000000UL

#define	_CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL

#define	_CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL

#define	_CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL

#define	_CMU_CMD_USBCCLKSEL_MASK 0xE0UL

#define	_CMU_CMD_USBCCLKSEL_SHIFT 5

#define	_CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL

#define	_CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL

#define	_CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL

#define	_CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL

#define	_CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL

#define	_CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL

#define	_CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL

#define	_CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL

#define	_CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL

#define	_CMU_CTRL_CLKOUTSEL0_SHIFT 20

#define	_CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL

#define	_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL

#define	_CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL

#define	_CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL

#define	_CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL

#define	_CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL

#define	_CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL

#define	_CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL

#define	_CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL

#define	_CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL

#define	_CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL

#define	_CMU_CTRL_CLKOUTSEL1_SHIFT 23

#define	_CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL

#define	_CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL

#define	_CMU_CTRL_DBGCLK_HFCLK 0x00000001UL

#define	_CMU_CTRL_DBGCLK_MASK 0x10000000UL

#define	_CMU_CTRL_DBGCLK_SHIFT 28

#define	_CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL

#define	_CMU_CTRL_HFCLKDIV_MASK 0x1C000UL

#define	_CMU_CTRL_HFCLKDIV_SHIFT 14

#define	_CMU_CTRL_HFLE_DEFAULT 0x00000000UL

#define	_CMU_CTRL_HFLE_MASK 0x40000000UL

#define	_CMU_CTRL_HFLE_SHIFT 30

#define	_CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL

#define	_CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL

#define	_CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL

#define	_CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL

#define	_CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL

#define	_CMU_CTRL_HFXOBOOST_MASK 0xCUL

#define	_CMU_CTRL_HFXOBOOST_SHIFT 2

#define	_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL

#define	_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL

#define	_CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL

#define	_CMU_CTRL_HFXOBUFCUR_MASK 0x60UL

#define	_CMU_CTRL_HFXOBUFCUR_SHIFT 5

#define	_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL

#define	_CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL

#define	_CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7

#define	_CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL

#define	_CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL

#define	_CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL

#define	_CMU_CTRL_HFXOMODE_MASK 0x3UL

#define	_CMU_CTRL_HFXOMODE_SHIFT 0

#define	_CMU_CTRL_HFXOMODE_XTAL 0x00000000UL

#define	_CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL

#define	_CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL

#define	_CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL

#define	_CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL

#define	_CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL

#define	_CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL

#define	_CMU_CTRL_HFXOTIMEOUT_SHIFT 9

#define	_CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL

#define	_CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL

#define	_CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL

#define	_CMU_CTRL_LFXOBOOST_MASK 0x2000UL

#define	_CMU_CTRL_LFXOBOOST_SHIFT 13

#define	_CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL

#define	_CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL

#define	_CMU_CTRL_LFXOBUFCUR_SHIFT 17

#define	_CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL

#define	_CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL

#define	_CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL

#define	_CMU_CTRL_LFXOMODE_MASK 0x1800UL

#define	_CMU_CTRL_LFXOMODE_SHIFT 11

#define	_CMU_CTRL_LFXOMODE_XTAL 0x00000000UL

#define	_CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL

#define	_CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL

#define	_CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL

#define	_CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL

#define	_CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL

#define	_CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL

#define	_CMU_CTRL_LFXOTIMEOUT_SHIFT 18

#define	_CMU_CTRL_MASK 0x57FFFEEFUL

#define	_CMU_CTRL_RESETVALUE 0x000C262CUL

#define	_CMU_FREEZE_MASK 0x00000001UL

#define	_CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL

#define	_CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL

#define	_CMU_FREEZE_REGFREEZE_MASK 0x1UL

#define	_CMU_FREEZE_REGFREEZE_SHIFT 0

#define	_CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL

#define	_CMU_FREEZE_RESETVALUE 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8

#define	_CMU_HFCORECLKDIV_MASK 0x0000010FUL

#define	_CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL

#define	_CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_AES_MASK 0x2UL

#define	_CMU_HFCORECLKEN0_AES_SHIFT 1

#define	_CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_DMA_MASK 0x1UL

#define	_CMU_HFCORECLKEN0_DMA_SHIFT 0

#define	_CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_LE_MASK 0x10UL

#define	_CMU_HFCORECLKEN0_LE_SHIFT 4

#define	_CMU_HFCORECLKEN0_MASK 0x0000001FUL

#define	_CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL

#define	_CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_USB_MASK 0x8UL

#define	_CMU_HFCORECLKEN0_USB_SHIFT 3

#define	_CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_USBC_MASK 0x4UL

#define	_CMU_HFCORECLKEN0_USBC_SHIFT 2

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0

#define	_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL

#define	_CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL

#define	_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8

#define	_CMU_HFPERCLKDIV_MASK 0x0000010FUL

#define	_CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL

#define	_CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL

#define	_CMU_HFPERCLKEN0_ACMP0_SHIFT 9

#define	_CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL

#define	_CMU_HFPERCLKEN0_ACMP1_SHIFT 10

#define	_CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL

#define	_CMU_HFPERCLKEN0_ADC0_SHIFT 16

#define	_CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL

#define	_CMU_HFPERCLKEN0_DAC0_SHIFT 17

#define	_CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL

#define	_CMU_HFPERCLKEN0_GPIO_SHIFT 13

#define	_CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_I2C0_MASK 0x800UL

#define	_CMU_HFPERCLKEN0_I2C0_SHIFT 11

#define	_CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL

#define	_CMU_HFPERCLKEN0_I2C1_SHIFT 12

#define	_CMU_HFPERCLKEN0_MASK 0x0003FFFFUL

#define	_CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_PRS_MASK 0x8000UL

#define	_CMU_HFPERCLKEN0_PRS_SHIFT 15

#define	_CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL

#define	_CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL

#define	_CMU_HFPERCLKEN0_TIMER0_SHIFT 5

#define	_CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL

#define	_CMU_HFPERCLKEN0_TIMER1_SHIFT 6

#define	_CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL

#define	_CMU_HFPERCLKEN0_TIMER2_SHIFT 7

#define	_CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL

#define	_CMU_HFPERCLKEN0_TIMER3_SHIFT 8

#define	_CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_UART0_MASK 0x8UL

#define	_CMU_HFPERCLKEN0_UART0_SHIFT 3

#define	_CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_UART1_MASK 0x10UL

#define	_CMU_HFPERCLKEN0_UART1_SHIFT 4

#define	_CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_USART1_MASK 0x2UL

#define	_CMU_HFPERCLKEN0_USART1_SHIFT 1

#define	_CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_USART2_MASK 0x4UL

#define	_CMU_HFPERCLKEN0_USART2_SHIFT 2

#define	_CMU_HFPERCLKEN0_USARTRF0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_USARTRF0_MASK 0x1UL

#define	_CMU_HFPERCLKEN0_USARTRF0_SHIFT 0

#define	_CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL

#define	_CMU_HFPERCLKEN0_VCMP_SHIFT 14

#define	_CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL

#define	_CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL

#define	_CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL

#define	_CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL

#define	_CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL

#define	_CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL

#define	_CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL

#define	_CMU_HFRCOCTRL_BAND_MASK 0x700UL

#define	_CMU_HFRCOCTRL_BAND_SHIFT 8

#define	_CMU_HFRCOCTRL_MASK 0x0001F7FFUL

#define	_CMU_HFRCOCTRL_RESETVALUE 0x00000380UL

#define	_CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL

#define	_CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL

#define	_CMU_HFRCOCTRL_SUDELAY_SHIFT 12

#define	_CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL

#define	_CMU_HFRCOCTRL_TUNING_MASK 0xFFUL

#define	_CMU_HFRCOCTRL_TUNING_SHIFT 0

#define	_CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_AUXHFRCORDY_MASK 0x10UL

#define	_CMU_IEN_AUXHFRCORDY_SHIFT 4

#define	_CMU_IEN_CALOF_DEFAULT 0x00000000UL

#define	_CMU_IEN_CALOF_MASK 0x40UL

#define	_CMU_IEN_CALOF_SHIFT 6

#define	_CMU_IEN_CALRDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_CALRDY_MASK 0x20UL

#define	_CMU_IEN_CALRDY_SHIFT 5

#define	_CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_HFRCORDY_MASK 0x1UL

#define	_CMU_IEN_HFRCORDY_SHIFT 0

#define	_CMU_IEN_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_HFXORDY_MASK 0x2UL

#define	_CMU_IEN_HFXORDY_SHIFT 1

#define	_CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_LFRCORDY_MASK 0x4UL

#define	_CMU_IEN_LFRCORDY_SHIFT 2

#define	_CMU_IEN_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_LFXORDY_MASK 0x8UL

#define	_CMU_IEN_LFXORDY_SHIFT 3

#define	_CMU_IEN_MASK 0x000000FFUL

#define	_CMU_IEN_RESETVALUE 0x00000000UL

#define	_CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_IEN_USBCHFCLKSEL_MASK 0x80UL

#define	_CMU_IEN_USBCHFCLKSEL_SHIFT 7

#define	_CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IF_AUXHFRCORDY_MASK 0x10UL

#define	_CMU_IF_AUXHFRCORDY_SHIFT 4

#define	_CMU_IF_CALOF_DEFAULT 0x00000000UL

#define	_CMU_IF_CALOF_MASK 0x40UL

#define	_CMU_IF_CALOF_SHIFT 6

#define	_CMU_IF_CALRDY_DEFAULT 0x00000000UL

#define	_CMU_IF_CALRDY_MASK 0x20UL

#define	_CMU_IF_CALRDY_SHIFT 5

#define	_CMU_IF_HFRCORDY_DEFAULT 0x00000001UL

#define	_CMU_IF_HFRCORDY_MASK 0x1UL

#define	_CMU_IF_HFRCORDY_SHIFT 0

#define	_CMU_IF_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IF_HFXORDY_MASK 0x2UL

#define	_CMU_IF_HFXORDY_SHIFT 1

#define	_CMU_IF_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IF_LFRCORDY_MASK 0x4UL

#define	_CMU_IF_LFRCORDY_SHIFT 2

#define	_CMU_IF_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IF_LFXORDY_MASK 0x8UL

#define	_CMU_IF_LFXORDY_SHIFT 3

#define	_CMU_IF_MASK 0x000000FFUL

#define	_CMU_IF_RESETVALUE 0x00000001UL

#define	_CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_IF_USBCHFCLKSEL_MASK 0x80UL

#define	_CMU_IF_USBCHFCLKSEL_SHIFT 7

#define	_CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_AUXHFRCORDY_MASK 0x10UL

#define	_CMU_IFC_AUXHFRCORDY_SHIFT 4

#define	_CMU_IFC_CALOF_DEFAULT 0x00000000UL

#define	_CMU_IFC_CALOF_MASK 0x40UL

#define	_CMU_IFC_CALOF_SHIFT 6

#define	_CMU_IFC_CALRDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_CALRDY_MASK 0x20UL

#define	_CMU_IFC_CALRDY_SHIFT 5

#define	_CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_HFRCORDY_MASK 0x1UL

#define	_CMU_IFC_HFRCORDY_SHIFT 0

#define	_CMU_IFC_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_HFXORDY_MASK 0x2UL

#define	_CMU_IFC_HFXORDY_SHIFT 1

#define	_CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_LFRCORDY_MASK 0x4UL

#define	_CMU_IFC_LFRCORDY_SHIFT 2

#define	_CMU_IFC_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_LFXORDY_MASK 0x8UL

#define	_CMU_IFC_LFXORDY_SHIFT 3

#define	_CMU_IFC_MASK 0x000000FFUL

#define	_CMU_IFC_RESETVALUE 0x00000000UL

#define	_CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_IFC_USBCHFCLKSEL_MASK 0x80UL

#define	_CMU_IFC_USBCHFCLKSEL_SHIFT 7

#define	_CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_AUXHFRCORDY_MASK 0x10UL

#define	_CMU_IFS_AUXHFRCORDY_SHIFT 4

#define	_CMU_IFS_CALOF_DEFAULT 0x00000000UL

#define	_CMU_IFS_CALOF_MASK 0x40UL

#define	_CMU_IFS_CALOF_SHIFT 6

#define	_CMU_IFS_CALRDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_CALRDY_MASK 0x20UL

#define	_CMU_IFS_CALRDY_SHIFT 5

#define	_CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_HFRCORDY_MASK 0x1UL

#define	_CMU_IFS_HFRCORDY_SHIFT 0

#define	_CMU_IFS_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_HFXORDY_MASK 0x2UL

#define	_CMU_IFS_HFXORDY_SHIFT 1

#define	_CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_LFRCORDY_MASK 0x4UL

#define	_CMU_IFS_LFRCORDY_SHIFT 2

#define	_CMU_IFS_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_LFXORDY_MASK 0x8UL

#define	_CMU_IFS_LFXORDY_SHIFT 3

#define	_CMU_IFS_MASK 0x000000FFUL

#define	_CMU_IFS_RESETVALUE 0x00000000UL

#define	_CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_IFS_USBCHFCLKSEL_MASK 0x80UL

#define	_CMU_IFS_USBCHFCLKSEL_SHIFT 7

#define	_CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL

#define	_CMU_LFACLKEN0_LESENSE_MASK 0x1UL

#define	_CMU_LFACLKEN0_LESENSE_SHIFT 0

#define	_CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL

#define	_CMU_LFACLKEN0_LETIMER0_MASK 0x4UL

#define	_CMU_LFACLKEN0_LETIMER0_SHIFT 2

#define	_CMU_LFACLKEN0_MASK 0x00000007UL

#define	_CMU_LFACLKEN0_RESETVALUE 0x00000000UL

#define	_CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL

#define	_CMU_LFACLKEN0_RTC_MASK 0x2UL

#define	_CMU_LFACLKEN0_RTC_SHIFT 1

#define	_CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL

#define	_CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL

#define	_CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL

#define	_CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL

#define	_CMU_LFAPRESC0_LESENSE_MASK 0x3UL

#define	_CMU_LFAPRESC0_LESENSE_SHIFT 0

#define	_CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL

#define	_CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL

#define	_CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL

#define	_CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL

#define	_CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL

#define	_CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL

#define	_CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL

#define	_CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL

#define	_CMU_LFAPRESC0_LETIMER0_SHIFT 8

#define	_CMU_LFAPRESC0_MASK 0x00000FF3UL

#define	_CMU_LFAPRESC0_RESETVALUE 0x00000000UL

#define	_CMU_LFAPRESC0_RTC_DIV1 0x00000000UL

#define	_CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL

#define	_CMU_LFAPRESC0_RTC_DIV128 0x00000007UL

#define	_CMU_LFAPRESC0_RTC_DIV16 0x00000004UL

#define	_CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL

#define	_CMU_LFAPRESC0_RTC_DIV2 0x00000001UL

#define	_CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL

#define	_CMU_LFAPRESC0_RTC_DIV256 0x00000008UL

#define	_CMU_LFAPRESC0_RTC_DIV32 0x00000005UL

#define	_CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL

#define	_CMU_LFAPRESC0_RTC_DIV4 0x00000002UL

#define	_CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL

#define	_CMU_LFAPRESC0_RTC_DIV512 0x00000009UL

#define	_CMU_LFAPRESC0_RTC_DIV64 0x00000006UL

#define	_CMU_LFAPRESC0_RTC_DIV8 0x00000003UL

#define	_CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL

#define	_CMU_LFAPRESC0_RTC_MASK 0xF0UL

#define	_CMU_LFAPRESC0_RTC_SHIFT 4

#define	_CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL

#define	_CMU_LFBCLKEN0_LEUART0_MASK 0x1UL

#define	_CMU_LFBCLKEN0_LEUART0_SHIFT 0

#define	_CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL

#define	_CMU_LFBCLKEN0_LEUART1_MASK 0x2UL

#define	_CMU_LFBCLKEN0_LEUART1_SHIFT 1

#define	_CMU_LFBCLKEN0_MASK 0x00000003UL

#define	_CMU_LFBCLKEN0_RESETVALUE 0x00000000UL

#define	_CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL

#define	_CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL

#define	_CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL

#define	_CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL

#define	_CMU_LFBPRESC0_LEUART0_MASK 0x3UL

EZR32WG_CMU_BitFieldsDevices

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