DMA_TypeDef Struct ReferenceDevices > EZR32WG_DMA

Definition at line 48 of file ezr32wg_dma.h.

Data Fields

__IM uint32_t ALTCTRLBASE
 
DMA_CH_TypeDef CH [12U]
 
__OM uint32_t CHALTC
 
__IOM uint32_t CHALTS
 
__OM uint32_t CHENC
 
__IOM uint32_t CHENS
 
__OM uint32_t CHPRIC
 
__IOM uint32_t CHPRIS
 
__OM uint32_t CHREQMASKC
 
__IOM uint32_t CHREQMASKS
 
__IM uint32_t CHREQSTATUS
 
__IM uint32_t CHSREQSTATUS
 
__OM uint32_t CHSWREQ
 
__OM uint32_t CHUSEBURSTC
 
__IOM uint32_t CHUSEBURSTS
 
__IM uint32_t CHWAITSTATUS
 
__OM uint32_t CONFIG
 
__IOM uint32_t CTRL
 
__IOM uint32_t CTRLBASE
 
__IOM uint32_t ERRORC
 
__IOM uint32_t IEN
 
__IM uint32_t IF
 
__IOM uint32_t IFC
 
__IOM uint32_t IFS
 
__IOM uint32_t LOOP0
 
__IOM uint32_t LOOP1
 
__IOM uint32_t RDS
 
__IOM uint32_t RECT0
 
uint32_t RESERVED0 [3U]
 
uint32_t RESERVED1 [880U]
 
uint32_t RESERVED2 [1U]
 
uint32_t RESERVED3 [121U]
 
uint32_t RESERVED4 [2U]
 
uint32_t RESERVED5 [14U]
 
uint32_t RESERVED6 [39U]
 
__IM uint32_t STATUS
 

Field Documentation

__IM uint32_t DMA_TypeDef::ALTCTRLBASE

Channel Alternate Control Data Base Pointer Register

Definition at line 52 of file ezr32wg_dma.h.

DMA_CH_TypeDef DMA_TypeDef::CH[12U]

Channel registers

Definition at line 88 of file ezr32wg_dma.h.

__OM uint32_t DMA_TypeDef::CHALTC

Channel Alternate Clear Register

Definition at line 62 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::CHALTS

Channel Alternate Set Register

Definition at line 61 of file ezr32wg_dma.h.

__OM uint32_t DMA_TypeDef::CHENC

Channel Enable Clear Register

Definition at line 60 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::CHENS

Channel Enable Set Register

Definition at line 59 of file ezr32wg_dma.h.

__OM uint32_t DMA_TypeDef::CHPRIC

Channel Priority Clear Register

Definition at line 64 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::CHPRIS

Channel Priority Set Register

Definition at line 63 of file ezr32wg_dma.h.

__OM uint32_t DMA_TypeDef::CHREQMASKC

Channel Request Mask Clear Register

Definition at line 58 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::CHREQMASKS

Channel Request Mask Set Register

Definition at line 57 of file ezr32wg_dma.h.

__IM uint32_t DMA_TypeDef::CHREQSTATUS

Channel Request Status

Definition at line 69 of file ezr32wg_dma.h.

__IM uint32_t DMA_TypeDef::CHSREQSTATUS

Channel Single Request Status

Definition at line 71 of file ezr32wg_dma.h.

__OM uint32_t DMA_TypeDef::CHSWREQ

Channel Software Request Register

Definition at line 54 of file ezr32wg_dma.h.

__OM uint32_t DMA_TypeDef::CHUSEBURSTC

Channel Useburst Clear Register

Definition at line 56 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::CHUSEBURSTS

Channel Useburst Set Register

Definition at line 55 of file ezr32wg_dma.h.

__IM uint32_t DMA_TypeDef::CHWAITSTATUS

Channel Wait on Request Status Register

Definition at line 53 of file ezr32wg_dma.h.

__OM uint32_t DMA_TypeDef::CONFIG

DMA Configuration Register

Definition at line 50 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::CTRL

DMA Control Register

Definition at line 78 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::CTRLBASE

Channel Control Data Base Pointer Register

Definition at line 51 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::ERRORC

Bus Error Clear Register

Definition at line 66 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::IEN

Interrupt Enable register

Definition at line 77 of file ezr32wg_dma.h.

__IM uint32_t DMA_TypeDef::IF

Interrupt Flag Register

Definition at line 74 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::IFC

Interrupt Flag Clear Register

Definition at line 76 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::IFS

Interrupt Flag Set Register

Definition at line 75 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::LOOP0

Channel 0 Loop Register

Definition at line 82 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::LOOP1

Channel 1 Loop Register

Definition at line 83 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::RDS

DMA Retain Descriptor State

Definition at line 79 of file ezr32wg_dma.h.

__IOM uint32_t DMA_TypeDef::RECT0

Channel 0 Rectangle Register

Definition at line 85 of file ezr32wg_dma.h.

uint32_t DMA_TypeDef::RESERVED0[3U]

Reserved for future use

Definition at line 65 of file ezr32wg_dma.h.

uint32_t DMA_TypeDef::RESERVED1[880U]

Reserved for future use

Definition at line 68 of file ezr32wg_dma.h.

uint32_t DMA_TypeDef::RESERVED2[1U]

Reserved for future use

Definition at line 70 of file ezr32wg_dma.h.

uint32_t DMA_TypeDef::RESERVED3[121U]

Reserved for future use

Definition at line 73 of file ezr32wg_dma.h.

uint32_t DMA_TypeDef::RESERVED4[2U]

Reserved for future use

Definition at line 81 of file ezr32wg_dma.h.

uint32_t DMA_TypeDef::RESERVED5[14U]

Reserved for future use

Definition at line 84 of file ezr32wg_dma.h.

uint32_t DMA_TypeDef::RESERVED6[39U]

Reserved registers

Definition at line 87 of file ezr32wg_dma.h.

__IM uint32_t DMA_TypeDef::STATUS

DMA Status Registers

Definition at line 49 of file ezr32wg_dma.h.


The documentation for this struct was generated from the following file:
  • C:/repos/embsw_super_h1/platform/Device/SiliconLabs/EZR32WG/Include/ezr32wg_dma.h