|
#define
|
_DAC_BIASPROG_BIASPROG_DEFAULT
0x00000007UL
|
|
#define
|
_DAC_BIASPROG_BIASPROG_MASK
0xFUL
|
|
#define
|
_DAC_BIASPROG_BIASPROG_SHIFT
0
|
|
#define
|
_DAC_BIASPROG_HALFBIAS_DEFAULT
0x00000001UL
|
|
#define
|
_DAC_BIASPROG_HALFBIAS_MASK
0x40UL
|
|
#define
|
_DAC_BIASPROG_HALFBIAS_SHIFT
6
|
|
#define
|
_DAC_BIASPROG_MASK
0x00004F4FUL
|
|
#define
|
_DAC_BIASPROG_OPA2BIASPROG_DEFAULT
0x00000007UL
|
|
#define
|
_DAC_BIASPROG_OPA2BIASPROG_MASK
0xF00UL
|
|
#define
|
_DAC_BIASPROG_OPA2BIASPROG_SHIFT
8
|
|
#define
|
_DAC_BIASPROG_OPA2HALFBIAS_DEFAULT
0x00000001UL
|
|
#define
|
_DAC_BIASPROG_OPA2HALFBIAS_MASK
0x4000UL
|
|
#define
|
_DAC_BIASPROG_OPA2HALFBIAS_SHIFT
14
|
|
#define
|
_DAC_BIASPROG_RESETVALUE
0x00004747UL
|
|
#define
|
_DAC_CAL_CH0OFFSET_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CAL_CH0OFFSET_MASK
0x3FUL
|
|
#define
|
_DAC_CAL_CH0OFFSET_SHIFT
0
|
|
#define
|
_DAC_CAL_CH1OFFSET_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CAL_CH1OFFSET_MASK
0x3F00UL
|
|
#define
|
_DAC_CAL_CH1OFFSET_SHIFT
8
|
|
#define
|
_DAC_CAL_GAIN_DEFAULT
0x00000040UL
|
|
#define
|
_DAC_CAL_GAIN_MASK
0x7F0000UL
|
|
#define
|
_DAC_CAL_GAIN_SHIFT
16
|
|
#define
|
_DAC_CAL_MASK
0x007F3F3FUL
|
|
#define
|
_DAC_CAL_RESETVALUE
0x00400000UL
|
|
#define
|
_DAC_CH0CTRL_EN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CH0CTRL_EN_MASK
0x1UL
|
|
#define
|
_DAC_CH0CTRL_EN_SHIFT
0
|
|
#define
|
_DAC_CH0CTRL_MASK
0x000000F7UL
|
|
#define
|
_DAC_CH0CTRL_PRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CH0CTRL_PRSEN_MASK
0x4UL
|
|
#define
|
_DAC_CH0CTRL_PRSEN_SHIFT
2
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_MASK
0xF0UL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_PRSCH0
0x00000000UL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_PRSCH1
0x00000001UL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_PRSCH10
0x0000000AUL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_PRSCH11
0x0000000BUL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_PRSCH2
0x00000002UL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_PRSCH3
0x00000003UL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_PRSCH4
0x00000004UL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_PRSCH5
0x00000005UL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_PRSCH6
0x00000006UL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_PRSCH7
0x00000007UL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_PRSCH8
0x00000008UL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_PRSCH9
0x00000009UL
|
|
#define
|
_DAC_CH0CTRL_PRSSEL_SHIFT
4
|
|
#define
|
_DAC_CH0CTRL_REFREN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CH0CTRL_REFREN_MASK
0x2UL
|
|
#define
|
_DAC_CH0CTRL_REFREN_SHIFT
1
|
|
#define
|
_DAC_CH0CTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_DAC_CH0DATA_DATA_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CH0DATA_DATA_MASK
0xFFFUL
|
|
#define
|
_DAC_CH0DATA_DATA_SHIFT
0
|
|
#define
|
_DAC_CH0DATA_MASK
0x00000FFFUL
|
|
#define
|
_DAC_CH0DATA_RESETVALUE
0x00000000UL
|
|
#define
|
_DAC_CH1CTRL_EN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CH1CTRL_EN_MASK
0x1UL
|
|
#define
|
_DAC_CH1CTRL_EN_SHIFT
0
|
|
#define
|
_DAC_CH1CTRL_MASK
0x000000F7UL
|
|
#define
|
_DAC_CH1CTRL_PRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CH1CTRL_PRSEN_MASK
0x4UL
|
|
#define
|
_DAC_CH1CTRL_PRSEN_SHIFT
2
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_MASK
0xF0UL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_PRSCH0
0x00000000UL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_PRSCH1
0x00000001UL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_PRSCH10
0x0000000AUL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_PRSCH11
0x0000000BUL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_PRSCH2
0x00000002UL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_PRSCH3
0x00000003UL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_PRSCH4
0x00000004UL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_PRSCH5
0x00000005UL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_PRSCH6
0x00000006UL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_PRSCH7
0x00000007UL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_PRSCH8
0x00000008UL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_PRSCH9
0x00000009UL
|
|
#define
|
_DAC_CH1CTRL_PRSSEL_SHIFT
4
|
|
#define
|
_DAC_CH1CTRL_REFREN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CH1CTRL_REFREN_MASK
0x2UL
|
|
#define
|
_DAC_CH1CTRL_REFREN_SHIFT
1
|
|
#define
|
_DAC_CH1CTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_DAC_CH1DATA_DATA_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CH1DATA_DATA_MASK
0xFFFUL
|
|
#define
|
_DAC_CH1DATA_DATA_SHIFT
0
|
|
#define
|
_DAC_CH1DATA_MASK
0x00000FFFUL
|
|
#define
|
_DAC_CH1DATA_RESETVALUE
0x00000000UL
|
|
#define
|
_DAC_COMBDATA_CH0DATA_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_COMBDATA_CH0DATA_MASK
0xFFFUL
|
|
#define
|
_DAC_COMBDATA_CH0DATA_SHIFT
0
|
|
#define
|
_DAC_COMBDATA_CH1DATA_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_COMBDATA_CH1DATA_MASK
0xFFF0000UL
|
|
#define
|
_DAC_COMBDATA_CH1DATA_SHIFT
16
|
|
#define
|
_DAC_COMBDATA_MASK
0x0FFF0FFFUL
|
|
#define
|
_DAC_COMBDATA_RESETVALUE
0x00000000UL
|
|
#define
|
_DAC_CTRL_CH0PRESCRST_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CTRL_CH0PRESCRST_MASK
0x80UL
|
|
#define
|
_DAC_CTRL_CH0PRESCRST_SHIFT
7
|
|
#define
|
_DAC_CTRL_CONVMODE_CONTINUOUS
0x00000000UL
|
|
#define
|
_DAC_CTRL_CONVMODE_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CTRL_CONVMODE_MASK
0xCUL
|
|
#define
|
_DAC_CTRL_CONVMODE_SAMPLEHOLD
0x00000001UL
|
|
#define
|
_DAC_CTRL_CONVMODE_SAMPLEOFF
0x00000002UL
|
|
#define
|
_DAC_CTRL_CONVMODE_SHIFT
2
|
|
#define
|
_DAC_CTRL_DIFF_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CTRL_DIFF_MASK
0x1UL
|
|
#define
|
_DAC_CTRL_DIFF_SHIFT
0
|
|
#define
|
_DAC_CTRL_MASK
0x003703FFUL
|
|
#define
|
_DAC_CTRL_OUTENPRS_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CTRL_OUTENPRS_MASK
0x40UL
|
|
#define
|
_DAC_CTRL_OUTENPRS_SHIFT
6
|
|
#define
|
_DAC_CTRL_OUTMODE_ADC
0x00000002UL
|
|
#define
|
_DAC_CTRL_OUTMODE_DEFAULT
0x00000001UL
|
|
#define
|
_DAC_CTRL_OUTMODE_DISABLE
0x00000000UL
|
|
#define
|
_DAC_CTRL_OUTMODE_MASK
0x30UL
|
|
#define
|
_DAC_CTRL_OUTMODE_PIN
0x00000001UL
|
|
#define
|
_DAC_CTRL_OUTMODE_PINADC
0x00000003UL
|
|
#define
|
_DAC_CTRL_OUTMODE_SHIFT
4
|
|
#define
|
_DAC_CTRL_PRESC_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CTRL_PRESC_MASK
0x70000UL
|
|
#define
|
_DAC_CTRL_PRESC_NODIVISION
0x00000000UL
|
|
#define
|
_DAC_CTRL_PRESC_SHIFT
16
|
|
#define
|
_DAC_CTRL_REFRSEL_16CYCLES
0x00000001UL
|
|
#define
|
_DAC_CTRL_REFRSEL_32CYCLES
0x00000002UL
|
|
#define
|
_DAC_CTRL_REFRSEL_64CYCLES
0x00000003UL
|
|
#define
|
_DAC_CTRL_REFRSEL_8CYCLES
0x00000000UL
|
|
#define
|
_DAC_CTRL_REFRSEL_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CTRL_REFRSEL_MASK
0x300000UL
|
|
#define
|
_DAC_CTRL_REFRSEL_SHIFT
20
|
|
#define
|
_DAC_CTRL_REFSEL_1V25
0x00000000UL
|
|
#define
|
_DAC_CTRL_REFSEL_2V5
0x00000001UL
|
|
#define
|
_DAC_CTRL_REFSEL_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CTRL_REFSEL_MASK
0x300UL
|
|
#define
|
_DAC_CTRL_REFSEL_SHIFT
8
|
|
#define
|
_DAC_CTRL_REFSEL_VDD
0x00000002UL
|
|
#define
|
_DAC_CTRL_RESETVALUE
0x00000010UL
|
|
#define
|
_DAC_CTRL_SINEMODE_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_CTRL_SINEMODE_MASK
0x2UL
|
|
#define
|
_DAC_CTRL_SINEMODE_SHIFT
1
|
|
#define
|
_DAC_IEN_CH0_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IEN_CH0_MASK
0x1UL
|
|
#define
|
_DAC_IEN_CH0_SHIFT
0
|
|
#define
|
_DAC_IEN_CH0UF_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IEN_CH0UF_MASK
0x10UL
|
|
#define
|
_DAC_IEN_CH0UF_SHIFT
4
|
|
#define
|
_DAC_IEN_CH1_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IEN_CH1_MASK
0x2UL
|
|
#define
|
_DAC_IEN_CH1_SHIFT
1
|
|
#define
|
_DAC_IEN_CH1UF_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IEN_CH1UF_MASK
0x20UL
|
|
#define
|
_DAC_IEN_CH1UF_SHIFT
5
|
|
#define
|
_DAC_IEN_MASK
0x00000033UL
|
|
#define
|
_DAC_IEN_RESETVALUE
0x00000000UL
|
|
#define
|
_DAC_IF_CH0_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IF_CH0_MASK
0x1UL
|
|
#define
|
_DAC_IF_CH0_SHIFT
0
|
|
#define
|
_DAC_IF_CH0UF_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IF_CH0UF_MASK
0x10UL
|
|
#define
|
_DAC_IF_CH0UF_SHIFT
4
|
|
#define
|
_DAC_IF_CH1_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IF_CH1_MASK
0x2UL
|
|
#define
|
_DAC_IF_CH1_SHIFT
1
|
|
#define
|
_DAC_IF_CH1UF_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IF_CH1UF_MASK
0x20UL
|
|
#define
|
_DAC_IF_CH1UF_SHIFT
5
|
|
#define
|
_DAC_IF_MASK
0x00000033UL
|
|
#define
|
_DAC_IF_RESETVALUE
0x00000000UL
|
|
#define
|
_DAC_IFC_CH0_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IFC_CH0_MASK
0x1UL
|
|
#define
|
_DAC_IFC_CH0_SHIFT
0
|
|
#define
|
_DAC_IFC_CH0UF_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IFC_CH0UF_MASK
0x10UL
|
|
#define
|
_DAC_IFC_CH0UF_SHIFT
4
|
|
#define
|
_DAC_IFC_CH1_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IFC_CH1_MASK
0x2UL
|
|
#define
|
_DAC_IFC_CH1_SHIFT
1
|
|
#define
|
_DAC_IFC_CH1UF_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IFC_CH1UF_MASK
0x20UL
|
|
#define
|
_DAC_IFC_CH1UF_SHIFT
5
|
|
#define
|
_DAC_IFC_MASK
0x00000033UL
|
|
#define
|
_DAC_IFC_RESETVALUE
0x00000000UL
|
|
#define
|
_DAC_IFS_CH0_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IFS_CH0_MASK
0x1UL
|
|
#define
|
_DAC_IFS_CH0_SHIFT
0
|
|
#define
|
_DAC_IFS_CH0UF_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IFS_CH0UF_MASK
0x10UL
|
|
#define
|
_DAC_IFS_CH0UF_SHIFT
4
|
|
#define
|
_DAC_IFS_CH1_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IFS_CH1_MASK
0x2UL
|
|
#define
|
_DAC_IFS_CH1_SHIFT
1
|
|
#define
|
_DAC_IFS_CH1UF_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_IFS_CH1UF_MASK
0x20UL
|
|
#define
|
_DAC_IFS_CH1UF_SHIFT
5
|
|
#define
|
_DAC_IFS_MASK
0x00000033UL
|
|
#define
|
_DAC_IFS_RESETVALUE
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_MASK
0x74C7F737UL
|
|
#define
|
_DAC_OPA0MUX_NEGSEL_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_NEGSEL_DISABLE
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_NEGSEL_MASK
0x30UL
|
|
#define
|
_DAC_OPA0MUX_NEGSEL_NEGPAD
0x00000003UL
|
|
#define
|
_DAC_OPA0MUX_NEGSEL_OPATAP
0x00000002UL
|
|
#define
|
_DAC_OPA0MUX_NEGSEL_SHIFT
4
|
|
#define
|
_DAC_OPA0MUX_NEGSEL_UG
0x00000001UL
|
|
#define
|
_DAC_OPA0MUX_NEXTOUT_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_NEXTOUT_MASK
0x4000000UL
|
|
#define
|
_DAC_OPA0MUX_NEXTOUT_SHIFT
26
|
|
#define
|
_DAC_OPA0MUX_NPEN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_NPEN_MASK
0x2000UL
|
|
#define
|
_DAC_OPA0MUX_NPEN_SHIFT
13
|
|
#define
|
_DAC_OPA0MUX_OUTMODE_ALL
0x00000003UL
|
|
#define
|
_DAC_OPA0MUX_OUTMODE_ALT
0x00000002UL
|
|
#define
|
_DAC_OPA0MUX_OUTMODE_DEFAULT
0x00000001UL
|
|
#define
|
_DAC_OPA0MUX_OUTMODE_DISABLE
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_OUTMODE_MAIN
0x00000001UL
|
|
#define
|
_DAC_OPA0MUX_OUTMODE_MASK
0xC00000UL
|
|
#define
|
_DAC_OPA0MUX_OUTMODE_SHIFT
22
|
|
#define
|
_DAC_OPA0MUX_OUTPEN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_OUTPEN_MASK
0x7C000UL
|
|
#define
|
_DAC_OPA0MUX_OUTPEN_OUT0
0x00000001UL
|
|
#define
|
_DAC_OPA0MUX_OUTPEN_OUT1
0x00000002UL
|
|
#define
|
_DAC_OPA0MUX_OUTPEN_OUT2
0x00000004UL
|
|
#define
|
_DAC_OPA0MUX_OUTPEN_OUT3
0x00000008UL
|
|
#define
|
_DAC_OPA0MUX_OUTPEN_OUT4
0x00000010UL
|
|
#define
|
_DAC_OPA0MUX_OUTPEN_SHIFT
14
|
|
#define
|
_DAC_OPA0MUX_POSSEL_DAC
0x00000001UL
|
|
#define
|
_DAC_OPA0MUX_POSSEL_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_POSSEL_DISABLE
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_POSSEL_MASK
0x7UL
|
|
#define
|
_DAC_OPA0MUX_POSSEL_OPA0INP
0x00000003UL
|
|
#define
|
_DAC_OPA0MUX_POSSEL_OPATAP
0x00000004UL
|
|
#define
|
_DAC_OPA0MUX_POSSEL_POSPAD
0x00000002UL
|
|
#define
|
_DAC_OPA0MUX_POSSEL_SHIFT
0
|
|
#define
|
_DAC_OPA0MUX_PPEN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_PPEN_MASK
0x1000UL
|
|
#define
|
_DAC_OPA0MUX_PPEN_SHIFT
12
|
|
#define
|
_DAC_OPA0MUX_RESETVALUE
0x00400000UL
|
|
#define
|
_DAC_OPA0MUX_RESINMUX_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_RESINMUX_DISABLE
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_RESINMUX_MASK
0x700UL
|
|
#define
|
_DAC_OPA0MUX_RESINMUX_NEGPAD
0x00000002UL
|
|
#define
|
_DAC_OPA0MUX_RESINMUX_OPA0INP
0x00000001UL
|
|
#define
|
_DAC_OPA0MUX_RESINMUX_POSPAD
0x00000003UL
|
|
#define
|
_DAC_OPA0MUX_RESINMUX_SHIFT
8
|
|
#define
|
_DAC_OPA0MUX_RESINMUX_VSS
0x00000004UL
|
|
#define
|
_DAC_OPA0MUX_RESSEL_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_RESSEL_MASK
0x70000000UL
|
|
#define
|
_DAC_OPA0MUX_RESSEL_RES0
0x00000000UL
|
|
#define
|
_DAC_OPA0MUX_RESSEL_RES1
0x00000001UL
|
|
#define
|
_DAC_OPA0MUX_RESSEL_RES2
0x00000002UL
|
|
#define
|
_DAC_OPA0MUX_RESSEL_RES3
0x00000003UL
|
|
#define
|
_DAC_OPA0MUX_RESSEL_RES4
0x00000004UL
|
|
#define
|
_DAC_OPA0MUX_RESSEL_RES5
0x00000005UL
|
|
#define
|
_DAC_OPA0MUX_RESSEL_RES6
0x00000006UL
|
|
#define
|
_DAC_OPA0MUX_RESSEL_RES7
0x00000007UL
|
|
#define
|
_DAC_OPA0MUX_RESSEL_SHIFT
28
|
|
#define
|
_DAC_OPA1MUX_MASK
0x74C7F737UL
|
|
#define
|
_DAC_OPA1MUX_NEGSEL_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_NEGSEL_DISABLE
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_NEGSEL_MASK
0x30UL
|
|
#define
|
_DAC_OPA1MUX_NEGSEL_NEGPAD
0x00000003UL
|
|
#define
|
_DAC_OPA1MUX_NEGSEL_OPATAP
0x00000002UL
|
|
#define
|
_DAC_OPA1MUX_NEGSEL_SHIFT
4
|
|
#define
|
_DAC_OPA1MUX_NEGSEL_UG
0x00000001UL
|
|
#define
|
_DAC_OPA1MUX_NEXTOUT_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_NEXTOUT_MASK
0x4000000UL
|
|
#define
|
_DAC_OPA1MUX_NEXTOUT_SHIFT
26
|
|
#define
|
_DAC_OPA1MUX_NPEN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_NPEN_MASK
0x2000UL
|
|
#define
|
_DAC_OPA1MUX_NPEN_SHIFT
13
|
|
#define
|
_DAC_OPA1MUX_OUTMODE_ALL
0x00000003UL
|
|
#define
|
_DAC_OPA1MUX_OUTMODE_ALT
0x00000002UL
|
|
#define
|
_DAC_OPA1MUX_OUTMODE_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_OUTMODE_DISABLE
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_OUTMODE_MAIN
0x00000001UL
|
|
#define
|
_DAC_OPA1MUX_OUTMODE_MASK
0xC00000UL
|
|
#define
|
_DAC_OPA1MUX_OUTMODE_SHIFT
22
|
|
#define
|
_DAC_OPA1MUX_OUTPEN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_OUTPEN_MASK
0x7C000UL
|
|
#define
|
_DAC_OPA1MUX_OUTPEN_OUT0
0x00000001UL
|
|
#define
|
_DAC_OPA1MUX_OUTPEN_OUT1
0x00000002UL
|
|
#define
|
_DAC_OPA1MUX_OUTPEN_OUT2
0x00000004UL
|
|
#define
|
_DAC_OPA1MUX_OUTPEN_OUT3
0x00000008UL
|
|
#define
|
_DAC_OPA1MUX_OUTPEN_OUT4
0x00000010UL
|
|
#define
|
_DAC_OPA1MUX_OUTPEN_SHIFT
14
|
|
#define
|
_DAC_OPA1MUX_POSSEL_DAC
0x00000001UL
|
|
#define
|
_DAC_OPA1MUX_POSSEL_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_POSSEL_DISABLE
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_POSSEL_MASK
0x7UL
|
|
#define
|
_DAC_OPA1MUX_POSSEL_OPA0INP
0x00000003UL
|
|
#define
|
_DAC_OPA1MUX_POSSEL_OPATAP
0x00000004UL
|
|
#define
|
_DAC_OPA1MUX_POSSEL_POSPAD
0x00000002UL
|
|
#define
|
_DAC_OPA1MUX_POSSEL_SHIFT
0
|
|
#define
|
_DAC_OPA1MUX_PPEN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_PPEN_MASK
0x1000UL
|
|
#define
|
_DAC_OPA1MUX_PPEN_SHIFT
12
|
|
#define
|
_DAC_OPA1MUX_RESETVALUE
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_RESINMUX_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_RESINMUX_DISABLE
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_RESINMUX_MASK
0x700UL
|
|
#define
|
_DAC_OPA1MUX_RESINMUX_NEGPAD
0x00000002UL
|
|
#define
|
_DAC_OPA1MUX_RESINMUX_OPA0INP
0x00000001UL
|
|
#define
|
_DAC_OPA1MUX_RESINMUX_POSPAD
0x00000003UL
|
|
#define
|
_DAC_OPA1MUX_RESINMUX_SHIFT
8
|
|
#define
|
_DAC_OPA1MUX_RESINMUX_VSS
0x00000004UL
|
|
#define
|
_DAC_OPA1MUX_RESSEL_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_RESSEL_MASK
0x70000000UL
|
|
#define
|
_DAC_OPA1MUX_RESSEL_RES0
0x00000000UL
|
|
#define
|
_DAC_OPA1MUX_RESSEL_RES1
0x00000001UL
|
|
#define
|
_DAC_OPA1MUX_RESSEL_RES2
0x00000002UL
|
|
#define
|
_DAC_OPA1MUX_RESSEL_RES3
0x00000003UL
|
|
#define
|
_DAC_OPA1MUX_RESSEL_RES4
0x00000004UL
|
|
#define
|
_DAC_OPA1MUX_RESSEL_RES5
0x00000005UL
|
|
#define
|
_DAC_OPA1MUX_RESSEL_RES6
0x00000006UL
|
|
#define
|
_DAC_OPA1MUX_RESSEL_RES7
0x00000007UL
|
|
#define
|
_DAC_OPA1MUX_RESSEL_SHIFT
28
|
|
#define
|
_DAC_OPA2MUX_MASK
0x7440F737UL
|
|
#define
|
_DAC_OPA2MUX_NEGSEL_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_NEGSEL_DISABLE
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_NEGSEL_MASK
0x30UL
|
|
#define
|
_DAC_OPA2MUX_NEGSEL_NEGPAD
0x00000003UL
|
|
#define
|
_DAC_OPA2MUX_NEGSEL_OPATAP
0x00000002UL
|
|
#define
|
_DAC_OPA2MUX_NEGSEL_SHIFT
4
|
|
#define
|
_DAC_OPA2MUX_NEGSEL_UG
0x00000001UL
|
|
#define
|
_DAC_OPA2MUX_NEXTOUT_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_NEXTOUT_MASK
0x4000000UL
|
|
#define
|
_DAC_OPA2MUX_NEXTOUT_SHIFT
26
|
|
#define
|
_DAC_OPA2MUX_NPEN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_NPEN_MASK
0x2000UL
|
|
#define
|
_DAC_OPA2MUX_NPEN_SHIFT
13
|
|
#define
|
_DAC_OPA2MUX_OUTMODE_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_OUTMODE_MASK
0x400000UL
|
|
#define
|
_DAC_OPA2MUX_OUTMODE_SHIFT
22
|
|
#define
|
_DAC_OPA2MUX_OUTPEN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_OUTPEN_MASK
0xC000UL
|
|
#define
|
_DAC_OPA2MUX_OUTPEN_OUT0
0x00000001UL
|
|
#define
|
_DAC_OPA2MUX_OUTPEN_OUT1
0x00000002UL
|
|
#define
|
_DAC_OPA2MUX_OUTPEN_SHIFT
14
|
|
#define
|
_DAC_OPA2MUX_POSSEL_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_POSSEL_DISABLE
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_POSSEL_MASK
0x7UL
|
|
#define
|
_DAC_OPA2MUX_POSSEL_OPA1INP
0x00000003UL
|
|
#define
|
_DAC_OPA2MUX_POSSEL_OPATAP
0x00000004UL
|
|
#define
|
_DAC_OPA2MUX_POSSEL_POSPAD
0x00000002UL
|
|
#define
|
_DAC_OPA2MUX_POSSEL_SHIFT
0
|
|
#define
|
_DAC_OPA2MUX_PPEN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_PPEN_MASK
0x1000UL
|
|
#define
|
_DAC_OPA2MUX_PPEN_SHIFT
12
|
|
#define
|
_DAC_OPA2MUX_RESETVALUE
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_RESINMUX_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_RESINMUX_DISABLE
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_RESINMUX_MASK
0x700UL
|
|
#define
|
_DAC_OPA2MUX_RESINMUX_NEGPAD
0x00000002UL
|
|
#define
|
_DAC_OPA2MUX_RESINMUX_OPA1INP
0x00000001UL
|
|
#define
|
_DAC_OPA2MUX_RESINMUX_POSPAD
0x00000003UL
|
|
#define
|
_DAC_OPA2MUX_RESINMUX_SHIFT
8
|
|
#define
|
_DAC_OPA2MUX_RESINMUX_VSS
0x00000004UL
|
|
#define
|
_DAC_OPA2MUX_RESSEL_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_RESSEL_MASK
0x70000000UL
|
|
#define
|
_DAC_OPA2MUX_RESSEL_RES0
0x00000000UL
|
|
#define
|
_DAC_OPA2MUX_RESSEL_RES1
0x00000001UL
|
|
#define
|
_DAC_OPA2MUX_RESSEL_RES2
0x00000002UL
|
|
#define
|
_DAC_OPA2MUX_RESSEL_RES3
0x00000003UL
|
|
#define
|
_DAC_OPA2MUX_RESSEL_RES4
0x00000004UL
|
|
#define
|
_DAC_OPA2MUX_RESSEL_RES5
0x00000005UL
|
|
#define
|
_DAC_OPA2MUX_RESSEL_RES6
0x00000006UL
|
|
#define
|
_DAC_OPA2MUX_RESSEL_RES7
0x00000007UL
|
|
#define
|
_DAC_OPA2MUX_RESSEL_SHIFT
28
|
|
#define
|
_DAC_OPACTRL_MASK
0x01C3F1C7UL
|
|
#define
|
_DAC_OPACTRL_OPA0EN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPACTRL_OPA0EN_MASK
0x1UL
|
|
#define
|
_DAC_OPACTRL_OPA0EN_SHIFT
0
|
|
#define
|
_DAC_OPACTRL_OPA0HCMDIS_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPACTRL_OPA0HCMDIS_MASK
0x40UL
|
|
#define
|
_DAC_OPACTRL_OPA0HCMDIS_SHIFT
6
|
|
#define
|
_DAC_OPACTRL_OPA0LPFDIS_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPACTRL_OPA0LPFDIS_MASK
0x3000UL
|
|
#define
|
_DAC_OPACTRL_OPA0LPFDIS_NLPFDIS
0x00000002UL
|
|
#define
|
_DAC_OPACTRL_OPA0LPFDIS_PLPFDIS
0x00000001UL
|
|
#define
|
_DAC_OPACTRL_OPA0LPFDIS_SHIFT
12
|
|
#define
|
_DAC_OPACTRL_OPA0SHORT_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPACTRL_OPA0SHORT_MASK
0x400000UL
|
|
#define
|
_DAC_OPACTRL_OPA0SHORT_SHIFT
22
|
|
#define
|
_DAC_OPACTRL_OPA1EN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPACTRL_OPA1EN_MASK
0x2UL
|
|
#define
|
_DAC_OPACTRL_OPA1EN_SHIFT
1
|
|
#define
|
_DAC_OPACTRL_OPA1HCMDIS_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPACTRL_OPA1HCMDIS_MASK
0x80UL
|
|
#define
|
_DAC_OPACTRL_OPA1HCMDIS_SHIFT
7
|
|
#define
|
_DAC_OPACTRL_OPA1LPFDIS_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPACTRL_OPA1LPFDIS_MASK
0xC000UL
|
|
#define
|
_DAC_OPACTRL_OPA1LPFDIS_NLPFDIS
0x00000002UL
|
|
#define
|
_DAC_OPACTRL_OPA1LPFDIS_PLPFDIS
0x00000001UL
|
|
#define
|
_DAC_OPACTRL_OPA1LPFDIS_SHIFT
14
|
|
#define
|
_DAC_OPACTRL_OPA1SHORT_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPACTRL_OPA1SHORT_MASK
0x800000UL
|
|
#define
|
_DAC_OPACTRL_OPA1SHORT_SHIFT
23
|
|
#define
|
_DAC_OPACTRL_OPA2EN_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPACTRL_OPA2EN_MASK
0x4UL
|
|
#define
|
_DAC_OPACTRL_OPA2EN_SHIFT
2
|
|
#define
|
_DAC_OPACTRL_OPA2HCMDIS_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPACTRL_OPA2HCMDIS_MASK
0x100UL
|
|
#define
|
_DAC_OPACTRL_OPA2HCMDIS_SHIFT
8
|
|
#define
|
_DAC_OPACTRL_OPA2LPFDIS_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPACTRL_OPA2LPFDIS_MASK
0x30000UL
|
|
#define
|
_DAC_OPACTRL_OPA2LPFDIS_NLPFDIS
0x00000002UL
|
|
#define
|
_DAC_OPACTRL_OPA2LPFDIS_PLPFDIS
0x00000001UL
|
|
#define
|
_DAC_OPACTRL_OPA2LPFDIS_SHIFT
16
|
|
#define
|
_DAC_OPACTRL_OPA2SHORT_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_OPACTRL_OPA2SHORT_MASK
0x1000000UL
|
|
#define
|
_DAC_OPACTRL_OPA2SHORT_SHIFT
24
|
|
#define
|
_DAC_OPACTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_DAC_OPAOFFSET_MASK
0x0000003FUL
|
|
#define
|
_DAC_OPAOFFSET_OPA2OFFSET_DEFAULT
0x00000020UL
|
|
#define
|
_DAC_OPAOFFSET_OPA2OFFSET_MASK
0x3FUL
|
|
#define
|
_DAC_OPAOFFSET_OPA2OFFSET_SHIFT
0
|
|
#define
|
_DAC_OPAOFFSET_RESETVALUE
0x00000020UL
|
|
#define
|
_DAC_STATUS_CH0DV_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_STATUS_CH0DV_MASK
0x1UL
|
|
#define
|
_DAC_STATUS_CH0DV_SHIFT
0
|
|
#define
|
_DAC_STATUS_CH1DV_DEFAULT
0x00000000UL
|
|
#define
|
_DAC_STATUS_CH1DV_MASK
0x2UL
|
|
#define
|
_DAC_STATUS_CH1DV_SHIFT
1
|
|
#define
|
_DAC_STATUS_MASK
0x00000003UL
|
|
#define
|
_DAC_STATUS_RESETVALUE
0x00000000UL
|
|
#define
|
DAC_BIASPROG_BIASPROG_DEFAULT
(
_DAC_BIASPROG_BIASPROG_DEFAULT
<< 0)
|
|
#define
|
DAC_BIASPROG_HALFBIAS
(0x1UL << 6)
|
|
#define
|
DAC_BIASPROG_HALFBIAS_DEFAULT
(
_DAC_BIASPROG_HALFBIAS_DEFAULT
<< 6)
|
|
#define
|
DAC_BIASPROG_OPA2BIASPROG_DEFAULT
(
_DAC_BIASPROG_OPA2BIASPROG_DEFAULT
<< 8)
|
|
#define
|
DAC_BIASPROG_OPA2HALFBIAS
(0x1UL << 14)
|
|
#define
|
DAC_BIASPROG_OPA2HALFBIAS_DEFAULT
(
_DAC_BIASPROG_OPA2HALFBIAS_DEFAULT
<< 14)
|
|
#define
|
DAC_CAL_CH0OFFSET_DEFAULT
(
_DAC_CAL_CH0OFFSET_DEFAULT
<< 0)
|
|
#define
|
DAC_CAL_CH1OFFSET_DEFAULT
(
_DAC_CAL_CH1OFFSET_DEFAULT
<< 8)
|
|
#define
|
DAC_CAL_GAIN_DEFAULT
(
_DAC_CAL_GAIN_DEFAULT
<< 16)
|
|
#define
|
DAC_CH0CTRL_EN
(0x1UL << 0)
|
|
#define
|
DAC_CH0CTRL_EN_DEFAULT
(
_DAC_CH0CTRL_EN_DEFAULT
<< 0)
|
|
#define
|
DAC_CH0CTRL_PRSEN
(0x1UL << 2)
|
|
#define
|
DAC_CH0CTRL_PRSEN_DEFAULT
(
_DAC_CH0CTRL_PRSEN_DEFAULT
<< 2)
|
|
#define
|
DAC_CH0CTRL_PRSSEL_DEFAULT
(
_DAC_CH0CTRL_PRSSEL_DEFAULT
<< 4)
|
|
#define
|
DAC_CH0CTRL_PRSSEL_PRSCH0
(
_DAC_CH0CTRL_PRSSEL_PRSCH0
<< 4)
|
|
#define
|
DAC_CH0CTRL_PRSSEL_PRSCH1
(
_DAC_CH0CTRL_PRSSEL_PRSCH1
<< 4)
|
|
#define
|
DAC_CH0CTRL_PRSSEL_PRSCH10
(
_DAC_CH0CTRL_PRSSEL_PRSCH10
<< 4)
|
|
#define
|
DAC_CH0CTRL_PRSSEL_PRSCH11
(
_DAC_CH0CTRL_PRSSEL_PRSCH11
<< 4)
|
|
#define
|
DAC_CH0CTRL_PRSSEL_PRSCH2
(
_DAC_CH0CTRL_PRSSEL_PRSCH2
<< 4)
|
|
#define
|
DAC_CH0CTRL_PRSSEL_PRSCH3
(
_DAC_CH0CTRL_PRSSEL_PRSCH3
<< 4)
|
|
#define
|
DAC_CH0CTRL_PRSSEL_PRSCH4
(
_DAC_CH0CTRL_PRSSEL_PRSCH4
<< 4)
|
|
#define
|
DAC_CH0CTRL_PRSSEL_PRSCH5
(
_DAC_CH0CTRL_PRSSEL_PRSCH5
<< 4)
|
|
#define
|
DAC_CH0CTRL_PRSSEL_PRSCH6
(
_DAC_CH0CTRL_PRSSEL_PRSCH6
<< 4)
|
|
#define
|
DAC_CH0CTRL_PRSSEL_PRSCH7
(
_DAC_CH0CTRL_PRSSEL_PRSCH7
|