EZR32WG_DMA_BitFieldsDevices

Macros

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL
#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL
#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0
#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL
#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL
#define _DMA_CH_CTRL_MASK 0x003F000FUL
#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL
#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL
#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL
#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL
#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL
#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_SHIFT 0
#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL
#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL
#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL
#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL
#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL
#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL
#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL
#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL
#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_UART0TXBL 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 0x00000002UL
#define _DMA_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_UART1TXBL 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_UART1TXEMPTY 0x00000002UL
#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL
#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL
#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL
#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL
#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL
#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL
#define _DMA_CH_CTRL_SIGSEL_USARTRF0RXDATAV 0x00000000UL
#define _DMA_CH_CTRL_SIGSEL_USARTRF0TXBL 0x00000001UL
#define _DMA_CH_CTRL_SIGSEL_USARTRF0TXEMPTY 0x00000002UL
#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL
#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL
#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL
#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL
#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL
#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL
#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL
#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL
#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL
#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL
#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL
#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16
#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL
#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL
#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL
#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL
#define _DMA_CH_CTRL_SOURCESEL_UART0 0x0000002CUL
#define _DMA_CH_CTRL_SOURCESEL_UART1 0x0000002DUL
#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL
#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL
#define _DMA_CH_CTRL_SOURCESEL_USARTRF0 0x0000000CUL
#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL
#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL
#define _DMA_CHALTC_CH0ALTC_SHIFT 0
#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL
#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL
#define _DMA_CHALTC_CH10ALTC_SHIFT 10
#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL
#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL
#define _DMA_CHALTC_CH11ALTC_SHIFT 11
#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL
#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL
#define _DMA_CHALTC_CH1ALTC_SHIFT 1
#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL
#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL
#define _DMA_CHALTC_CH2ALTC_SHIFT 2
#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL
#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL
#define _DMA_CHALTC_CH3ALTC_SHIFT 3
#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL
#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL
#define _DMA_CHALTC_CH4ALTC_SHIFT 4
#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL
#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL
#define _DMA_CHALTC_CH5ALTC_SHIFT 5
#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL
#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL
#define _DMA_CHALTC_CH6ALTC_SHIFT 6
#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL
#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL
#define _DMA_CHALTC_CH7ALTC_SHIFT 7
#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL
#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL
#define _DMA_CHALTC_CH8ALTC_SHIFT 8
#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL
#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL
#define _DMA_CHALTC_CH9ALTC_SHIFT 9
#define _DMA_CHALTC_MASK 0x00000FFFUL
#define _DMA_CHALTC_RESETVALUE 0x00000000UL
#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL
#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL
#define _DMA_CHALTS_CH0ALTS_SHIFT 0
#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL
#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL
#define _DMA_CHALTS_CH10ALTS_SHIFT 10
#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL
#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL
#define _DMA_CHALTS_CH11ALTS_SHIFT 11
#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL
#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL
#define _DMA_CHALTS_CH1ALTS_SHIFT 1
#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL
#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL
#define _DMA_CHALTS_CH2ALTS_SHIFT 2
#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL
#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL
#define _DMA_CHALTS_CH3ALTS_SHIFT 3
#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL
#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL
#define _DMA_CHALTS_CH4ALTS_SHIFT 4
#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL
#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL
#define _DMA_CHALTS_CH5ALTS_SHIFT 5
#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL
#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL
#define _DMA_CHALTS_CH6ALTS_SHIFT 6
#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL
#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL
#define _DMA_CHALTS_CH7ALTS_SHIFT 7
#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL
#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL
#define _DMA_CHALTS_CH8ALTS_SHIFT 8
#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL
#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL
#define _DMA_CHALTS_CH9ALTS_SHIFT 9
#define _DMA_CHALTS_MASK 0x00000FFFUL
#define _DMA_CHALTS_RESETVALUE 0x00000000UL
#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL
#define _DMA_CHENC_CH0ENC_MASK 0x1UL
#define _DMA_CHENC_CH0ENC_SHIFT 0
#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL
#define _DMA_CHENC_CH10ENC_MASK 0x400UL
#define _DMA_CHENC_CH10ENC_SHIFT 10
#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL
#define _DMA_CHENC_CH11ENC_MASK 0x800UL
#define _DMA_CHENC_CH11ENC_SHIFT 11
#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL
#define _DMA_CHENC_CH1ENC_MASK 0x2UL
#define _DMA_CHENC_CH1ENC_SHIFT 1
#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL
#define _DMA_CHENC_CH2ENC_MASK 0x4UL
#define _DMA_CHENC_CH2ENC_SHIFT 2
#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL
#define _DMA_CHENC_CH3ENC_MASK 0x8UL
#define _DMA_CHENC_CH3ENC_SHIFT 3
#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL
#define _DMA_CHENC_CH4ENC_MASK 0x10UL
#define _DMA_CHENC_CH4ENC_SHIFT 4
#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL
#define _DMA_CHENC_CH5ENC_MASK 0x20UL
#define _DMA_CHENC_CH5ENC_SHIFT 5
#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL
#define _DMA_CHENC_CH6ENC_MASK 0x40UL
#define _DMA_CHENC_CH6ENC_SHIFT 6
#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL
#define _DMA_CHENC_CH7ENC_MASK 0x80UL
#define _DMA_CHENC_CH7ENC_SHIFT 7
#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL
#define _DMA_CHENC_CH8ENC_MASK 0x100UL
#define _DMA_CHENC_CH8ENC_SHIFT 8
#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL
#define _DMA_CHENC_CH9ENC_MASK 0x200UL
#define _DMA_CHENC_CH9ENC_SHIFT 9
#define _DMA_CHENC_MASK 0x00000FFFUL
#define _DMA_CHENC_RESETVALUE 0x00000000UL
#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL
#define _DMA_CHENS_CH0ENS_MASK 0x1UL
#define _DMA_CHENS_CH0ENS_SHIFT 0
#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL
#define _DMA_CHENS_CH10ENS_MASK 0x400UL
#define _DMA_CHENS_CH10ENS_SHIFT 10
#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL
#define _DMA_CHENS_CH11ENS_MASK 0x800UL
#define _DMA_CHENS_CH11ENS_SHIFT 11
#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL
#define _DMA_CHENS_CH1ENS_MASK 0x2UL
#define _DMA_CHENS_CH1ENS_SHIFT 1
#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL
#define _DMA_CHENS_CH2ENS_MASK 0x4UL
#define _DMA_CHENS_CH2ENS_SHIFT 2
#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL
#define _DMA_CHENS_CH3ENS_MASK 0x8UL
#define _DMA_CHENS_CH3ENS_SHIFT 3
#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL
#define _DMA_CHENS_CH4ENS_MASK 0x10UL
#define _DMA_CHENS_CH4ENS_SHIFT 4
#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL
#define _DMA_CHENS_CH5ENS_MASK 0x20UL
#define _DMA_CHENS_CH5ENS_SHIFT 5
#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL
#define _DMA_CHENS_CH6ENS_MASK 0x40UL
#define _DMA_CHENS_CH6ENS_SHIFT 6
#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL
#define _DMA_CHENS_CH7ENS_MASK 0x80UL
#define _DMA_CHENS_CH7ENS_SHIFT 7
#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL
#define _DMA_CHENS_CH8ENS_MASK 0x100UL
#define _DMA_CHENS_CH8ENS_SHIFT 8
#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL
#define _DMA_CHENS_CH9ENS_MASK 0x200UL
#define _DMA_CHENS_CH9ENS_SHIFT 9
#define _DMA_CHENS_MASK 0x00000FFFUL
#define _DMA_CHENS_RESETVALUE 0x00000000UL
#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL
#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL
#define _DMA_CHPRIC_CH0PRIC_SHIFT 0
#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL
#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL
#define _DMA_CHPRIC_CH10PRIC_SHIFT 10
#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL
#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL
#define _DMA_CHPRIC_CH11PRIC_SHIFT 11
#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL
#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL
#define _DMA_CHPRIC_CH1PRIC_SHIFT 1
#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL
#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL
#define _DMA_CHPRIC_CH2PRIC_SHIFT 2
#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL
#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL
#define _DMA_CHPRIC_CH3PRIC_SHIFT 3
#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL
#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL
#define _DMA_CHPRIC_CH4PRIC_SHIFT 4
#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL
#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL
#define _DMA_CHPRIC_CH5PRIC_SHIFT 5
#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL
#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL
#define _DMA_CHPRIC_CH6PRIC_SHIFT 6
#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL
#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL
#define _DMA_CHPRIC_CH7PRIC_SHIFT 7
#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL
#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL
#define _DMA_CHPRIC_CH8PRIC_SHIFT 8
#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL
#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL
#define _DMA_CHPRIC_CH9PRIC_SHIFT 9
#define _DMA_CHPRIC_MASK 0x00000FFFUL
#define _DMA_CHPRIC_RESETVALUE 0x00000000UL
#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL
#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL
#define _DMA_CHPRIS_CH0PRIS_SHIFT 0
#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL
#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL
#define _DMA_CHPRIS_CH10PRIS_SHIFT 10
#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL
#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL
#define _DMA_CHPRIS_CH11PRIS_SHIFT 11
#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL
#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL
#define _DMA_CHPRIS_CH1PRIS_SHIFT 1
#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL
#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL
#define _DMA_CHPRIS_CH2PRIS_SHIFT 2
#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL
#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL
#define _DMA_CHPRIS_CH3PRIS_SHIFT 3
#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL
#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL
#define _DMA_CHPRIS_CH4PRIS_SHIFT 4
#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL
#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL
#define _DMA_CHPRIS_CH5PRIS_SHIFT 5
#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL
#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL
#define _DMA_CHPRIS_CH6PRIS_SHIFT 6
#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL
#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL
#define _DMA_CHPRIS_CH7PRIS_SHIFT 7
#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL
#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL
#define _DMA_CHPRIS_CH8PRIS_SHIFT 8
#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL
#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL
#define _DMA_CHPRIS_CH9PRIS_SHIFT 9
#define _DMA_CHPRIS_MASK 0x00000FFFUL
#define _DMA_CHPRIS_RESETVALUE 0x00000000UL
#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL
#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0
#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL
#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10
#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL
#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11
#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL
#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1
#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL
#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2
#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL
#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3
#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL
#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4
#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL
#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5
#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL
#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6
#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL
#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7
#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL
#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8
#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL
#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9
#define _DMA_CHREQMASKC_MASK 0x00000FFFUL
#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL
#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL
#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0
#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL
#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10
#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL
#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11
#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL
#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1
#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL
#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2
#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL
#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3
#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL
#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4
#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL
#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5
#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL
#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6
#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL
#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7
#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL
#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8
#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL
#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL
#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9
#define _DMA_CHREQMASKS_MASK 0x00000FFFUL
#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL
#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL
#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0
#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL
#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10
#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL
#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11
#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL
#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1
#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL
#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2
#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL
#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3
#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL
#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4
#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL
#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5
#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL
#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6
#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL
#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7
#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL
#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8
#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL
#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9
#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL
#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL
#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL
#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0
#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL
#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10
#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL
#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11
#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL
#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1
#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL
#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2
#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL
#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3
#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL
#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4
#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL
#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL
#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5
#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL