EZR32WG330F256R69Devices

Modules

EZR32WG330F256R69 Alternate Function
EZR32WG330F256R69 Bit Fields
EZR32WG330F256R69 Core
Processor and Core Peripheral Section.
EZR32WG330F256R69 Part
EZR32WG330F256R69 Peripheral Declarations
EZR32WG330F256R69 Peripheral Memory Map
EZR32WG330F256R69 Peripheral TypeDefs
Device Specific Peripheral Register Structures.

Macros

#define SET_BIT_FIELD (REG, MASK, VALUE, OFFSET)   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Set the value of a bit field within a register.

Typedefs

typedef enum IRQn IRQn_Type

Enumerations

enum IRQn {
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
DMA_IRQn = 0,
GPIO_EVEN_IRQn = 1,
TIMER0_IRQn = 2,
USARTRF0_RX_IRQn = 3,
USARTRF0_TX_IRQn = 4,
USB_IRQn = 5,
ACMP0_IRQn = 6,
ADC0_IRQn = 7,
DAC0_IRQn = 8,
I2C0_IRQn = 9,
I2C1_IRQn = 10,
GPIO_ODD_IRQn = 11,
TIMER1_IRQn = 12,
TIMER2_IRQn = 13,
TIMER3_IRQn = 14,
USART1_RX_IRQn = 15,
USART1_TX_IRQn = 16,
LESENSE_IRQn = 17,
USART2_RX_IRQn = 18,
USART2_TX_IRQn = 19,
UART0_RX_IRQn = 20,
UART0_TX_IRQn = 21,
UART1_RX_IRQn = 22,
UART1_TX_IRQn = 23,
LEUART0_IRQn = 24,
LEUART1_IRQn = 25,
LETIMER0_IRQn = 26,
PCNT0_IRQn = 27,
PCNT1_IRQn = 28,
PCNT2_IRQn = 29,
RTC_IRQn = 30,
BURTC_IRQn = 31,
CMU_IRQn = 32,
VCMP_IRQn = 33,
MSC_IRQn = 35,
AES_IRQn = 36,
EMU_IRQn = 38,
FPUEH_IRQn = 39
}

Macro Definition Documentation

#define SET_BIT_FIELD ( REG,
MASK,
VALUE,
OFFSET
) REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));

Set the value of a bit field within a register.

Parameters
REG The register to update
MASK The mask for the bit field to update
VALUE The value to write to the bit field
OFFSET The number of bits that the field is offset within the register. 0 (zero) means LSB.

Definition at line 498 of file ezr32wg330f256r69.h .

Typedef Documentation

typedef enum IRQn IRQn_Type

Interrupt Number Definition

Enumeration Type Documentation

enum IRQn

Interrupt Number Definition

Enumerator
NonMaskableInt_IRQn

-14 Cortex-M4 Non Maskable Interrupt

HardFault_IRQn

-13 Cortex-M4 Hard Fault Interrupt

MemoryManagement_IRQn

-12 Cortex-M4 Memory Management Interrupt

BusFault_IRQn

-11 Cortex-M4 Bus Fault Interrupt

UsageFault_IRQn

-10 Cortex-M4 Usage Fault Interrupt

SVCall_IRQn

-5 Cortex-M4 SV Call Interrupt

DebugMonitor_IRQn

-4 Cortex-M4 Debug Monitor Interrupt

PendSV_IRQn

-2 Cortex-M4 Pend SV Interrupt

SysTick_IRQn

-1 Cortex-M4 System Tick Interrupt

DMA_IRQn

0 EZR32 DMA Interrupt

GPIO_EVEN_IRQn

1 EZR32 GPIO_EVEN Interrupt

TIMER0_IRQn

2 EZR32 TIMER0 Interrupt

USARTRF0_RX_IRQn

3 EZR32 USARTRF0_RX Interrupt

USARTRF0_TX_IRQn

4 EZR32 USARTRF0_TX Interrupt

USB_IRQn

5 EZR32 USB Interrupt

ACMP0_IRQn

6 EZR32 ACMP0 Interrupt

ADC0_IRQn

7 EZR32 ADC0 Interrupt

DAC0_IRQn

8 EZR32 DAC0 Interrupt

I2C0_IRQn

9 EZR32 I2C0 Interrupt

I2C1_IRQn

10 EZR32 I2C1 Interrupt

GPIO_ODD_IRQn

11 EZR32 GPIO_ODD Interrupt

TIMER1_IRQn

12 EZR32 TIMER1 Interrupt

TIMER2_IRQn

13 EZR32 TIMER2 Interrupt

TIMER3_IRQn

14 EZR32 TIMER3 Interrupt

USART1_RX_IRQn

15 EZR32 USART1_RX Interrupt

USART1_TX_IRQn

16 EZR32 USART1_TX Interrupt

LESENSE_IRQn

17 EZR32 LESENSE Interrupt

USART2_RX_IRQn

18 EZR32 USART2_RX Interrupt

USART2_TX_IRQn

19 EZR32 USART2_TX Interrupt

UART0_RX_IRQn

20 EZR32 UART0_RX Interrupt

UART0_TX_IRQn

21 EZR32 UART0_TX Interrupt

UART1_RX_IRQn

22 EZR32 UART1_RX Interrupt

UART1_TX_IRQn

23 EZR32 UART1_TX Interrupt

LEUART0_IRQn

24 EZR32 LEUART0 Interrupt

LEUART1_IRQn

25 EZR32 LEUART1 Interrupt

LETIMER0_IRQn

26 EZR32 LETIMER0 Interrupt

PCNT0_IRQn

27 EZR32 PCNT0 Interrupt

PCNT1_IRQn

28 EZR32 PCNT1 Interrupt

PCNT2_IRQn

29 EZR32 PCNT2 Interrupt

RTC_IRQn

30 EZR32 RTC Interrupt

BURTC_IRQn

31 EZR32 BURTC Interrupt

CMU_IRQn

32 EZR32 CMU Interrupt

VCMP_IRQn

33 EZR32 VCMP Interrupt

MSC_IRQn

35 EZR32 MSC Interrupt

AES_IRQn

36 EZR32 AES Interrupt

EMU_IRQn

38 EZR32 EMU Interrupt

FPUEH_IRQn

39 EZR32 FPUEH Interrupt

Definition at line 57 of file ezr32wg330f256r69.h .