Device Power Modes


This document provides details on the different WF200 device power modes which can be used by the host to optimize the power efficiency of its application. To optimize even further the power consumption, the WF(M)200 can make use of its different Wi-Fi power modes (i.e., active, Fast-PS, PS-Poll and U-APSD). The Wi-Fi power modes are documented here.

Device Power Saving

First, a good RF design is needed to achieve a good link with other Wi-Fi devices, leading to less retries and thus reduced power consumption during active phases (Tx and Rx) using the 38 MHz clock.

See UG382 (WF200) and UG395 (WFM200) for details on RF-related hardware design.

WF(M)200 Device Power Save Modes

The best power saving mode an application can reach depends on its hardware. We consider four device power modes:

Device Power Mode32 kHz LP_CLKHF_CLK/XTAL_SHAREDClock UsedXTal OscillatorPower Savings
Snoozeno-38 MHzOnsub-optimal
Sleep with XOyesyes32 kHzOntrade-off
Sleepyesno32 kHzOffoptimal while maintaining context
Shutdown----optimal (requires firmware download to restart)

'-' means that the presence or absence of the hardware does not matter for the power mode.

Low-Speed Clock

When in power save mode, using a slower clock instead of the 38 MHz clock is more energy efficient, since silicon power consumption is a direct relation between the number of clock cycles per second and the number of active gates.

A Low Power Clock (LP_CLK) running at 32 KHz can be provided to WF(M)200. This clock is used in Sleep with XO and Sleep modes instead of the 38 MHz clock. The LP_CLK frequency drift within 1 second should be lower than +/-100 ppm. The sleep current reaches 22 µA with LP_CLK, as opposed to 1.2 mA with the normal clock (38.4 MHz), as detailed in the datasheet.

To enable the use of a low power clock, the hardware design has to provide a 32.768 KHz on LP_CLK. The LP_CLK is detected automatically after reset, so no configuration is required.

38 MHz Clock

As described above, the WF(M)200 can save power using a 32 KHz clock while in Sleep mode. In most cases, the crystal oscillator driving the 38 MHz clock is switched off, thus saving some power.

Depending on the hardware design it may be necessary to keep the 38 MHz clock active if it's fed to another device. In this situation, the WF(M)200 will still run on the 32 KHz clock, but the crystal oscillator will be kept on to maintain the 38 MHz clock. Power savings won't be optimum. This case is the Sleep with XO mode. To share the 38 MHz clock:

The WFM200 has no 38 MHz sharing capability, so HF_CLK/XTAL_SHARED: off; is mandatory with WFM200.


GPIO/WUP is an output for the host and an input for the WF(M)200.

The GPIO/WUP (wake-up) pin allows the Host to enable or disable device power save modes in the WF(M)200.

Although the Host indicates to WF(M)200 via GPIO/WUP that it can enter device power save, the WF(M)200 may not be able to do so, depending on Wi-Fi activity. To enable the WUP GPIO, set GPIO_WUP/PIN_MODE: func; in your PDS file.


GPIO/WIRQ is an output for WF(M)200 and an input for the Host. WF(M)200 raises the WIRQ signal when a Wi-Fi message intended for the host is received, indicating that the host needs to retrieve it. If the host is in suspend state it goes back to an active state.

Messages solely intended to maintain the connection to the AP (which can be processed by the firmware) are not sent over the SPI or SDIO bus, so GPIO/WIRQ is not raised in this situation.

To enable the WIRQ GPIO, set GPIO_WIRQ/PIN_MODE: func; in your PDS file.

Enabling Device Power Save


Refer to the FMAC Device Power Save documentation.


With the Low-MAC driver (used with Linux platforms), two conditions must be met to enable Device Power Save:

Additional Power Saving Considerations



Power Supplies

See AN1219: Power Consumption Measurement Setup and Results on WF(M)200 for additional details on power consumption.