PartDevices > EFM32PG12B500F1024GL125
Macros |
|
| #define | __CM4_REV 0x001 |
| #define | _EFM32_PEARL_FAMILY 1 |
| #define | _EFM_DEVICE |
| #define | _SILICON_LABS_32B_PLATFORM 2 |
| #define | _SILICON_LABS_32B_PLATFORM_2 |
| #define | _SILICON_LABS_32B_PLATFORM_2_GEN 2 |
| #define | _SILICON_LABS_32B_PLATFORM_2_GEN_2 |
| #define | _SILICON_LABS_32B_SERIES 1 |
| #define | _SILICON_LABS_32B_SERIES_1 |
| #define | _SILICON_LABS_32B_SERIES_1_CONFIG 2 |
| #define | _SILICON_LABS_32B_SERIES_1_CONFIG_2 |
| #define | _SILICON_LABS_GECKO_INTERNAL_SDID 84 |
| #define | _SILICON_LABS_GECKO_INTERNAL_SDID_84 |
| #define | ACMP_COUNT 2 |
| #define | ACMP_PRESENT |
| #define | ADC_COUNT 1 |
| #define | ADC_PRESENT |
| #define | AFACHAN_MAX 125U |
| #define | AFCHAN_MAX 136U |
| #define | AFCHANLOC_MAX 32U |
| #define | BITBAND_PER_BASE ((uint32_t) 0x42000000UL) |
| #define | BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) |
| #define | BOOTLOADER_COUNT 1 |
| #define | BOOTLOADER_PRESENT |
| #define | CMU_COUNT 1 |
| #define | CMU_PRESENT |
| #define | CRYOTIMER_COUNT 1 |
| #define | CRYOTIMER_PRESENT |
| #define | CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) |
| #define | CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) |
| #define | CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) |
| #define | CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) |
| #define | CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) |
| #define | CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) |
| #define | CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) |
| #define | CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) |
| #define | CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) |
| #define | CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) |
| #define | CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) |
| #define | CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) |
| #define | CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE |
| #define | CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS |
| #define | CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END |
| #define | CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE |
| #define | CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE |
| #define | CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS |
| #define | CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END |
| #define | CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE |
| #define | CRYPTO_COUNT 2 |
| #define | CRYPTO_MEM_BASE CRYPTO0_MEM_BASE |
| #define | CRYPTO_MEM_BITS CRYPTO0_MEM_BITS |
| #define | CRYPTO_MEM_END CRYPTO0_MEM_END |
| #define | CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE |
| #define | CRYPTO_PRESENT |
| #define | CSEN_COUNT 1 |
| #define | CSEN_PRESENT |
| #define | DCDC_COUNT 1 |
| #define | DCDC_PRESENT |
| #define | DMA_CHAN_COUNT 8 |
| #define | EMU_COUNT 1 |
| #define | EMU_PRESENT |
| #define | ETM_COUNT 1 |
| #define | ETM_PRESENT |
| #define | EXT_IRQ_COUNT 51 |
| #define | FLASH_BASE (0x00000000UL) |
| #define | FLASH_MEM_BASE ((uint32_t) 0x00000000UL) |
| #define | FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) |
| #define | FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) |
| #define | FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) |
| #define | FLASH_PAGE_SIZE 2048U |
| #define | FLASH_SIZE (0x00100000UL) |
| #define | FPUEH_COUNT 1 |
| #define | FPUEH_PRESENT |
| #define | GPCRC_COUNT 1 |
| #define | GPCRC_PRESENT |
| #define | GPIO_COUNT 1 |
| #define | GPIO_PRESENT |
| #define | I2C_COUNT 2 |
| #define | I2C_PRESENT |
| #define | IDAC_COUNT 1 |
| #define | IDAC_PRESENT |
| #define | LDMA_COUNT 1 |
| #define | LDMA_PRESENT |
| #define | LESENSE_COUNT 1 |
| #define | LESENSE_PRESENT |
| #define | LETIMER_COUNT 1 |
| #define | LETIMER_PRESENT |
| #define | LEUART_COUNT 1 |
| #define | LEUART_PRESENT |
| #define | MSC_COUNT 1 |
| #define | MSC_PRESENT |
| #define | PART_NUMBER "EFM32PG12B500F1024GL125" |
| #define | PCNT_COUNT 3 |
| #define | PCNT_PRESENT |
| #define | PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) |
| #define | PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) |
| #define | PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) |
| #define | PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) |
| #define | PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) |
| #define | PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) |
| #define | PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) |
| #define | PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) |
| #define | PER_MEM_BASE ((uint32_t) 0x40000000UL) |
| #define | PER_MEM_BITS ((uint32_t) 0x00000014UL) |
| #define | PER_MEM_END ((uint32_t) 0x400EFFFFUL) |
| #define | PER_MEM_SIZE ((uint32_t) 0xF0000UL) |
| #define | PRS_CHAN_COUNT 12 |
| #define | PRS_COUNT 1 |
| #define | PRS_PRESENT |
| #define | RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) |
| #define | RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) |
| #define | RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) |
| #define | RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) |
| #define | RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) |
| #define | RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) |
| #define | RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) |
| #define | RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) |
| #define | RAM1_MEM_BASE ((uint32_t) 0x20020000UL) |
| #define | RAM1_MEM_BITS ((uint32_t) 0x00000011UL) |
| #define | RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) |
| #define | RAM1_MEM_SIZE ((uint32_t) 0x20000UL) |
| #define | RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) |
| #define | RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) |
| #define | RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) |
| #define | RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) |
| #define | RAM2_MEM_BASE ((uint32_t) 0x20040000UL) |
| #define | RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) |
| #define | RAM2_MEM_END ((uint32_t) 0x200407FFUL) |
| #define | RAM2_MEM_SIZE ((uint32_t) 0x800UL) |
| #define | RAM_MEM_BASE ((uint32_t) 0x20000000UL) |
| #define | RAM_MEM_BITS ((uint32_t) 0x00000011UL) |
| #define | RAM_MEM_END ((uint32_t) 0x2001FFFFUL) |
| #define | RAM_MEM_SIZE ((uint32_t) 0x20000UL) |
| #define | RMU_COUNT 1 |
| #define | RMU_PRESENT |
| #define | RTCC_COUNT 1 |
| #define | RTCC_PRESENT |
| #define | SMU_COUNT 1 |
| #define | SMU_PRESENT |
| #define | SRAM_BASE (0x20000000UL) |
| #define | SRAM_SIZE (0x00040000UL) |
| #define | TIMER_COUNT 2 |
| #define | TIMER_PRESENT |
| #define | TRNG_COUNT 1 |
| #define | TRNG_PRESENT |
| #define | USART_COUNT 4 |
| #define | USART_PRESENT |
| #define | VDAC_COUNT 1 |
| #define | VDAC_PRESENT |
| #define | WDOG_COUNT 2 |
| #define | WDOG_PRESENT |
| #define | WTIMER_COUNT 2 |
| #define | WTIMER_PRESENT |
Macro Definition Documentation
| #define __CM4_REV 0x001 |
Cortex-M4 Core revision r0p1
Definition at line
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| #define _EFM32_PEARL_FAMILY 1 |
Part family PEARL Gecko MCU Family
Definition at line
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| #define _EFM_DEVICE |
Silicon Labs EFM-type microcontroller
Definition at line
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| #define _SILICON_LABS_32B_PLATFORM 2 |
- Deprecated:
- Silicon Labs platform name
Definition at line
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| #define _SILICON_LABS_32B_PLATFORM_2 |
- Deprecated:
- Silicon Labs platform name
Definition at line
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| #define _SILICON_LABS_32B_PLATFORM_2_GEN 2 |
- Deprecated:
- Platform 2, generation 2
Definition at line
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| #define _SILICON_LABS_32B_PLATFORM_2_GEN_2 |
- Deprecated:
- Platform 2, generation 2
Definition at line
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| #define _SILICON_LABS_32B_SERIES 1 |
Silicon Labs series number
Definition at line
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| #define _SILICON_LABS_32B_SERIES_1 |
Silicon Labs series number
Definition at line
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| #define _SILICON_LABS_32B_SERIES_1_CONFIG 2 |
Series 1, Configuration 2
Definition at line
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| #define _SILICON_LABS_32B_SERIES_1_CONFIG_2 |
Series 1, Configuration 2
Definition at line
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| #define _SILICON_LABS_GECKO_INTERNAL_SDID 84 |
Silicon Labs internal use only, may change any time
Definition at line
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Referenced by nvm3_halGetDeviceId() .
| #define _SILICON_LABS_GECKO_INTERNAL_SDID_84 |
Silicon Labs internal use only, may change any time
Definition at line
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| #define ACMP_COUNT 2 |
2 ACMPs available
Definition at line
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| #define ACMP_PRESENT |
ACMP is available in this part
Definition at line
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| #define ADC_COUNT 1 |
1 ADCs available
Definition at line
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| #define ADC_PRESENT |
ADC is available in this part
Definition at line
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| #define AFACHAN_MAX 125U |
Analog AF channels
Definition at line
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| #define AFCHAN_MAX 136U |
AF channels connect the different on-chip peripherals with the af-mux
Definition at line
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| #define AFCHANLOC_MAX 32U |
AF channel maximum location number
Definition at line
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Referenced by DBG_SWOEnable() , and GPIO_DbgLocationSet() .
| #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) |
Bit banding area Peripheral Address Space bit-band area
Definition at line
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Referenced by BUS_RegBitRead() , and BUS_RegBitWrite() .
| #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) |
SRAM Address Space bit-band area
Definition at line
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Referenced by BUS_RamBitRead() , and BUS_RamBitWrite() .
| #define BOOTLOADER_COUNT 1 |
1 BOOTLOADER available
Definition at line
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| #define BOOTLOADER_PRESENT |
BOOTLOADER is available in this part
Definition at line
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| #define CMU_COUNT 1 |
1 CMU available
Definition at line
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| #define CMU_PRESENT |
CMU is available in this part
Definition at line
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| #define CRYOTIMER_COUNT 1 |
1 CRYOTIMER available
Definition at line
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| #define CRYOTIMER_PRESENT |
CRYOTIMER is available in this part
Definition at line
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| #define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) |
CRYPTO0_BITCLR base address
Definition at line
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| #define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO0_BITCLR used bits
Definition at line
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| #define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) |
CRYPTO0_BITCLR end address
Definition at line
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| #define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO0_BITCLR available address space
Definition at line
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| #define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) |
CRYPTO0_BITSET base address
Definition at line
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| #define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO0_BITSET used bits
Definition at line
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| #define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) |
CRYPTO0_BITSET end address
Definition at line
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| #define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO0_BITSET available address space
Definition at line
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| #define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) |
CRYPTO0 base address
Definition at line
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| #define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO0 used bits
Definition at line
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| #define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) |
CRYPTO0 end address
Definition at line
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| #define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO0 available address space
Definition at line
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| #define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) |
CRYPTO1_BITCLR base address
Definition at line
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| #define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO1_BITCLR used bits
Definition at line
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| #define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) |
CRYPTO1_BITCLR end address
Definition at line
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| #define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO1_BITCLR available address space
Definition at line
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| #define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) |
CRYPTO1_BITSET base address
Definition at line
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| #define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO1_BITSET used bits
Definition at line
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| #define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) |
CRYPTO1_BITSET end address
Definition at line
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| #define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO1_BITSET available address space
Definition at line
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| #define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) |
CRYPTO1 base address
Definition at line
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| #define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO1 used bits
Definition at line
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| #define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) |
CRYPTO1 end address
Definition at line
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| #define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO1 available address space
Definition at line
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| #define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE |
Alias for CRYPTO0_BITCLR_MEM_BASE
Definition at line
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| #define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS |
Alias for CRYPTO0_BITCLR_MEM_BITS
Definition at line
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| #define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END |
Alias for CRYPTO0_BITCLR_MEM_END
Definition at line
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| #define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE |
Alias for CRYPTO0_BITCLR_MEM_SIZE
Definition at line
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| #define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE |
Alias for CRYPTO0_BITSET_MEM_BASE
Definition at line
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| #define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS |
Alias for CRYPTO0_BITSET_MEM_BITS
Definition at line
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| #define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END |
Alias for CRYPTO0_BITSET_MEM_END
Definition at line
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| #define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE |
Alias for CRYPTO0_BITSET_MEM_SIZE
Definition at line
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| #define CRYPTO_COUNT 2 |
2 CRYPTOs available
Definition at line
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| #define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE |
Alias for CRYPTO0_MEM_BASE
Definition at line
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| #define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS |
Alias for CRYPTO0_MEM_BITS
Definition at line
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| #define CRYPTO_MEM_END CRYPTO0_MEM_END |
Alias for CRYPTO0_MEM_END
Definition at line
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| #define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE |
Alias for CRYPTO0_MEM_SIZE
Definition at line
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| #define CRYPTO_PRESENT |
CRYPTO is available in this part
Definition at line
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| #define CSEN_COUNT 1 |
1 CSEN available
Definition at line
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| #define CSEN_PRESENT |
CSEN is available in this part
Definition at line
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| #define DCDC_COUNT 1 |
1 DCDC available
Definition at line
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| #define DCDC_PRESENT |
DCDC is available in this part
Definition at line
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| #define DMA_CHAN_COUNT 8 |
Number of DMA channels
Definition at line
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Referenced by NANDFLASH_Init() .
| #define EMU_COUNT 1 |
1 EMU available
Definition at line
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| #define EMU_PRESENT |
EMU is available in this part
Definition at line
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| #define ETM_COUNT 1 |
1 ETM available
Definition at line
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| #define ETM_PRESENT |
ETM is available in this part
Definition at line
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| #define EXT_IRQ_COUNT 51 |
Number of External (NVIC) interrupts
Definition at line
247
of file
efm32pg12b500f1024gl125.h
.
Referenced by CORE_GetNvicRamTableHandler() , CORE_IrqIsBlocked() , CORE_NvicIRQDisabled() , CORE_NvicMaskClearIRQ() , CORE_NvicMaskSetIRQ() , and CORE_SetNvicRamTableHandler() .
| #define FLASH_BASE (0x00000000UL) |
Flash and SRAM limits for EFM32PG12B500F1024GL125 Flash Base Address
Definition at line
239
of file
efm32pg12b500f1024gl125.h
.
| #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) |
FLASH base address
Definition at line
185
of file
efm32pg12b500f1024gl125.h
.
| #define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) |
FLASH used bits
Definition at line
188
of file
efm32pg12b500f1024gl125.h
.
| #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) |
FLASH end address
Definition at line
187
of file
efm32pg12b500f1024gl125.h
.
| #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) |
FLASH available address space
Definition at line
186
of file
efm32pg12b500f1024gl125.h
.
| #define FLASH_PAGE_SIZE 2048U |
Flash Memory page size (interleaving off)
Definition at line
241
of file
efm32pg12b500f1024gl125.h
.
Referenced by MSC_ErasePage() , and SYSTEM_GetFlashPageSize() .
| #define FLASH_SIZE (0x00100000UL) |
Available Flash Memory
Definition at line
240
of file
efm32pg12b500f1024gl125.h
.
| #define FPUEH_COUNT 1 |
1 FPUEH available
Definition at line
301
of file
efm32pg12b500f1024gl125.h
.
| #define FPUEH_PRESENT |
FPUEH is available in this part
Definition at line
300
of file
efm32pg12b500f1024gl125.h
.
| #define GPCRC_COUNT 1 |
1 GPCRC available
Definition at line
303
of file
efm32pg12b500f1024gl125.h
.
| #define GPCRC_PRESENT |
GPCRC is available in this part
Definition at line
302
of file
efm32pg12b500f1024gl125.h
.
| #define GPIO_COUNT 1 |
1 GPIO available
Definition at line
295
of file
efm32pg12b500f1024gl125.h
.
| #define GPIO_PRESENT |
GPIO is available in this part
Definition at line
294
of file
efm32pg12b500f1024gl125.h
.
| #define I2C_COUNT 2 |
2 I2Cs available
Definition at line
273
of file
efm32pg12b500f1024gl125.h
.
| #define I2C_PRESENT |
I2C is available in this part
Definition at line
272
of file
efm32pg12b500f1024gl125.h
.
| #define IDAC_COUNT 1 |
1 IDACs available
Definition at line
279
of file
efm32pg12b500f1024gl125.h
.
| #define IDAC_PRESENT |
IDAC is available in this part
Definition at line
278
of file
efm32pg12b500f1024gl125.h
.
| #define LDMA_COUNT 1 |
1 LDMA available
Definition at line
299
of file
efm32pg12b500f1024gl125.h
.
| #define LDMA_PRESENT |
LDMA is available in this part
Definition at line
298
of file
efm32pg12b500f1024gl125.h
.
| #define LESENSE_COUNT 1 |
1 LESENSE available
Definition at line
309
of file
efm32pg12b500f1024gl125.h
.
| #define LESENSE_PRESENT |
LESENSE is available in this part
Definition at line
308
of file
efm32pg12b500f1024gl125.h
.
| #define LETIMER_COUNT 1 |
1 LETIMERs available
Definition at line
269
of file
efm32pg12b500f1024gl125.h
.
| #define LETIMER_PRESENT |
LETIMER is available in this part
Definition at line
268
of file
efm32pg12b500f1024gl125.h
.
| #define LEUART_COUNT 1 |
1 LEUARTs available
Definition at line
267
of file
efm32pg12b500f1024gl125.h
.
| #define LEUART_PRESENT |
LEUART is available in this part
Definition at line
266
of file
efm32pg12b500f1024gl125.h
.
| #define MSC_COUNT 1 |
1 MSC available
Definition at line
287
of file
efm32pg12b500f1024gl125.h
.
| #define MSC_PRESENT |
MSC is available in this part
Definition at line
286
of file
efm32pg12b500f1024gl125.h
.
| #define PART_NUMBER "EFM32PG12B500F1024GL125" |
Configure part number Part Number
Definition at line
154
of file
efm32pg12b500f1024gl125.h
.
| #define PCNT_COUNT 3 |
3 PCNTs available
Definition at line
271
of file
efm32pg12b500f1024gl125.h
.
Referenced by CMU_PCNTClockExternalSet() .
| #define PCNT_PRESENT |
PCNT is available in this part
Definition at line
270
of file
efm32pg12b500f1024gl125.h
.
| #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) |
PER_BITCLR base address
Definition at line
197
of file
efm32pg12b500f1024gl125.h
.
Referenced by BUS_RegMaskedClear() .
| #define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) |
PER_BITCLR used bits
Definition at line
200
of file
efm32pg12b500f1024gl125.h
.
| #define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) |
PER_BITCLR end address
Definition at line
199
of file
efm32pg12b500f1024gl125.h
.
| #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) |
PER_BITCLR available address space
Definition at line
198
of file
efm32pg12b500f1024gl125.h
.
| #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) |
PER_BITSET base address
Definition at line
217
of file
efm32pg12b500f1024gl125.h
.
Referenced by BUS_RegMaskedSet() .
| #define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) |
PER_BITSET used bits
Definition at line
220
of file
efm32pg12b500f1024gl125.h
.
| #define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) |
PER_BITSET end address
Definition at line
219
of file
efm32pg12b500f1024gl125.h
.
| #define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) |
PER_BITSET available address space
Definition at line
218
of file
efm32pg12b500f1024gl125.h
.
| #define PER_MEM_BASE ((uint32_t) 0x40000000UL) |
PER base address
Definition at line
173
of file
efm32pg12b500f1024gl125.h
.
Referenced by BUS_RegBitRead() , BUS_RegBitWrite() , BUS_RegMaskedClear() , and BUS_RegMaskedSet() .
| #define PER_MEM_BITS ((uint32_t) 0x00000014UL) |
PER used bits
Definition at line
176
of file
efm32pg12b500f1024gl125.h
.
| #define PER_MEM_END ((uint32_t) 0x400EFFFFUL) |
PER end address
Definition at line
175
of file
efm32pg12b500f1024gl125.h
.
| #define PER_MEM_SIZE ((uint32_t) 0xF0000UL) |
PER available address space
Definition at line
174
of file
efm32pg12b500f1024gl125.h
.
| #define PRS_CHAN_COUNT 12 |
Number of PRS channels
Definition at line
245
of file
efm32pg12b500f1024gl125.h
.
Referenced by PRS_SourceAsyncSignalSet() , and PRS_SourceSignalSet() .
| #define PRS_COUNT 1 |
1 PRS available
Definition at line
297
of file
efm32pg12b500f1024gl125.h
.
| #define PRS_PRESENT |
PRS is available in this part
Definition at line
296
of file
efm32pg12b500f1024gl125.h
.
| #define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) |
Memory Base addresses and limits RAM0_CODE base address
Definition at line
157
of file
efm32pg12b500f1024gl125.h
.
| #define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) |
RAM0_CODE used bits
Definition at line
160
of file
efm32pg12b500f1024gl125.h
.
| #define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) |
RAM0_CODE end address
Definition at line
159
of file
efm32pg12b500f1024gl125.h
.
| #define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) |
RAM0_CODE available address space
Definition at line
158
of file
efm32pg12b500f1024gl125.h
.
| #define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) |
RAM1_CODE base address
Definition at line
177
of file
efm32pg12b500f1024gl125.h
.
| #define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) |
RAM1_CODE used bits
Definition at line
180
of file
efm32pg12b500f1024gl125.h
.
| #define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) |
RAM1_CODE end address
Definition at line
179
of file
efm32pg12b500f1024gl125.h
.
| #define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) |
RAM1_CODE available address space
Definition at line
178
of file
efm32pg12b500f1024gl125.h
.
| #define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) |
RAM1 base address
Definition at line
165
of file
efm32pg12b500f1024gl125.h
.
Referenced by EMU_RamPowerDown() .
| #define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) |
RAM1 used bits
Definition at line
168
of file
efm32pg12b500f1024gl125.h
.
| #define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) |
RAM1 end address
Definition at line
167
of file
efm32pg12b500f1024gl125.h
.
Referenced by EMU_RamPowerDown() .
| #define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) |
RAM1 available address space
Definition at line
166
of file
efm32pg12b500f1024gl125.h
.
| #define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) |
RAM2_CODE base address
Definition at line
225
of file
efm32pg12b500f1024gl125.h
.
| #define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) |
RAM2_CODE used bits
Definition at line
228
of file
efm32pg12b500f1024gl125.h
.
| #define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) |
RAM2_CODE end address
Definition at line
227
of file
efm32pg12b500f1024gl125.h
.
| #define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) |
RAM2_CODE available address space
Definition at line
226
of file
efm32pg12b500f1024gl125.h
.
| #define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) |
RAM2 base address
Definition at line
161
of file
efm32pg12b500f1024gl125.h
.
Referenced by EMU_RamPowerDown() .
| #define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) |
RAM2 used bits
Definition at line
164
of file
efm32pg12b500f1024gl125.h
.
| #define RAM2_MEM_END ((uint32_t) 0x200407FFUL) |
RAM2 end address
Definition at line
163
of file
efm32pg12b500f1024gl125.h
.
Referenced by EMU_RamPowerDown() .
| #define RAM2_MEM_SIZE ((uint32_t) 0x800UL) |
RAM2 available address space
Definition at line
162
of file
efm32pg12b500f1024gl125.h
.
| #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) |
RAM base address
Definition at line
229
of file
efm32pg12b500f1024gl125.h
.
Referenced by EMU_RamPowerDown() .
| #define RAM_MEM_BITS ((uint32_t) 0x00000011UL) |
RAM used bits
Definition at line
232
of file
efm32pg12b500f1024gl125.h
.
| #define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) |
RAM end address
Definition at line
231
of file
efm32pg12b500f1024gl125.h
.
| #define RAM_MEM_SIZE ((uint32_t) 0x20000UL) |
RAM available address space
Definition at line
230
of file
efm32pg12b500f1024gl125.h
.
| #define RMU_COUNT 1 |
1 RMU available
Definition at line
291
of file
efm32pg12b500f1024gl125.h
.
| #define RMU_PRESENT |
RMU is available in this part
Definition at line
290
of file
efm32pg12b500f1024gl125.h
.
| #define RTCC_COUNT 1 |
1 RTCC available
Definition at line
311
of file
efm32pg12b500f1024gl125.h
.
| #define RTCC_PRESENT |
RTCC is available in this part
Definition at line
310
of file
efm32pg12b500f1024gl125.h
.
| #define SMU_COUNT 1 |
1 SMU available
Definition at line
317
of file
efm32pg12b500f1024gl125.h
.
| #define SMU_PRESENT |
SMU is available in this part
Definition at line
316
of file
efm32pg12b500f1024gl125.h
.
| #define SRAM_BASE (0x20000000UL) |
SRAM Base Address
Definition at line
242
of file
efm32pg12b500f1024gl125.h
.
Referenced by BUS_RamBitRead() , BUS_RamBitWrite() , CORE_InitNvicVectorTable() , and EMU_RamPowerDown() .
| #define SRAM_SIZE (0x00040000UL) |
Available SRAM Memory
Definition at line
243
of file
efm32pg12b500f1024gl125.h
.
Referenced by CORE_InitNvicVectorTable() , and EMU_RamPowerDown() .
| #define TIMER_COUNT 2 |
2 TIMERs available
Definition at line
261
of file
efm32pg12b500f1024gl125.h
.
| #define TIMER_PRESENT |
TIMER is available in this part
Definition at line
260
of file
efm32pg12b500f1024gl125.h
.
| #define TRNG_COUNT 1 |
1 TRNGs available
Definition at line
285
of file
efm32pg12b500f1024gl125.h
.
| #define TRNG_PRESENT |
TRNG is available in this part
Definition at line
284
of file
efm32pg12b500f1024gl125.h
.
| #define USART_COUNT 4 |
4 USARTs available
Definition at line
265
of file
efm32pg12b500f1024gl125.h
.
| #define USART_PRESENT |
USART is available in this part
Definition at line
264
of file
efm32pg12b500f1024gl125.h
.
| #define VDAC_COUNT 1 |
1 VDACs available
Definition at line
281
of file
efm32pg12b500f1024gl125.h
.
| #define VDAC_PRESENT |
VDAC is available in this part
Definition at line
280
of file
efm32pg12b500f1024gl125.h
.
| #define WDOG_COUNT 2 |
2 WDOGs available
Definition at line
283
of file
efm32pg12b500f1024gl125.h
.
| #define WDOG_PRESENT |
WDOG is available in this part
Definition at line
282
of file
efm32pg12b500f1024gl125.h
.
| #define WTIMER_COUNT 2 |
2 WTIMERs available
Definition at line
263
of file
efm32pg12b500f1024gl125.h
.
| #define WTIMER_PRESENT |
WTIMER is available in this part
Definition at line
262
of file
efm32pg12b500f1024gl125.h
.