SMU_TypeDef Struct ReferenceDevices > SMU

SMU Register Declaration

Definition at line 48 of file efm32tg11b_smu.h .

#include < efm32tg11b_smu.h >

Data Fields

__IOM uint32_t IEN
__IM uint32_t IF
__IOM uint32_t IFC
__IOM uint32_t IFS
__IOM uint32_t PPUCTRL
__IM uint32_t PPUFS
__IOM uint32_t PPUPATD0
__IOM uint32_t PPUPATD1
uint32_t RESERVED0 [3U]
uint32_t RESERVED1 [9U]
uint32_t RESERVED2 [3U]
uint32_t RESERVED3 [14U]

Field Documentation

__IOM uint32_t SMU_TypeDef::IEN

Interrupt Enable Register

Definition at line 53 of file efm32tg11b_smu.h .

__IM uint32_t SMU_TypeDef::IF

Interrupt Flag Register

Definition at line 50 of file efm32tg11b_smu.h .

__IOM uint32_t SMU_TypeDef::IFC

Interrupt Flag Clear Register

Definition at line 52 of file efm32tg11b_smu.h .

__IOM uint32_t SMU_TypeDef::IFS

Interrupt Flag Set Register

Definition at line 51 of file efm32tg11b_smu.h .

__IOM uint32_t SMU_TypeDef::PPUCTRL

PPU Control Register

Definition at line 56 of file efm32tg11b_smu.h .

__IM uint32_t SMU_TypeDef::PPUFS

PPU Fault Status

Definition at line 62 of file efm32tg11b_smu.h .

__IOM uint32_t SMU_TypeDef::PPUPATD0

PPU Privilege Access Type Descriptor 0

Definition at line 58 of file efm32tg11b_smu.h .

__IOM uint32_t SMU_TypeDef::PPUPATD1

PPU Privilege Access Type Descriptor 1

Definition at line 59 of file efm32tg11b_smu.h .

uint32_t SMU_TypeDef::RESERVED0[3U]

Reserved for future use

Definition at line 49 of file efm32tg11b_smu.h .

uint32_t SMU_TypeDef::RESERVED1[9U]

Reserved for future use

Definition at line 55 of file efm32tg11b_smu.h .

uint32_t SMU_TypeDef::RESERVED2[3U]

Reserved for future use

Definition at line 57 of file efm32tg11b_smu.h .

uint32_t SMU_TypeDef::RESERVED3[14U]

Reserved for future use

Definition at line 61 of file efm32tg11b_smu.h .


The documentation for this struct was generated from the following file:
  • C:/repos/super_h1/platform/Device/SiliconLabs/EFM32TG11B/Include/ efm32tg11b_smu.h