EUSART - Extended USART

Description

Extended Universal Synchronous/Asynchronous Receiver/Transmitter.


Introduction

This module contains functions to control the Enhanced Universal Synchronous / Asynchronous Receiver / Transmitter controller(s) (EUSART) peripheral of Silicon Labs' 32-bit MCUs and SoCs. EUSART can be used as a UART and can, therefore, be connected to an external transceiver to communicate with another host using the serial link.

It supports full duplex asynchronous UART communication as well as RS-485, SPI, MicroWire, and 3-wire. It can also interface with ISO7816 Smart-Cards, and IrDA devices.

EUSART has a wide selection of operating modes, frame formats, and baud rates. All features are supported through the API of this module.

This module does not support DMA configuration. UARTDRV and SPIDRV drivers provide full support for DMA and more.


Example

EUSART Async TX example:

{
EUSART_UartInit_TypeDef init = EUSART_UART_INIT_DEFAULT_HF ;
// Configure the clocks.
CMU_ClockSelectSet ( cmuClock_EUSART0CLK , cmuSelect_EM01GRPCCLK );
CMU_ClockEnable ( cmuClock_EUSART0CLK , true );
// Initialize the EUSART
EUSART_UartInitHf (EUSART0, &init);
EUSART_Tx (EUSART0, data);
}

EUSART Sync SPI Transaction example:

{
EUSART_SpiInit_TypeDef init_master = EUSART_SPI_MASTER_INIT_DEFAULT_HF ;
// Configure the clocks.
CMU_ClockSelectSet ( cmuClock_EM01GRPCCLK , cmuSelect_HFRCODPLL );
CMU_ClockEnable ( cmuClock_EUSART1 , true );
CMU_ClockEnable ( cmuClock_GPIO , true );
//Configure the SPI ports
GPIO_PinModeSet (sclk_port, sclk_pin, gpioModePushPull , 0);
GPIO_PinModeSet (mosi_port, mosi_pin, gpioModePushPull , 0);
GPIO_PinModeSet (mosi_port, miso_pin, gpioModeInput , 0);
// Connect EUSART to ports
GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].TXROUTE = (mosi_port << _GPIO_EUSART_TXROUTE_PORT_SHIFT)
| (mosi_pin << _GPIO_EUSART_TXROUTE_PIN_SHIFT);
GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].RXROUTE = (miso_port << _GPIO_EUSART_RXROUTE_PORT_SHIFT)
| (miso_pin << _GPIO_EUSART_RXROUTE_PIN_SHIFT);
GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].SCLKROUTE = (sclk_port << _GPIO_EUSART_SCLKROUTE_PORT_SHIFT)
| (sclk_pin << _GPIO_EUSART_SCLKROUTE_PIN_SHIFT);
GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN;
// Initialize the EUSART
EUSART_SpiInit (EUSART1, &init_master);
EUSART_Spi_TxRx (EUSART1, data);
}


EM2 guidelines for non EM2-Capable instances

Note
EUSART instances located in the PD1 power domain are non EM2-capable. The EUSART_EM2_CAPABLE() and EUSART_NOT_EM2_CAPABLE() macros can be used to determine whether or not a EUSART instance is EM2-Capable.

Follow theses steps when entering in EM2:

  1. Wait for the current transaction to complete with TXCIF interrupt
  2. Disable TX and RX using TXDIS and RXDIS cmd
  3. Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low
  4. Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low
  5. Disable SCLKPEN and CSPEN in GPIO if they were previously enabled
  6. Enter EM2

On wakeup from EM2, EUSART transmitter/receiver and relevant GPIO (SCLKPEN and CSPEN) must be re-enabled. For example:

{
// Enable TX and RX
EUSART_Enable (EUSART0, eusartEnable );
BUS_RegMaskedWrite (&GPIO->EUSARTROUTE[EUSART_NUM(EUSART0)].ROUTEEN,
_GPIO_EUSART_ROUTEEN_TXPEN_MASK | _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK,
GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN);
}

Data Structures

struct EUSART_AdvancedInit_TypeDef
Advanced initialization structure.
struct EUSART_UartInit_TypeDef
Initialization structure.
struct EUSART_IrDAInit_TypeDef
IrDA Initialization structure.
struct EUSART_PrsTriggerInit_TypeDef
PRS Trigger initialization structure.
struct EUSART_SpiAdvancedInit_TypeDef
SPI Advanced initialization structure.
struct EUSART_SpiInit_TypeDef
SPI Initialization structure.
struct EUSART_DaliInit_TypeDef
DALI Initialization structure.

Functions

void EUSART_UartInitHf (EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init)
Initialize EUSART when used in UART mode with the high frequency clock.
void EUSART_UartInitLf (EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init)
Initialize EUSART when used in UART mode with the low frequency clock.
void EUSART_IrDAInit (EUSART_TypeDef *eusart, const EUSART_IrDAInit_TypeDef *irdaInit)
Initialize EUSART when used in IrDA mode with the high or low frequency clock.
void EUSART_SpiInit (EUSART_TypeDef *eusart, const EUSART_SpiInit_TypeDef *init)
Initialize EUSART when used in SPI mode.
void EUSART_Reset (EUSART_TypeDef *eusart)
Configure EUSART to its reset state.
void EUSART_Enable (EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable)
Enable/disable EUSART receiver and/or transmitter.
uint8_t EUSART_Rx (EUSART_TypeDef *eusart)
Receive one 8 bit frame, (or part of 9 bit frame).
uint16_t EUSART_RxExt (EUSART_TypeDef *eusart)
Receive one 8-16 bit frame with extended information.
void EUSART_Tx (EUSART_TypeDef *eusart, uint8_t data)
Transmit one frame.
void EUSART_TxExt (EUSART_TypeDef *eusart, uint16_t data)
Transmit one 8-9 bit frame with extended control.
uint16_t EUSART_Spi_TxRx (EUSART_TypeDef *eusart, uint16_t data)
Transmit one 8-16 bit frame and return received data.
void EUSART_BaudrateSet (EUSART_TypeDef *eusart, uint32_t refFreq, uint32_t baudrate)
Configure the baudrate (or as close as possible to a specified baudrate).
uint32_t EUSART_BaudrateGet (EUSART_TypeDef *eusart)
Get the current baudrate.
void EUSART_RxBlock (EUSART_TypeDef *eusart, EUSART_BlockRx_TypeDef enable)
Enable/Disable reception operation until the configured start frame is received.
void EUSART_TxTristateSet (EUSART_TypeDef *eusart, EUSART_TristateTx_TypeDef enable)
Enable/Disable the tristating of the transmitter output.
void EUSART_PrsTriggerEnable (EUSART_TypeDef *eusart, const EUSART_PrsTriggerInit_TypeDef *init)
Initialize the automatic enabling of transmissions and/or reception using the PRS as a trigger.
uint32_t EUSART_StatusGet (EUSART_TypeDef *eusart)
Get EUSART STATUS register.
void EUSART_IntClear (EUSART_TypeDef *eusart, uint32_t flags)
Clear one or more pending EUSART interrupts.
void EUSART_IntDisable (EUSART_TypeDef *eusart, uint32_t flags)
Disable one or more EUSART interrupts.
void EUSART_IntEnable (EUSART_TypeDef *eusart, uint32_t flags)
Enable one or more EUSART interrupts.
uint32_t EUSART_IntGet (EUSART_TypeDef *eusart)
Get pending EUSART interrupt flags.
uint32_t EUSART_IntGetEnabled (EUSART_TypeDef *eusart)
Get enabled and pending EUSART interrupt flags.
void EUSART_IntSet (EUSART_TypeDef *eusart, uint32_t flags)
Set one or more pending EUSART interrupts from SW.

Macros

#define EUSART_UART_INIT_DEFAULT_HF
Default configuration for EUSART initialization structure in UART mode with high-frequency clock.
#define EUSART_DEFAULT_START_FRAME 0x00u
Default start frame configuration, i.e. feature disabled.
#define EUSART_ADVANCED_INIT_DEFAULT
Default configuration for EUSART advanced initialization structure.
#define EUSART_UART_INIT_DEFAULT_LF
Default configuration for EUSART initialization structure in UART mode with low-frequency clock.
#define EUSART_IRDA_INIT_DEFAULT_HF
Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock.
#define EUSART_IRDA_INIT_DEFAULT_LF
Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock.
#define EUSART_SPI_ADVANCED_INIT_DEFAULT
Default advanced configuration for EUSART initialization structure in SPI mode with high-frequency clock.
#define EUSART_SPI_MASTER_INIT_DEFAULT_HF
Default configuration for EUSART initialization structure in SPI master mode with high-frequency clock.
#define EUSART_SPI_SLAVE_INIT_DEFAULT_HF
Default configuration for EUSART initialization structure in SPI slave mode with high-frequency clock.

Typedefs

typedef uint8_t EUSART_PrsChannel_TypeDef
PRS Channel type.

Enumerations

enum EUSART_Enable_TypeDef {
eusartDisable = 0x0,
eusartEnableRx = (EUSART_CMD_RXEN | EUSART_CMD_TXDIS),
eusartEnableTx = (EUSART_CMD_TXEN | EUSART_CMD_RXDIS),
eusartEnable = (EUSART_CMD_RXEN | EUSART_CMD_TXEN)
}
Enable selection.
enum EUSART_Databits_TypeDef {
eusartDataBits7 = EUSART_FRAMECFG_DATABITS_SEVEN,
eusartDataBits8 = EUSART_FRAMECFG_DATABITS_EIGHT,
eusartDataBits9 = EUSART_FRAMECFG_DATABITS_NINE,
eusartDataBits10 = EUSART_FRAMECFG_DATABITS_TEN,
eusartDataBits11 = EUSART_FRAMECFG_DATABITS_ELEVEN,
eusartDataBits12 = EUSART_FRAMECFG_DATABITS_TWELVE,
eusartDataBits13 = EUSART_FRAMECFG_DATABITS_THIRTEEN,
eusartDataBits14 = EUSART_FRAMECFG_DATABITS_FOURTEEN,
eusartDataBits15 = EUSART_FRAMECFG_DATABITS_FIFTEEN,
eusartDataBits16 = EUSART_FRAMECFG_DATABITS_SIXTEEN
}
Data bit selection.
enum EUSART_Parity_TypeDef {
eusartNoParity = EUSART_FRAMECFG_PARITY_NONE,
eusartEvenParity = EUSART_FRAMECFG_PARITY_EVEN,
eusartOddParity = EUSART_FRAMECFG_PARITY_ODD
}
Parity selection.
enum EUSART_Stopbits_TypeDef {
eusartStopbits0p5 = EUSART_FRAMECFG_STOPBITS_HALF,
eusartStopbits1p5 = EUSART_FRAMECFG_STOPBITS_ONEANDAHALF,
eusartStopbits1 = EUSART_FRAMECFG_STOPBITS_ONE,
eusartStopbits2 = EUSART_FRAMECFG_STOPBITS_TWO
}
Stop bits selection.
enum EUSART_OVS_TypeDef {
eusartOVS16 = EUSART_CFG0_OVS_X16,
eusartOVS8 = EUSART_CFG0_OVS_X8,
eusartOVS6 = EUSART_CFG0_OVS_X6,
eusartOVS4 = EUSART_CFG0_OVS_X4,
eusartOVS0 = EUSART_CFG0_OVS_DISABLE
}
Oversampling selection, used for asynchronous operation.
enum EUSART_HwFlowControl_TypeDef {
eusartHwFlowControlNone = 0,
eusartHwFlowControlCts ,
eusartHwFlowControlRts ,
eusartHwFlowControlCtsAndRts
}
HW flow control config.
enum EUSART_LoopbackEnable_TypeDef {
eusartLoopbackEnable = EUSART_CFG0_LOOPBK,
eusartLoopbackDisable = _EUSART_CFG0_RESETVALUE
}
Loopback enable.
enum EUSART_MajorityVote_TypeDef {
eusartMajorityVoteEnable = EUSART_CFG0_MVDIS_DEFAULT,
eusartMajorityVoteDisable = EUSART_CFG0_MVDIS
}
Majority vote enable.
enum EUSART_BlockRx_TypeDef {
eusartBlockRxEnable = EUSART_CMD_RXBLOCKEN,
eusartBlockRxDisable = EUSART_CMD_RXBLOCKDIS
}
Block reception enable.
enum EUSART_TristateTx_TypeDef {
eusartTristateTxEnable = EUSART_CMD_TXTRIEN,
eusartTristateTxDisable = EUSART_CMD_TXTRIDIS
}
TX output tristate enable.
enum EUSART_IrDARxFilterEnable_TypeDef {
eusartIrDARxFilterEnable = EUSART_IRHFCFG_IRHFFILT_ENABLE,
eusartIrDARxFilterDisable = EUSART_IRHFCFG_IRHFFILT_DISABLE
}
IrDA filter enable.
enum EUSART_IrDAPulseWidth_Typedef {
eusartIrDAPulseWidthOne = EUSART_IRHFCFG_IRHFPW_ONE,
eusartIrDAPulseWidthTwo = EUSART_IRHFCFG_IRHFPW_TWO,
eusartIrDAPulseWidthThree = EUSART_IRHFCFG_IRHFPW_THREE,
eusartIrDAPulseWidthFour = EUSART_IRHFCFG_IRHFPW_FOUR
}
Pulse width selection for IrDA mode.
enum EUSART_PrsTriggerEnable_TypeDef {
eusartPrsTriggerDisable = 0x0,
eusartPrsTriggerEnableRx = EUSART_TRIGCTRL_RXTEN,
eusartPrsTriggerEnableTx = EUSART_TRIGCTRL_TXTEN,
eusartPrsTriggerEnableRxTx = (EUSART_TRIGCTRL_RXTEN | EUSART_TRIGCTRL_TXTEN)
}
PRS trigger enable.
enum EUSART_InvertIO_TypeDef {
eusartInvertIODisable = (EUSART_CFG0_RXINV_DISABLE | EUSART_CFG0_TXINV_DISABLE),
eusartInvertRxEnable = EUSART_CFG0_RXINV_ENABLE,
eusartInvertTxEnable = EUSART_CFG0_TXINV_ENABLE,
eusartInvertIOEnable = (EUSART_CFG0_RXINV_ENABLE | EUSART_CFG0_TXINV_ENABLE)
}
IO polarity selection.
enum EUSART_ClockMode_TypeDef {
eusartClockMode0 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLELEADING,
eusartClockMode1 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLETRAILING,
eusartClockMode2 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLELEADING,
eusartClockMode3 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLETRAILING
}
Clock polarity/phase mode.
enum EUSART_CsPolarity_TypeDef {
eusartCsActiveLow = EUSART_CFG2_CSINV_AL,
eusartCsActiveHigh = EUSART_CFG2_CSINV_AH
}
Chip select polarity.
enum EUSART_RxFifoWatermark_TypeDef {
eusartRxFiFoWatermark1Frame = EUSART_CFG1_RXFIW_ONEFRAME,
eusartRxFiFoWatermark2Frame = EUSART_CFG1_RXFIW_TWOFRAMES,
eusartRxFiFoWatermark3Frame = EUSART_CFG1_RXFIW_THREEFRAMES,
eusartRxFiFoWatermark4Frame = EUSART_CFG1_RXFIW_FOURFRAMES,
eusartRxFiFoWatermark5Frame = EUSART_CFG1_RXFIW_FIVEFRAMES,
eusartRxFiFoWatermark6Frame = EUSART_CFG1_RXFIW_SIXFRAMES,
eusartRxFiFoWatermark7Frame = EUSART_CFG1_RXFIW_SEVENFRAMES,
eusartRxFiFoWatermark8Frame = EUSART_CFG1_RXFIW_EIGHTFRAMES,
eusartRxFiFoWatermark9Frame = EUSART_CFG1_RXFIW_NINEFRAMES,
eusartRxFiFoWatermark10Frame = EUSART_CFG1_RXFIW_TENFRAMES,
eusartRxFiFoWatermark11Frame = EUSART_CFG1_RXFIW_ELEVENFRAMES,
eusartRxFiFoWatermark12Frame = EUSART_CFG1_RXFIW_TWELVEFRAMES,
eusartRxFiFoWatermark13Frame = EUSART_CFG1_RXFIW_THIRTEENFRAMES,
eusartRxFiFoWatermark14Frame = EUSART_CFG1_RXFIW_FOURTEENFRAMES,
eusartRxFiFoWatermark15Frame = EUSART_CFG1_RXFIW_FIFTEENFRAMES,
eusartRxFiFoWatermark16Frame = EUSART_CFG1_RXFIW_SIXTEENFRAMES
}
RX FIFO Interrupt ans Status Watermark.
enum EUSART_TxFifoWatermark_TypeDef {
eusartTxFiFoWatermark1Frame = EUSART_CFG1_TXFIW_ONEFRAME,
eusartTxFiFoWatermark2Frame = EUSART_CFG1_TXFIW_TWOFRAMES,
eusartTxFiFoWatermark3Frame = EUSART_CFG1_TXFIW_THREEFRAMES,
eusartTxFiFoWatermark4Frame = EUSART_CFG1_TXFIW_FOURFRAMES,
eusartTxFiFoWatermark5Frame = EUSART_CFG1_TXFIW_FIVEFRAMES,
eusartTxFiFoWatermark6Frame = EUSART_CFG1_TXFIW_SIXFRAMES,
eusartTxFiFoWatermark7Frame = EUSART_CFG1_TXFIW_SEVENFRAMES,
eusartTxFiFoWatermark8Frame = EUSART_CFG1_TXFIW_EIGHTFRAMES,
eusartTxFiFoWatermark9Frame = EUSART_CFG1_TXFIW_NINEFRAMES,
eusartTxFiFoWatermark10Frame = EUSART_CFG1_TXFIW_TENFRAMES,
eusartTxFiFoWatermark11Frame = EUSART_CFG1_TXFIW_ELEVENFRAMES,
eusartTxFiFoWatermark12Frame = EUSART_CFG1_TXFIW_TWELVEFRAMES,
eusartTxFiFoWatermark13Frame = EUSART_CFG1_TXFIW_THIRTEENFRAMES,
eusartTxFiFoWatermark14Frame = EUSART_CFG1_TXFIW_FOURTEENFRAMES,
eusartTxFiFoWatermark15Frame = EUSART_CFG1_TXFIW_FIFTEENFRAMES,
eusartTxFiFoWatermark16Frame = EUSART_CFG1_TXFIW_SIXTEENFRAMES
}
TX FIFO Interrupt and Status Watermark.

Function Documentation

◆ EUSART_UartInitHf()

void EUSART_UartInitHf ( EUSART_TypeDef * eusart,
const EUSART_UartInit_TypeDef * init
)

Initialize EUSART when used in UART mode with the high frequency clock.

Parameters
eusart Pointer to the EUSART peripheral register block.
init A pointer to the initialization structure.

Initialize EUSART when used in UART mode with the high frequency clock.

◆ EUSART_UartInitLf()

void EUSART_UartInitLf ( EUSART_TypeDef * eusart,
const EUSART_UartInit_TypeDef * init
)

Initialize EUSART when used in UART mode with the low frequency clock.

Parameters
eusart Pointer to the EUSART peripheral register block.
init A pointer to the initialization structure.

Initialize EUSART when used in UART mode with the low frequency clock.

Note
(1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral clock frequency must be at least three times higher than the chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), thus 32768 / 3 ~ 9600 baudrate.

◆ EUSART_IrDAInit()

void EUSART_IrDAInit ( EUSART_TypeDef * eusart,
const EUSART_IrDAInit_TypeDef * irdaInit
)

Initialize EUSART when used in IrDA mode with the high or low frequency clock.

Parameters
eusart Pointer to the EUSART peripheral register block.
irdaInit A pointer to the initialization structure.

Initialize EUSART when used in IrDA mode with the high or low frequency clock.

◆ EUSART_SpiInit()

void EUSART_SpiInit ( EUSART_TypeDef * eusart,
EUSART_SpiInit_TypeDef const * init
)

Initialize EUSART when used in SPI mode.

Parameters
eusart Pointer to the EUSART peripheral register block.
init A pointer to the initialization structure.

Initialize EUSART when used in SPI mode.

◆ EUSART_Reset()

void EUSART_Reset ( EUSART_TypeDef * eusart )

Configure EUSART to its reset state.

Parameters
eusart Pointer to the EUSART peripheral register block.

Configure EUSART to its reset state.

◆ EUSART_Enable()

void EUSART_Enable ( EUSART_TypeDef * eusart,
EUSART_Enable_TypeDef enable
)

Enable/disable EUSART receiver and/or transmitter.

Parameters
eusart Pointer to the EUSART peripheral register block.
enable Select the status for the receiver and transmitter.

Enable/disable EUSART receiver and/or transmitter.

◆ EUSART_Rx()

uint8_t EUSART_Rx ( EUSART_TypeDef * eusart )

Receive one 8 bit frame, (or part of 9 bit frame).

Parameters
eusart Pointer to the EUSART peripheral register block.
Note
This function is normally used to receive one frame when operating with frame length of 8 bits. See EUSART_RxExt() for reception of 9 bit frames. Notice that possible parity/stop bits are not considered a part of the specified frame bit length.
This function will stall if buffer is empty until data is received.
Returns
Data received.

Receive one 8 bit frame, (or part of 9 bit frame).

◆ EUSART_RxExt()

uint16_t EUSART_RxExt ( EUSART_TypeDef * eusart )

Receive one 8-16 bit frame with extended information.

Parameters
eusart Pointer to the EUSART peripheral register block.
Note
This function is normally used to receive one frame and additional RX status information.
This function will stall if buffer is empty until data is received.
Returns
Data received and receive status.

Receive one 8-16 bit frame with extended information.

◆ EUSART_Tx()

void EUSART_Tx ( EUSART_TypeDef * eusart,
uint8_t data
)

Transmit one frame.

Parameters
eusart Pointer to the EUSART peripheral register block.
data Data to transmit.
Note
Depending on the frame length configuration, 8 (least significant) bits from data are transmitted. If the frame length is 9, 8 bits are transmitted from data . See EUSART_TxExt() for transmitting 9 bit frame with full control of all 9 bits.
This function will stall if the 4 frame FIFO is full, until the buffer becomes available.

Transmit one frame.

◆ EUSART_TxExt()

void EUSART_TxExt ( EUSART_TypeDef * eusart,
uint16_t data
)

Transmit one 8-9 bit frame with extended control.

Parameters
eusart Pointer to the EUSART peripheral register block.
data Data to transmit.
Note
Possible parity/stop bits in asynchronous mode are not considered part of a specified frame bit length.
This function will stall if buffer is full until the buffer becomes available.

Transmit one 8-9 bit frame with extended control.

◆ EUSART_Spi_TxRx()

uint16_t EUSART_Spi_TxRx ( EUSART_TypeDef * eusart,
uint16_t data
)

Transmit one 8-16 bit frame and return received data.

Parameters
eusart Pointer to the EUSART peripheral register block.
data Data to transmit.
Returns
Data received and receive status.
Note
SPI master mode only.
This function will stall if the TX buffer is full until the buffer becomes available.

Transmit one 8-16 bit frame and return received data.

◆ EUSART_BaudrateSet()

void EUSART_BaudrateSet ( EUSART_TypeDef * eusart,
uint32_t refFreq,
uint32_t baudrate
)

Configure the baudrate (or as close as possible to a specified baudrate).

Parameters
eusart Pointer to the EUSART peripheral register block.
refFreq The EUSART reference clock frequency in Hz that will be used. If set to 0, the currently configured peripheral clock is used.
baudrate A baudrate to try to achieve.

Configure the baudrate (or as close as possible to a specified baudrate).

Note
(1) When the oversampling is disabled, the peripheral clock frequency must be at least three times higher than the chosen baud rate.

◆ EUSART_BaudrateGet()

uint32_t EUSART_BaudrateGet ( EUSART_TypeDef * eusart )

Get the current baudrate.

Parameters
eusart Pointer to the EUSART peripheral register block.
Returns
The current baudrate.

Get the current baudrate.

◆ EUSART_RxBlock()

void EUSART_RxBlock ( EUSART_TypeDef * eusart,
EUSART_BlockRx_TypeDef enable
)

Enable/Disable reception operation until the configured start frame is received.

Parameters
eusart Pointer to the EUSART peripheral register block.
enable Select the receiver blocking status.

Enable/Disable reception operation until the configured start frame is received.

◆ EUSART_TxTristateSet()

void EUSART_TxTristateSet ( EUSART_TypeDef * eusart,
EUSART_TristateTx_TypeDef enable
)

Enable/Disable the tristating of the transmitter output.

Parameters
eusart Pointer to the EUSART peripheral register block.
enable Select the transmitter tristate status.

Enable/Disable the tristating of the transmitter output.

◆ EUSART_PrsTriggerEnable()

void EUSART_PrsTriggerEnable ( EUSART_TypeDef * eusart,
const EUSART_PrsTriggerInit_TypeDef * init
)

Initialize the automatic enabling of transmissions and/or reception using the PRS as a trigger.

Note
Initialize EUSART with sl_eusart_initHf() or sl_eusart_initLf() before enabling the PRS trigger.
Parameters
eusart Pointer to the EUSART peripheral register block.
init Pointer to the initialization structure.

Initialize the automatic enabling of transmissions and/or reception using the PRS as a trigger.

◆ EUSART_StatusGet()

uint32_t EUSART_StatusGet ( EUSART_TypeDef * eusart )
inline

Get EUSART STATUS register.

Parameters
eusart Pointer to the EUSART peripheral register block.
Returns
STATUS register value.

◆ EUSART_IntClear()

void EUSART_IntClear ( EUSART_TypeDef * eusart,
uint32_t flags
)
inline

Clear one or more pending EUSART interrupts.

Parameters
eusart Pointer to the EUSART peripheral register block.
flags Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

◆ EUSART_IntDisable()

void EUSART_IntDisable ( EUSART_TypeDef * eusart,
uint32_t flags
)
inline

Disable one or more EUSART interrupts.

Parameters
eusart Pointer to the EUSART peripheral register block.
flags Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

◆ EUSART_IntEnable()

void EUSART_IntEnable ( EUSART_TypeDef * eusart,
uint32_t flags
)
inline

Enable one or more EUSART interrupts.

Parameters
eusart Pointer to the EUSART peripheral register block.
flags Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

◆ EUSART_IntGet()

uint32_t EUSART_IntGet ( EUSART_TypeDef * eusart )
inline

Get pending EUSART interrupt flags.

Parameters
eusart Pointer to the EUSART peripheral register block.
Returns
Pending EUSART interrupt sources.

◆ EUSART_IntGetEnabled()

uint32_t EUSART_IntGetEnabled ( EUSART_TypeDef * eusart )
inline

Get enabled and pending EUSART interrupt flags.

Useful for handling more interrupt sources in the same interrupt handler.

Parameters
eusart Pointer to the EUSART peripheral register block.
Returns
Pending and enabled EUSART interrupt sources.

◆ EUSART_IntSet()

void EUSART_IntSet ( EUSART_TypeDef * eusart,
uint32_t flags
)
inline

Set one or more pending EUSART interrupts from SW.

Parameters
eusart Pointer to the EUSART peripheral register block.
flags Interrupt source(s) to set to pending. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

Macro Definition Documentation

◆ EUSART_UART_INIT_DEFAULT_HF

#define EUSART_UART_INIT_DEFAULT_HF
Value:
{ \
eusartEnable, /* Enable RX/TX when initialization completed. */ \
0, /* Use current configured reference clock for configuring baud rate.*/ \
115200, /* 115200 bits/s. */ \
eusartOVS16, /* Oversampling x16. */ \
eusartDataBits8, /* 8 data bits. */ \
eusartNoParity, /* No parity. */ \
eusartStopbits1, /* 1 stop bit. */ \
eusartMajorityVoteEnable, /* Majority vote enabled. */ \
eusartLoopbackDisable, /* Loop back disabled. */ \
NULL, /* Default advanced settings. */ \
}

Default configuration for EUSART initialization structure in UART mode with high-frequency clock.

◆ EUSART_DEFAULT_START_FRAME

#define EUSART_DEFAULT_START_FRAME   0x00u

Default start frame configuration, i.e. feature disabled.

◆ EUSART_ADVANCED_INIT_DEFAULT

#define EUSART_ADVANCED_INIT_DEFAULT
Value:
{ \
eusartHwFlowControlNone, /* Flow control disabled. */ \
false, /* Collision detection disabled. */ \
false, /* Data is sent with the least significant bit first. */ \
eusartInvertIODisable, /* RX and TX signal active high. */ \
false, /* No DMA wake up on reception. */ \
false, /* No DMA wake up on transmission. */ \
false, /* Halt DMA on error disabled. */ \
EUSART_DEFAULT_START_FRAME, /* No start frame. */ \
false, /* TX auto tristate disabled. */ \
false, /* Do not use PRS signal as RX signal.*/ \
( EUSART_PrsChannel_TypeDef ) 0u, /* EUSART RX connected to prs channel 0. */ \
false , /* Multiprocessor mode disabled. */ \
false , /* Multiprocessor address bit : 0.*/ \
}

Default configuration for EUSART advanced initialization structure.

◆ EUSART_UART_INIT_DEFAULT_LF

#define EUSART_UART_INIT_DEFAULT_LF
Value:
{ \
eusartEnable, /* Enable RX/TX when initialization completed. */ \
0, /* Use current configured reference clock for configuring baud rate.*/ \
9600, /* 9600 bits/s. */ \
eusartOVS0, /* Oversampling disabled. */ \
eusartDataBits8, /* 8 data bits. */ \
eusartNoParity, /* No parity. */ \
eusartStopbits1, /* 1 stop bit. */ \
eusartMajorityVoteDisable, /* Majority vote enabled. */ \
eusartLoopbackDisable, /* Loop back disabled. */ \
NULL, /* Default advanced settings. */ \
}

Default configuration for EUSART initialization structure in UART mode with low-frequency clock.

◆ EUSART_IRDA_INIT_DEFAULT_HF

#define EUSART_IRDA_INIT_DEFAULT_HF
Value:
{ \
EUSART_UART_INIT_DEFAULT_HF, /* Default high frequency configuration. */ \
false, /* Disable IrDA low frequency mode. */ \
eusartIrDARxFilterDisable, /* RX Filter disabled. */ \
eusartIrDAPulseWidthOne, /* Pulse width is set to 1/16. */ \
}

Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock.

◆ EUSART_IRDA_INIT_DEFAULT_LF

#define EUSART_IRDA_INIT_DEFAULT_LF
Value:
{ \
{ \
eusartEnableRx, /* Enable RX when initialization completed (TX not allowed). */ \
0, /* Use current configured reference clock for configuring baud rate.*/ \
9600, /* 9600 bits/s. */ \
eusartOVS0, /* Oversampling disabled. */ \
eusartDataBits8, /* 8 data bits. */ \
eusartNoParity, /* No parity. */ \
eusartStopbits1, /* 1 stop bit. */ \
eusartMajorityVoteDisable, /* Majority vote enabled. */ \
eusartLoopbackDisable, /* Loop back disabled. */ \
NULL, /* Default advanced settings. */ \
}, \
true, /* Enable IrDA low frequency mode. */ \
eusartIrDARxFilterDisable, /* RX Filter disabled. */ \
eusartIrDAPulseWidthOne, /* Pulse width is set to 1. */ \
}

Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock.

◆ EUSART_SPI_ADVANCED_INIT_DEFAULT

#define EUSART_SPI_ADVANCED_INIT_DEFAULT
Value:
{ \
eusartCsActiveLow, /* CS active low. */ \
eusartInvertIODisable, /* RX and TX signal active High. */ \
true, /* AutoCS enabled. */ \
false, /* Data is sent with the least significant bit first. */ \
0u, /* CS setup time is 0 baud cycles */ \
0u, /* CS hold time is 0 baud cycles */ \
0u, /* Inter-frame time is 0 baud cycles */ \
false, /* AutoTX disabled. */ \
0x0000, /* Default transmitted data is 0. */ \
false, /* No DMA wake up on reception. */ \
false, /* Do not use PRS signal as RX signal. */ \
( EUSART_PrsChannel_TypeDef ) 0u, /* EUSART RX tied to prs channel 0. */ \
false , /* Do not use PRS signal as SCLK signal. */ \
( EUSART_PrsChannel_TypeDef ) 1u, /* EUSART SCLCK tied to prs channel 1. */ \
eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \
eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \
true, /* The first byte sent by the slave won't be the default value if a byte is made available \
after chip select is asserted. */ \
0x04u, /* Setup window before the sampling edge of SCLK at word-boundary to avoid force load error. */ \
}

Default advanced configuration for EUSART initialization structure in SPI mode with high-frequency clock.

◆ EUSART_SPI_MASTER_INIT_DEFAULT_HF

#define EUSART_SPI_MASTER_INIT_DEFAULT_HF
Value:
{ \
eusartEnable, /* Enable RX/TX when initialization completed. */ \
0, /* Use current configured reference clock for configuring baud rate.*/ \
10000000, /* 10 Mbits/s. */ \
eusartDataBits8, /* 8 data bits. */ \
true, /* Master mode enabled. */ \
eusartClockMode0, /* Clock idle low, sample on rising edge. */ \
eusartLoopbackDisable, /* Loop back disabled. */ \
NULL, /* Default advanced settings. */ \
}

Default configuration for EUSART initialization structure in SPI master mode with high-frequency clock.

◆ EUSART_SPI_SLAVE_INIT_DEFAULT_HF

#define EUSART_SPI_SLAVE_INIT_DEFAULT_HF
Value:
{ \
eusartEnable, /* Enable RX/TX when initialization completed. */ \
0, /* Use current configured reference clock for configuring baud rate.*/ \
10000000, /* 10 Mbits/s. */ \
eusartDataBits8, /* 8 data bits. */ \
false, /* Master mode enabled. */ \
eusartClockMode0, /* Clock idle low, sample on rising edge. */ \
eusartLoopbackDisable, /* Loop back disabled. */ \
NULL, /* Default advanced settings. */ \
}

Default configuration for EUSART initialization structure in SPI slave mode with high-frequency clock.

Typedef Documentation

◆ EUSART_PrsChannel_TypeDef

typedef uint8_t EUSART_PrsChannel_TypeDef

PRS Channel type.

Enumeration Type Documentation

◆ EUSART_Enable_TypeDef

enum EUSART_Enable_TypeDef

Enable selection.

Enumerator
eusartDisable

Disable the peripheral.

eusartEnableRx

Enable receiver only, transmitter disabled.

eusartEnableTx

Enable transmitter only, receiver disabled.

eusartEnable

Enable both receiver and transmitter.

◆ EUSART_Databits_TypeDef

enum EUSART_Databits_TypeDef

Data bit selection.

Enumerator
eusartDataBits7

7 data bits.

eusartDataBits8

8 data bits.

eusartDataBits9

9 data bits.

eusartDataBits10

10 data bits, SPI mode only.

eusartDataBits11

11 data bits, SPI mode only.

eusartDataBits12

12 data bits, SPI mode only.

eusartDataBits13

13 data bits, SPI mode only.

eusartDataBits14

14 data bits, SPI mode only.

eusartDataBits15

15 data bits, SPI mode only.

eusartDataBits16

16 data bits, SPI mode only.

◆ EUSART_Parity_TypeDef

enum EUSART_Parity_TypeDef

Parity selection.

Enumerator
eusartNoParity

No parity.

eusartEvenParity

Even parity.

eusartOddParity

Odd parity.

◆ EUSART_Stopbits_TypeDef

enum EUSART_Stopbits_TypeDef

Stop bits selection.

Enumerator
eusartStopbits0p5

0.5 stop bits.

eusartStopbits1p5

1.5 stop bits.

eusartStopbits1

1 stop bits.

eusartStopbits2

2 stop bits.

◆ EUSART_OVS_TypeDef

enum EUSART_OVS_TypeDef

Oversampling selection, used for asynchronous operation.

Enumerator
eusartOVS16

16x oversampling (normal).

eusartOVS8

8x oversampling.

eusartOVS6

6x oversampling.

eusartOVS4

4x oversampling.

eusartOVS0

Oversampling disabled.

◆ EUSART_HwFlowControl_TypeDef

enum EUSART_HwFlowControl_TypeDef

HW flow control config.

Enumerator
eusartHwFlowControlNone

No HW Flow Control.

eusartHwFlowControlCts

CTS HW Flow Control.

eusartHwFlowControlRts

RTS HW Flow Control.

eusartHwFlowControlCtsAndRts

CTS and RTS HW Flow Control.

◆ EUSART_LoopbackEnable_TypeDef

enum EUSART_LoopbackEnable_TypeDef

Loopback enable.

Enumerator
eusartLoopbackEnable

Enable loopback.

eusartLoopbackDisable

Disable loopback.

◆ EUSART_MajorityVote_TypeDef

enum EUSART_MajorityVote_TypeDef

Majority vote enable.

Enumerator
eusartMajorityVoteEnable

Enable majority vote for 16x, 8x and 6x oversampling modes.

eusartMajorityVoteDisable

Disable majority vote for 16x, 8x and 6x oversampling modes.

◆ EUSART_BlockRx_TypeDef

enum EUSART_BlockRx_TypeDef

Block reception enable.

Enumerator
eusartBlockRxEnable

Block reception enable, resulting in all incoming frames being discarded.

eusartBlockRxDisable

Block reception disable, resulting in all incoming frames being loaded into the RX FIFO.

◆ EUSART_TristateTx_TypeDef

enum EUSART_TristateTx_TypeDef

TX output tristate enable.

Enumerator
eusartTristateTxEnable

Tristates the transmitter output.

eusartTristateTxDisable

Disables tristating of the transmitter output.

◆ EUSART_IrDARxFilterEnable_TypeDef

enum EUSART_IrDARxFilterEnable_TypeDef

IrDA filter enable.

Enumerator
eusartIrDARxFilterEnable

Enable filter on demodulator.

eusartIrDARxFilterDisable

Disable filter on demodulator.

◆ EUSART_IrDAPulseWidth_Typedef

enum EUSART_IrDAPulseWidth_Typedef

Pulse width selection for IrDA mode.

Enumerator
eusartIrDAPulseWidthOne

IrDA pulse width is 1/16 for OVS=X16 and 1/8 for OVS=X8.

eusartIrDAPulseWidthTwo

IrDA pulse width is 2/16 for OVS=X16 and 2/8 for OVS=X8.

eusartIrDAPulseWidthThree

IrDA pulse width is 3/16 for OVS=X16 and 3/8 for OVS=X8.

eusartIrDAPulseWidthFour

IrDA pulse width is 4/16 for OVS=X16 and 4/8 for OVS=X8.

◆ EUSART_PrsTriggerEnable_TypeDef

enum EUSART_PrsTriggerEnable_TypeDef

PRS trigger enable.

Enumerator
eusartPrsTriggerDisable

Disable trigger on both receiver and transmitter.

eusartPrsTriggerEnableRx

Enable receive trigger only, transmit disabled.

eusartPrsTriggerEnableTx

Enable transmit trigger only, receive disabled.

eusartPrsTriggerEnableRxTx

Enable trigger on both receive and transmit.

◆ EUSART_InvertIO_TypeDef

enum EUSART_InvertIO_TypeDef

IO polarity selection.

Enumerator
eusartInvertIODisable

Disable inversion on both RX and TX signals.

eusartInvertRxEnable

Invert RX signal, before receiver.

eusartInvertTxEnable

Invert TX signal, after transmitter.

eusartInvertIOEnable

Enable trigger on both receive and transmit.

◆ EUSART_ClockMode_TypeDef

enum EUSART_ClockMode_TypeDef

Clock polarity/phase mode.

Enumerator
eusartClockMode0

Clock idle low, sample on rising edge.

eusartClockMode1

Clock idle low, sample on falling edge.

eusartClockMode2

Clock idle high, sample on falling edge.

eusartClockMode3

Clock idle high, sample on rising edge.

◆ EUSART_CsPolarity_TypeDef

enum EUSART_CsPolarity_TypeDef

Chip select polarity.

Enumerator
eusartCsActiveLow

Chip select active low.

eusartCsActiveHigh

Chip select active high.

◆ EUSART_RxFifoWatermark_TypeDef

enum EUSART_RxFifoWatermark_TypeDef

RX FIFO Interrupt ans Status Watermark.

◆ EUSART_TxFifoWatermark_TypeDef

enum EUSART_TxFifoWatermark_TypeDef

TX FIFO Interrupt and Status Watermark.