EUSART_SpiAdvancedInit_TypeDef Struct Reference

EUSART - Extended USART

Chip select polarity.

Enable inversion of RX and/or TX signals.

Enable automatic chip select. CS is managed by the peripheral.

If true, data will be send with most significant bit first.

Auto CS setup time (before transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).

Auto CS hold time (after transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).

Inter-frame time in baud cycles. Acceptable value ( 0 to 7 baud cycle).

Enable AUTOTX mode.

Transmits as long as the RX FIFO is not full. Generates underflow interrupt if the TX FIFO is empty.

Default transmitted data when the TXFIFO is empty.

Enable the automatic wake up from EM2 to EM1 for DMA RX operation.

Only applicable to EM2 (low frequency) capable EUSART instances.

Enable EUSART capability to use a PRS channel as an input data line for the receiver.

The configured RX GPIO signal won't be routed to the EUSART receiver.

PRS Channel used to transmit data from PRS to the EUSART.

Enable EUSART capability to use a PRS channel as an input SPI Clock.

Slave mode only.

PRS Channel used to transmit SCLK from PRS to the EUSART.

Interrupt and status level of the Receive FIFO.

Interrupt and status level of the Receive FIFO.

Force load the first FIFO value.

Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error.