CMU Bit FieldsDevices > CMU

Macros

#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT   0x00000000UL
 
#define _CMU_ADCCTRL_ADC0CLKDIV_MASK   0x3UL
 
#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION   0x00000000UL
 
#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT   0
 
#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT   0x00000000UL
 
#define _CMU_ADCCTRL_ADC0CLKINV_MASK   0x100UL
 
#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT   8
 
#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO   0x00000001UL
 
#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT   0x00000000UL
 
#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED   0x00000000UL
 
#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK   0x00000003UL
 
#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO   0x00000002UL
 
#define _CMU_ADCCTRL_ADC0CLKSEL_MASK   0x30UL
 
#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT   4
 
#define _CMU_ADCCTRL_MASK   0x00000133UL
 
#define _CMU_ADCCTRL_RESETVALUE   0x00000000UL
 
#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT   0x00000000UL
 
#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1   0x00000000UL
 
#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2   0x00000001UL
 
#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4   0x00000002UL
 
#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK   0x6000000UL
 
#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT   25
 
#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT   0x00000002UL
 
#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK   0xE00000UL
 
#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT   21
 
#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT   0x0000001FUL
 
#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK   0x3F00UL
 
#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT   8
 
#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT   0x00000000UL
 
#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK   0x8000000UL
 
#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT   27
 
#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT   0x00000008UL
 
#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK   0x1F0000UL
 
#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT   16
 
#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT   0x00000001UL
 
#define _CMU_AUXHFRCOCTRL_LDOHP_MASK   0x1000000UL
 
#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT   24
 
#define _CMU_AUXHFRCOCTRL_MASK   0xFFFF3F7FUL
 
#define _CMU_AUXHFRCOCTRL_RESETVALUE   0xB1481F7FUL
 
#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT   0x0000007FUL
 
#define _CMU_AUXHFRCOCTRL_TUNING_MASK   0x7FUL
 
#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT   0
 
#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT   0x0000000BUL
 
#define _CMU_AUXHFRCOCTRL_VREFTC_MASK   0xF0000000UL
 
#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT   28
 
#define _CMU_CALCNT_CALCNT_DEFAULT   0x00000000UL
 
#define _CMU_CALCNT_CALCNT_MASK   0xFFFFFUL
 
#define _CMU_CALCNT_CALCNT_SHIFT   0
 
#define _CMU_CALCNT_MASK   0x000FFFFFUL
 
#define _CMU_CALCNT_RESETVALUE   0x00000000UL
 
#define _CMU_CALCTRL_CONT_DEFAULT   0x00000000UL
 
#define _CMU_CALCTRL_CONT_MASK   0x100UL
 
#define _CMU_CALCTRL_CONT_SHIFT   8
 
#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO   0x00000005UL
 
#define _CMU_CALCTRL_DOWNSEL_DEFAULT   0x00000000UL
 
#define _CMU_CALCTRL_DOWNSEL_HFCLK   0x00000000UL
 
#define _CMU_CALCTRL_DOWNSEL_HFRCO   0x00000003UL
 
#define _CMU_CALCTRL_DOWNSEL_HFXO   0x00000001UL
 
#define _CMU_CALCTRL_DOWNSEL_LFRCO   0x00000004UL
 
#define _CMU_CALCTRL_DOWNSEL_LFXO   0x00000002UL
 
#define _CMU_CALCTRL_DOWNSEL_MASK   0x70UL
 
#define _CMU_CALCTRL_DOWNSEL_PRS   0x00000006UL
 
#define _CMU_CALCTRL_DOWNSEL_SHIFT   4
 
#define _CMU_CALCTRL_MASK   0x07070177UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT   0x00000000UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_MASK   0x7000000UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0   0x00000000UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1   0x00000001UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2   0x00000002UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3   0x00000003UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4   0x00000004UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5   0x00000005UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6   0x00000006UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7   0x00000007UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT   24
 
#define _CMU_CALCTRL_PRSUPSEL_DEFAULT   0x00000000UL
 
#define _CMU_CALCTRL_PRSUPSEL_MASK   0x70000UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH0   0x00000000UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH1   0x00000001UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH2   0x00000002UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH3   0x00000003UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH4   0x00000004UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH5   0x00000005UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH6   0x00000006UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH7   0x00000007UL
 
#define _CMU_CALCTRL_PRSUPSEL_SHIFT   16
 
#define _CMU_CALCTRL_RESETVALUE   0x00000000UL
 
#define _CMU_CALCTRL_UPSEL_AUXHFRCO   0x00000004UL
 
#define _CMU_CALCTRL_UPSEL_DEFAULT   0x00000000UL
 
#define _CMU_CALCTRL_UPSEL_HFRCO   0x00000002UL
 
#define _CMU_CALCTRL_UPSEL_HFXO   0x00000000UL
 
#define _CMU_CALCTRL_UPSEL_LFRCO   0x00000003UL
 
#define _CMU_CALCTRL_UPSEL_LFXO   0x00000001UL
 
#define _CMU_CALCTRL_UPSEL_MASK   0x7UL
 
#define _CMU_CALCTRL_UPSEL_PRS   0x00000005UL
 
#define _CMU_CALCTRL_UPSEL_SHIFT   0
 
#define _CMU_CMD_CALSTART_DEFAULT   0x00000000UL
 
#define _CMU_CMD_CALSTART_MASK   0x1UL
 
#define _CMU_CMD_CALSTART_SHIFT   0
 
#define _CMU_CMD_CALSTOP_DEFAULT   0x00000000UL
 
#define _CMU_CMD_CALSTOP_MASK   0x2UL
 
#define _CMU_CMD_CALSTOP_SHIFT   1
 
#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT   0x00000000UL
 
#define _CMU_CMD_HFXOPEAKDETSTART_MASK   0x10UL
 
#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT   4
 
#define _CMU_CMD_MASK   0x00000013UL
 
#define _CMU_CMD_RESETVALUE   0x00000000UL
 
#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ   0x0000000DUL
 
#define _CMU_CTRL_CLKOUTSEL0_DEFAULT   0x00000000UL
 
#define _CMU_CTRL_CLKOUTSEL0_DISABLED   0x00000000UL
 
#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK   0x00000007UL
 
#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ   0x0000000CUL
 
#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK   0x0000000FUL
 
#define _CMU_CTRL_CLKOUTSEL0_HFXO   0x00000006UL
 
#define _CMU_CTRL_CLKOUTSEL0_HFXOQ   0x0000000EUL
 
#define _CMU_CTRL_CLKOUTSEL0_LFRCO   0x00000002UL
 
#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ   0x0000000AUL
 
#define _CMU_CTRL_CLKOUTSEL0_LFXO   0x00000003UL
 
#define _CMU_CTRL_CLKOUTSEL0_LFXOQ   0x0000000BUL
 
#define _CMU_CTRL_CLKOUTSEL0_MASK   0xFUL
 
#define _CMU_CTRL_CLKOUTSEL0_SHIFT   0
 
#define _CMU_CTRL_CLKOUTSEL0_ULFRCO   0x00000001UL
 
#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ   0x00000009UL
 
#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ   0x0000000DUL
 
#define _CMU_CTRL_CLKOUTSEL1_DEFAULT   0x00000000UL
 
#define _CMU_CTRL_CLKOUTSEL1_DISABLED   0x00000000UL
 
#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK   0x00000007UL
 
#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ   0x0000000CUL
 
#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK   0x0000000FUL
 
#define _CMU_CTRL_CLKOUTSEL1_HFXO   0x00000006UL
 
#define _CMU_CTRL_CLKOUTSEL1_HFXOQ   0x0000000EUL
 
#define _CMU_CTRL_CLKOUTSEL1_LFRCO   0x00000002UL
 
#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ   0x0000000AUL
 
#define _CMU_CTRL_CLKOUTSEL1_LFXO   0x00000003UL
 
#define _CMU_CTRL_CLKOUTSEL1_LFXOQ   0x0000000BUL
 
#define _CMU_CTRL_CLKOUTSEL1_MASK   0x1E0UL
 
#define _CMU_CTRL_CLKOUTSEL1_SHIFT   5
 
#define _CMU_CTRL_CLKOUTSEL1_ULFRCO   0x00000001UL
 
#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ   0x00000009UL
 
#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ   0x0000000DUL
 
#define _CMU_CTRL_CLKOUTSEL2_DEFAULT   0x00000000UL
 
#define _CMU_CTRL_CLKOUTSEL2_DISABLED   0x00000000UL
 
#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK   0x00000007UL
 
#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ   0x0000000CUL
 
#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK   0x0000000FUL
 
#define _CMU_CTRL_CLKOUTSEL2_HFXO   0x00000006UL
 
#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q   0x00000005UL
 
#define _CMU_CTRL_CLKOUTSEL2_HFXOQ   0x0000000EUL
 
#define _CMU_CTRL_CLKOUTSEL2_LFRCO   0x00000002UL
 
#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ   0x0000000AUL
 
#define _CMU_CTRL_CLKOUTSEL2_LFXO   0x00000003UL
 
#define _CMU_CTRL_CLKOUTSEL2_LFXOQ   0x0000000BUL
 
#define _CMU_CTRL_CLKOUTSEL2_MASK   0x3C00UL
 
#define _CMU_CTRL_CLKOUTSEL2_SHIFT   10
 
#define _CMU_CTRL_CLKOUTSEL2_ULFRCO   0x00000001UL
 
#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ   0x00000009UL
 
#define _CMU_CTRL_HFPERCLKEN_DEFAULT   0x00000001UL
 
#define _CMU_CTRL_HFPERCLKEN_MASK   0x100000UL
 
#define _CMU_CTRL_HFPERCLKEN_SHIFT   20
 
#define _CMU_CTRL_MASK   0x00113DEFUL
 
#define _CMU_CTRL_RESETVALUE   0x00100000UL
 
#define _CMU_CTRL_WSHFLE_DEFAULT   0x00000000UL
 
#define _CMU_CTRL_WSHFLE_MASK   0x10000UL
 
#define _CMU_CTRL_WSHFLE_SHIFT   16
 
#define _CMU_DBGCLKSEL_DBG_AUXHFRCO   0x00000000UL
 
#define _CMU_DBGCLKSEL_DBG_DEFAULT   0x00000000UL
 
#define _CMU_DBGCLKSEL_DBG_HFCLK   0x00000001UL
 
#define _CMU_DBGCLKSEL_DBG_HFRCODIV2   0x00000002UL
 
#define _CMU_DBGCLKSEL_DBG_MASK   0x3UL
 
#define _CMU_DBGCLKSEL_DBG_SHIFT   0
 
#define _CMU_DBGCLKSEL_MASK   0x00000003UL
 
#define _CMU_DBGCLKSEL_RESETVALUE   0x00000000UL
 
#define _CMU_DPLLCTRL1_M_DEFAULT   0x00000000UL
 
#define _CMU_DPLLCTRL1_M_MASK   0xFFFUL
 
#define _CMU_DPLLCTRL1_M_SHIFT   0
 
#define _CMU_DPLLCTRL1_MASK   0x0FFF0FFFUL
 
#define _CMU_DPLLCTRL1_N_DEFAULT   0x00000000UL
 
#define _CMU_DPLLCTRL1_N_MASK   0xFFF0000UL
 
#define _CMU_DPLLCTRL1_N_SHIFT   16
 
#define _CMU_DPLLCTRL1_RESETVALUE   0x00000000UL
 
#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT   0x00000000UL
 
#define _CMU_DPLLCTRL_AUTORECOVER_MASK   0x4UL
 
#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT   2
 
#define _CMU_DPLLCTRL_DITHEN_DEFAULT   0x00000000UL
 
#define _CMU_DPLLCTRL_DITHEN_MASK   0x40UL
 
#define _CMU_DPLLCTRL_DITHEN_SHIFT   6
 
#define _CMU_DPLLCTRL_EDGESEL_DEFAULT   0x00000000UL
 
#define _CMU_DPLLCTRL_EDGESEL_FALL   0x00000000UL
 
#define _CMU_DPLLCTRL_EDGESEL_MASK   0x2UL
 
#define _CMU_DPLLCTRL_EDGESEL_RISE   0x00000001UL
 
#define _CMU_DPLLCTRL_EDGESEL_SHIFT   1
 
#define _CMU_DPLLCTRL_MASK   0x0000005FUL
 
#define _CMU_DPLLCTRL_MODE_DEFAULT   0x00000000UL
 
#define _CMU_DPLLCTRL_MODE_FREQLL   0x00000000UL
 
#define _CMU_DPLLCTRL_MODE_MASK   0x1UL
 
#define _CMU_DPLLCTRL_MODE_PHASELL   0x00000001UL
 
#define _CMU_DPLLCTRL_MODE_SHIFT   0
 
#define _CMU_DPLLCTRL_REFSEL_CLKIN0   0x00000003UL
 
#define _CMU_DPLLCTRL_REFSEL_DEFAULT   0x00000000UL
 
#define _CMU_DPLLCTRL_REFSEL_HFXO   0x00000000UL
 
#define _CMU_DPLLCTRL_REFSEL_LFXO   0x00000001UL
 
#define _CMU_DPLLCTRL_REFSEL_MASK   0x18UL
 
#define _CMU_DPLLCTRL_REFSEL_SHIFT   3
 
#define _CMU_DPLLCTRL_RESETVALUE   0x00000000UL
 
#define _CMU_FREEZE_MASK   0x00000001UL
 
#define _CMU_FREEZE_REGFREEZE_DEFAULT   0x00000000UL
 
#define _CMU_FREEZE_REGFREEZE_FREEZE   0x00000001UL
 
#define _CMU_FREEZE_REGFREEZE_MASK   0x1UL
 
#define _CMU_FREEZE_REGFREEZE_SHIFT   0
 
#define _CMU_FREEZE_REGFREEZE_UPDATE   0x00000000UL
 
#define _CMU_FREEZE_RESETVALUE   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK   0x2UL
 
#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT   1
 
#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_GPCRC_MASK   0x20UL
 
#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT   5
 
#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_GPIO_MASK   0x4UL
 
#define _CMU_HFBUSCLKEN0_GPIO_SHIFT   2
 
#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_LDMA_MASK   0x10UL
 
#define _CMU_HFBUSCLKEN0_LDMA_SHIFT   4
 
#define _CMU_HFBUSCLKEN0_LE_DEFAULT   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_LE_MASK   0x1UL
 
#define _CMU_HFBUSCLKEN0_LE_SHIFT   0
 
#define _CMU_HFBUSCLKEN0_MASK   0x0000003FUL
 
#define _CMU_HFBUSCLKEN0_PRS_DEFAULT   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_PRS_MASK   0x8UL
 
#define _CMU_HFBUSCLKEN0_PRS_SHIFT   3
 
#define _CMU_HFBUSCLKEN0_RESETVALUE   0x00000000UL
 
#define _CMU_HFBUSPRESC_MASK   0x0001FF00UL
 
#define _CMU_HFBUSPRESC_PRESC_DEFAULT   0x00000000UL
 
#define _CMU_HFBUSPRESC_PRESC_MASK   0x1FF00UL
 
#define _CMU_HFBUSPRESC_PRESC_NODIVISION   0x00000000UL
 
#define _CMU_HFBUSPRESC_PRESC_SHIFT   8
 
#define _CMU_HFBUSPRESC_RESETVALUE   0x00000000UL
 
#define _CMU_HFCLKSEL_HF_CLKIN0   0x00000007UL
 
#define _CMU_HFCLKSEL_HF_DEFAULT   0x00000000UL
 
#define _CMU_HFCLKSEL_HF_HFRCO   0x00000001UL
 
#define _CMU_HFCLKSEL_HF_HFRCODIV2   0x00000005UL
 
#define _CMU_HFCLKSEL_HF_HFXO   0x00000002UL
 
#define _CMU_HFCLKSEL_HF_LFRCO   0x00000003UL
 
#define _CMU_HFCLKSEL_HF_LFXO   0x00000004UL
 
#define _CMU_HFCLKSEL_HF_MASK   0x7UL
 
#define _CMU_HFCLKSEL_HF_SHIFT   0
 
#define _CMU_HFCLKSEL_MASK   0x00000007UL
 
#define _CMU_HFCLKSEL_RESETVALUE   0x00000000UL
 
#define _CMU_HFCLKSTATUS_MASK   0x00000007UL
 
#define _CMU_HFCLKSTATUS_RESETVALUE   0x00000001UL
 
#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0   0x00000007UL
 
#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT   0x00000001UL
 
#define _CMU_HFCLKSTATUS_SELECTED_HFRCO   0x00000001UL
 
#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2   0x00000005UL
 
#define _CMU_HFCLKSTATUS_SELECTED_HFXO   0x00000002UL
 
#define _CMU_HFCLKSTATUS_SELECTED_LFRCO   0x00000003UL
 
#define _CMU_HFCLKSTATUS_SELECTED_LFXO   0x00000004UL
 
#define _CMU_HFCLKSTATUS_SELECTED_MASK   0x7UL
 
#define _CMU_HFCLKSTATUS_SELECTED_SHIFT   0
 
#define _CMU_HFCOREPRESC_MASK   0x0001FF00UL
 
#define _CMU_HFCOREPRESC_PRESC_DEFAULT   0x00000000UL
 
#define _CMU_HFCOREPRESC_PRESC_MASK   0x1FF00UL
 
#define _CMU_HFCOREPRESC_PRESC_NODIVISION   0x00000000UL
 
#define _CMU_HFCOREPRESC_PRESC_SHIFT   8
 
#define _CMU_HFCOREPRESC_RESETVALUE   0x00000000UL
 
#define _CMU_HFEXPPRESC_MASK   0x00001F00UL
 
#define _CMU_HFEXPPRESC_PRESC_DEFAULT   0x00000000UL
 
#define _CMU_HFEXPPRESC_PRESC_MASK   0x1F00UL
 
#define _CMU_HFEXPPRESC_PRESC_NODIVISION   0x00000000UL
 
#define _CMU_HFEXPPRESC_PRESC_SHIFT   8
 
#define _CMU_HFEXPPRESC_RESETVALUE   0x00000000UL
 
#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_ACMP0_MASK   0x100UL
 
#define _CMU_HFPERCLKEN0_ACMP0_SHIFT   8
 
#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_ACMP1_MASK   0x200UL
 
#define _CMU_HFPERCLKEN0_ACMP1_SHIFT   9
 
#define _CMU_HFPERCLKEN0_ADC0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_ADC0_MASK   0x800UL
 
#define _CMU_HFPERCLKEN0_ADC0_SHIFT   11
 
#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK   0x400UL
 
#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT   10
 
#define _CMU_HFPERCLKEN0_I2C0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_I2C0_MASK   0x40UL
 
#define _CMU_HFPERCLKEN0_I2C0_SHIFT   6
 
#define _CMU_HFPERCLKEN0_I2C1_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_I2C1_MASK   0x80UL
 
#define _CMU_HFPERCLKEN0_I2C1_SHIFT   7
 
#define _CMU_HFPERCLKEN0_MASK   0x00001FFFUL
 
#define _CMU_HFPERCLKEN0_RESETVALUE   0x00000000UL
 
#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_TIMER0_MASK   0x10UL
 
#define _CMU_HFPERCLKEN0_TIMER0_SHIFT   4
 
#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_TIMER1_MASK   0x20UL
 
#define _CMU_HFPERCLKEN0_TIMER1_SHIFT   5
 
#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_TRNG0_MASK   0x1000UL
 
#define _CMU_HFPERCLKEN0_TRNG0_SHIFT   12
 
#define _CMU_HFPERCLKEN0_USART0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_USART0_MASK   0x1UL
 
#define _CMU_HFPERCLKEN0_USART0_SHIFT   0
 
#define _CMU_HFPERCLKEN0_USART1_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_USART1_MASK   0x2UL
 
#define _CMU_HFPERCLKEN0_USART1_SHIFT   1
 
#define _CMU_HFPERCLKEN0_USART2_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_USART2_MASK   0x4UL
 
#define _CMU_HFPERCLKEN0_USART2_SHIFT   2
 
#define _CMU_HFPERCLKEN0_USART3_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_USART3_MASK   0x8UL
 
#define _CMU_HFPERCLKEN0_USART3_SHIFT   3
 
#define _CMU_HFPERCLKEN1_CAN0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN1_CAN0_MASK   0x8UL
 
#define _CMU_HFPERCLKEN1_CAN0_SHIFT   3
 
#define _CMU_HFPERCLKEN1_CSEN_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN1_CSEN_MASK   0x20UL
 
#define _CMU_HFPERCLKEN1_CSEN_SHIFT   5
 
#define _CMU_HFPERCLKEN1_MASK   0x0000003FUL
 
#define _CMU_HFPERCLKEN1_RESETVALUE   0x00000000UL
 
#define _CMU_HFPERCLKEN1_UART0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN1_UART0_MASK   0x1UL
 
#define _CMU_HFPERCLKEN1_UART0_SHIFT   0
 
#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN1_VDAC0_MASK   0x10UL
 
#define _CMU_HFPERCLKEN1_VDAC0_SHIFT   4
 
#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN1_WTIMER0_MASK   0x2UL
 
#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT   1
 
#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN1_WTIMER1_MASK   0x4UL
 
#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT   2
 
#define _CMU_HFPERPRESC_MASK   0x0001FF00UL
 
#define _CMU_HFPERPRESC_PRESC_DEFAULT   0x00000000UL
 
#define _CMU_HFPERPRESC_PRESC_MASK   0x1FF00UL
 
#define _CMU_HFPERPRESC_PRESC_NODIVISION   0x00000000UL
 
#define _CMU_HFPERPRESC_PRESC_SHIFT   8
 
#define _CMU_HFPERPRESC_RESETVALUE   0x00000000UL
 
#define _CMU_HFPERPRESCB_MASK   0x0001FF00UL
 
#define _CMU_HFPERPRESCB_PRESC_DEFAULT   0x00000000UL
 
#define _CMU_HFPERPRESCB_PRESC_MASK   0x1FF00UL
 
#define _CMU_HFPERPRESCB_PRESC_NODIVISION   0x00000000UL
 
#define _CMU_HFPERPRESCB_PRESC_SHIFT   8
 
#define _CMU_HFPERPRESCB_RESETVALUE   0x00000000UL
 
#define _CMU_HFPERPRESCC_MASK   0x0001FF00UL
 
#define _CMU_HFPERPRESCC_PRESC_DEFAULT   0x00000000UL
 
#define _CMU_HFPERPRESCC_PRESC_MASK   0x1FF00UL
 
#define _CMU_HFPERPRESCC_PRESC_NODIVISION   0x00000000UL
 
#define _CMU_HFPERPRESCC_PRESC_SHIFT   8
 
#define _CMU_HFPERPRESCC_RESETVALUE   0x00000000UL
 
#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT   0x00000000UL
 
#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2   0x00000000UL
 
#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4   0x00000001UL
 
#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8   0x00000002UL
 
#define _CMU_HFPRESC_HFCLKLEPRESC_MASK   0x3000000UL
 
#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT   24
 
#define _CMU_HFPRESC_MASK   0x03001F00UL
 
#define _CMU_HFPRESC_PRESC_DEFAULT   0x00000000UL
 
#define _CMU_HFPRESC_PRESC_MASK   0x1F00UL
 
#define _CMU_HFPRESC_PRESC_NODIVISION   0x00000000UL
 
#define _CMU_HFPRESC_PRESC_SHIFT   8
 
#define _CMU_HFPRESC_RESETVALUE   0x00000000UL
 
#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT   0x00000000UL
 
#define _CMU_HFRCOCTRL_CLKDIV_DIV1   0x00000000UL
 
#define _CMU_HFRCOCTRL_CLKDIV_DIV2   0x00000001UL
 
#define _CMU_HFRCOCTRL_CLKDIV_DIV4   0x00000002UL
 
#define _CMU_HFRCOCTRL_CLKDIV_MASK   0x6000000UL
 
#define _CMU_HFRCOCTRL_CLKDIV_SHIFT   25
 
#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT   0x00000002UL
 
#define _CMU_HFRCOCTRL_CMPBIAS_MASK   0xE00000UL
 
#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT   21
 
#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT   0x0000001FUL
 
#define _CMU_HFRCOCTRL_FINETUNING_MASK   0x3F00UL
 
#define _CMU_HFRCOCTRL_FINETUNING_SHIFT   8
 
#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT   0x00000000UL
 
#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK   0x8000000UL
 
#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT   27
 
#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT   0x00000008UL
 
#define _CMU_HFRCOCTRL_FREQRANGE_MASK   0x1F0000UL
 
#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT   16
 
#define _CMU_HFRCOCTRL_LDOHP_DEFAULT   0x00000001UL
 
#define _CMU_HFRCOCTRL_LDOHP_MASK   0x1000000UL
 
#define _CMU_HFRCOCTRL_LDOHP_SHIFT   24
 
#define _CMU_HFRCOCTRL_MASK   0xFFFF3F7FUL
 
#define _CMU_HFRCOCTRL_RESETVALUE   0xB1481F7FUL
 
#define _CMU_HFRCOCTRL_TUNING_DEFAULT   0x0000007FUL
 
#define _CMU_HFRCOCTRL_TUNING_MASK   0x7FUL
 
#define _CMU_HFRCOCTRL_TUNING_SHIFT   0
 
#define _CMU_HFRCOCTRL_VREFTC_DEFAULT   0x0000000BUL
 
#define _CMU_HFRCOCTRL_VREFTC_MASK   0xF0000000UL
 
#define _CMU_HFRCOCTRL_VREFTC_SHIFT   28
 
#define _CMU_HFRCOSS_MASK   0x00001F07UL
 
#define _CMU_HFRCOSS_RESETVALUE   0x00000000UL
 
#define _CMU_HFRCOSS_SSAMP_DEFAULT   0x00000000UL
 
#define _CMU_HFRCOSS_SSAMP_MASK   0x7UL
 
#define _CMU_HFRCOSS_SSAMP_SHIFT   0
 
#define _CMU_HFRCOSS_SSINV_DEFAULT   0x00000000UL
 
#define _CMU_HFRCOSS_SSINV_MASK   0x1F00UL
 
#define _CMU_HFRCOSS_SSINV_SHIFT   8
 
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK   0x10000000UL
 
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT   28
 
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK   0x20000000UL
 
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT   29
 
#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES   0x00000000UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES   0x00000003UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES   0x00000006UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES   0x00000001UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES   0x00000004UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES   0x00000002UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES   0x00000007UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES   0x00000005UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_MASK   0x7000000UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT   24
 
#define _CMU_HFXOCTRL_MASK   0x37000033UL
 
#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK   0x00000001UL
 
#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK   0x00000002UL
 
#define _CMU_HFXOCTRL_MODE_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL_MODE_DIGEXTCLK   0x00000003UL
 
#define _CMU_HFXOCTRL_MODE_MASK   0x3UL
 
#define _CMU_HFXOCTRL_MODE_SHIFT   0
 
#define _CMU_HFXOCTRL_MODE_XTAL   0x00000000UL
 
#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD   0x00000001UL
 
#define _CMU_HFXOCTRL_PEAKDETMODE_CMD   0x00000002UL
 
#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL   0x00000003UL
 
#define _CMU_HFXOCTRL_PEAKDETMODE_MASK   0x30UL
 
#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD   0x00000000UL
 
#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT   4
 
#define _CMU_HFXOCTRL_RESETVALUE   0x00000000UL
 
#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT   0x00000000UL
 
#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK   0xFF800UL
 
#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT   11
 
#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT   0x00000600UL
 
#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK   0x7FFUL
 
#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT   0
 
#define _CMU_HFXOSTARTUPCTRL_MASK   0x000FFFFFUL
 
#define _CMU_HFXOSTARTUPCTRL_RESETVALUE   0x00000600UL
 
#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT   0x00000000UL
 
#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK   0xFF800UL
 
#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT   11
 
#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT   0x00000100UL
 
#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK   0x7FFUL
 
#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT   0
 
#define _CMU_HFXOSTEADYSTATECTRL_MASK   0x0C0FFFFFUL
 
#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT   0x00000000UL
 
#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK   0x4000000UL
 
#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT   26
 
#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT   0x00000001UL
 
#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK   0x8000000UL
 
#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT   27
 
#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE   0x08000100UL
 
#define _CMU_HFXOTIMEOUTCTRL_MASK   0x0000F0FFUL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES   0x00000005UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES   0x0000000EUL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES   0x00000002UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES   0x0000000BUL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES   0x00000007UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES   0x00000006UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES   0x00000000UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES   0x00000008UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES   0x00000003UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES   0x0000000CUL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES   0x00000001UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES   0x00000009UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES   0x00000004UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES   0x0000000DUL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES   0x0000000AUL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT   0x0000000DUL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK   0xF000UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT   12
 
#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE   0x0000D04EUL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES   0x00000005UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES   0x0000000EUL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES   0x00000002UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES   0x0000000BUL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES   0x00000007UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES   0x00000006UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES   0x00000000UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES   0x00000008UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES   0x00000003UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES   0x0000000CUL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES   0x00000001UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES   0x00000009UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES   0x00000004UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES   0x0000000DUL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES   0x0000000AUL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT   0x0000000EUL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK   0xFUL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT   0
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES   0x00000005UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES   0x0000000EUL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES   0x00000002UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES   0x0000000BUL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES   0x00000007UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES   0x00000006UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES   0x00000000UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES   0x00000008UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES   0x00000003UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES   0x0000000CUL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES   0x00000001UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES   0x00000009UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES   0x00000004UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES   0x0000000DUL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES   0x0000000AUL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT   0x00000004UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK   0xF0UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT   4
 
#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT   0x00000000UL
 
#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK   0x7FFUL
 
#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT   0
 
#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT   0x00000000UL
 
#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK   0x7FF0000UL
 
#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT   16
 
#define _CMU_HFXOTRIMSTATUS_MASK   0xC7FF07FFUL
 
#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT   0x00000000UL
 
#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK   0x80000000UL
 
#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT   31
 
#define _CMU_HFXOTRIMSTATUS_RESETVALUE   0x00000000UL
 
#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT   0x00000000UL
 
#define _CMU_HFXOTRIMSTATUS_VALID_MASK   0x40000000UL
 
#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT   30
 
#define _CMU_IEN_AUXHFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_AUXHFRCORDY_MASK   0x10UL
 
#define _CMU_IEN_AUXHFRCORDY_SHIFT   4
 
#define _CMU_IEN_CALOF_DEFAULT   0x00000000UL
 
#define _CMU_IEN_CALOF_MASK   0x40UL
 
#define _CMU_IEN_CALOF_SHIFT   6
 
#define _CMU_IEN_CALRDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_CALRDY_MASK   0x20UL
 
#define _CMU_IEN_CALRDY_SHIFT   5
 
#define _CMU_IEN_CMUERR_DEFAULT   0x00000000UL
 
#define _CMU_IEN_CMUERR_MASK   0x80000000UL
 
#define _CMU_IEN_CMUERR_SHIFT   31
 
#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT   0x00000000UL
 
#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK   0x20000UL
 
#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT   17
 
#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT   0x00000000UL
 
#define _CMU_IEN_DPLLLOCKFAILLOW_MASK   0x10000UL
 
#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT   16
 
#define _CMU_IEN_DPLLRDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_DPLLRDY_MASK   0x8000UL
 
#define _CMU_IEN_DPLLRDY_SHIFT   15
 
#define _CMU_IEN_HFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFRCODIS_MASK   0x2000UL
 
#define _CMU_IEN_HFRCODIS_SHIFT   13
 
#define _CMU_IEN_HFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFRCORDY_MASK   0x1UL
 
#define _CMU_IEN_HFRCORDY_SHIFT   0
 
#define _CMU_IEN_HFXOAUTOSW_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFXOAUTOSW_MASK   0x200UL
 
#define _CMU_IEN_HFXOAUTOSW_SHIFT   9
 
#define _CMU_IEN_HFXODISERR_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFXODISERR_MASK   0x100UL
 
#define _CMU_IEN_HFXODISERR_SHIFT   8
 
#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFXOPEAKDETRDY_MASK   0x800UL
 
#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT   11
 
#define _CMU_IEN_HFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFXORDY_MASK   0x2UL
 
#define _CMU_IEN_HFXORDY_SHIFT   1
 
#define _CMU_IEN_LFRCOEDGE_DEFAULT   0x00000000UL
 
#define _CMU_IEN_LFRCOEDGE_MASK   0x10000000UL
 
#define _CMU_IEN_LFRCOEDGE_SHIFT   28
 
#define _CMU_IEN_LFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_LFRCORDY_MASK   0x4UL
 
#define _CMU_IEN_LFRCORDY_SHIFT   2
 
#define _CMU_IEN_LFTIMEOUTERR_DEFAULT   0x00000000UL
 
#define _CMU_IEN_LFTIMEOUTERR_MASK   0x4000UL
 
#define _CMU_IEN_LFTIMEOUTERR_SHIFT   14
 
#define _CMU_IEN_LFXOEDGE_DEFAULT   0x00000000UL
 
#define _CMU_IEN_LFXOEDGE_MASK   0x8000000UL
 
#define _CMU_IEN_LFXOEDGE_SHIFT   27
 
#define _CMU_IEN_LFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_LFXORDY_MASK   0x8UL
 
#define _CMU_IEN_LFXORDY_SHIFT   3
 
#define _CMU_IEN_MASK   0xB803EB7FUL
 
#define _CMU_IEN_RESETVALUE   0x00000000UL
 
#define _CMU_IEN_ULFRCOEDGE_DEFAULT   0x00000000UL
 
#define _CMU_IEN_ULFRCOEDGE_MASK   0x20000000UL
 
#define _CMU_IEN_ULFRCOEDGE_SHIFT   29
 
#define _CMU_IF_AUXHFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_AUXHFRCORDY_MASK   0x10UL
 
#define _CMU_IF_AUXHFRCORDY_SHIFT   4
 
#define _CMU_IF_CALOF_DEFAULT   0x00000000UL
 
#define _CMU_IF_CALOF_MASK   0x40UL
 
#define _CMU_IF_CALOF_SHIFT   6
 
#define _CMU_IF_CALRDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_CALRDY_MASK   0x20UL
 
#define _CMU_IF_CALRDY_SHIFT   5
 
#define _CMU_IF_CMUERR_DEFAULT   0x00000000UL
 
#define _CMU_IF_CMUERR_MASK   0x80000000UL
 
#define _CMU_IF_CMUERR_SHIFT   31
 
#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT   0x00000000UL
 
#define _CMU_IF_DPLLLOCKFAILHIGH_MASK   0x20000UL
 
#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT   17
 
#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT   0x00000000UL
 
#define _CMU_IF_DPLLLOCKFAILLOW_MASK   0x10000UL
 
#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT   16
 
#define _CMU_IF_DPLLRDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_DPLLRDY_MASK   0x8000UL
 
#define _CMU_IF_DPLLRDY_SHIFT   15
 
#define _CMU_IF_HFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_IF_HFRCODIS_MASK   0x2000UL
 
#define _CMU_IF_HFRCODIS_SHIFT   13
 
#define _CMU_IF_HFRCORDY_DEFAULT   0x00000001UL
 
#define _CMU_IF_HFRCORDY_MASK   0x1UL
 
#define _CMU_IF_HFRCORDY_SHIFT   0
 
#define _CMU_IF_HFXOAUTOSW_DEFAULT   0x00000000UL
 
#define _CMU_IF_HFXOAUTOSW_MASK   0x200UL
 
#define _CMU_IF_HFXOAUTOSW_SHIFT   9
 
#define _CMU_IF_HFXODISERR_DEFAULT   0x00000000UL
 
#define _CMU_IF_HFXODISERR_MASK   0x100UL
 
#define _CMU_IF_HFXODISERR_SHIFT   8
 
#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_HFXOPEAKDETRDY_MASK   0x800UL
 
#define _CMU_IF_HFXOPEAKDETRDY_SHIFT   11
 
#define _CMU_IF_HFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_HFXORDY_MASK   0x2UL
 
#define _CMU_IF_HFXORDY_SHIFT   1
 
#define _CMU_IF_LFRCOEDGE_DEFAULT   0x00000000UL
 
#define _CMU_IF_LFRCOEDGE_MASK   0x10000000UL
 
#define _CMU_IF_LFRCOEDGE_SHIFT   28
 
#define _CMU_IF_LFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_LFRCORDY_MASK   0x4UL
 
#define _CMU_IF_LFRCORDY_SHIFT   2
 
#define _CMU_IF_LFTIMEOUTERR_DEFAULT   0x00000000UL
 
#define _CMU_IF_LFTIMEOUTERR_MASK   0x4000UL
 
#define _CMU_IF_LFTIMEOUTERR_SHIFT   14
 
#define _CMU_IF_LFXOEDGE_DEFAULT   0x00000000UL
 
#define _CMU_IF_LFXOEDGE_MASK   0x8000000UL
 
#define _CMU_IF_LFXOEDGE_SHIFT   27
 
#define _CMU_IF_LFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_LFXORDY_MASK   0x8UL
 
#define _CMU_IF_LFXORDY_SHIFT   3
 
#define _CMU_IF_MASK   0xB803EB7FUL
 
#define _CMU_IF_RESETVALUE   0x00000001UL
 
#define _CMU_IF_ULFRCOEDGE_DEFAULT   0x00000000UL
 
#define _CMU_IF_ULFRCOEDGE_MASK   0x20000000UL
 
#define _CMU_IF_ULFRCOEDGE_SHIFT   29
 
#define _CMU_IFC_AUXHFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_AUXHFRCORDY_MASK   0x10UL
 
#define _CMU_IFC_AUXHFRCORDY_SHIFT   4
 
#define _CMU_IFC_CALOF_DEFAULT   0x00000000UL
 
#define _CMU_IFC_CALOF_MASK   0x40UL
 
#define _CMU_IFC_CALOF_SHIFT   6
 
#define _CMU_IFC_CALRDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_CALRDY_MASK   0x20UL
 
#define _CMU_IFC_CALRDY_SHIFT   5
 
#define _CMU_IFC_CMUERR_DEFAULT   0x00000000UL
 
#define _CMU_IFC_CMUERR_MASK   0x80000000UL
 
#define _CMU_IFC_CMUERR_SHIFT   31
 
#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT   0x00000000UL
 
#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK   0x20000UL
 
#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT   17
 
#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT   0x00000000UL
 
#define _CMU_IFC_DPLLLOCKFAILLOW_MASK   0x10000UL
 
#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT   16
 
#define _CMU_IFC_DPLLRDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_DPLLRDY_MASK   0x8000UL
 
#define _CMU_IFC_DPLLRDY_SHIFT   15
 
#define _CMU_IFC_HFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFRCODIS_MASK   0x2000UL
 
#define _CMU_IFC_HFRCODIS_SHIFT   13
 
#define _CMU_IFC_HFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFRCORDY_MASK   0x1UL
 
#define _CMU_IFC_HFRCORDY_SHIFT   0
 
#define _CMU_IFC_HFXOAUTOSW_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFXOAUTOSW_MASK   0x200UL
 
#define _CMU_IFC_HFXOAUTOSW_SHIFT   9
 
#define _CMU_IFC_HFXODISERR_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFXODISERR_MASK   0x100UL
 
#define _CMU_IFC_HFXODISERR_SHIFT   8
 
#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFXOPEAKDETRDY_MASK   0x800UL
 
#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT   11
 
#define _CMU_IFC_HFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFXORDY_MASK   0x2UL
 
#define _CMU_IFC_HFXORDY_SHIFT   1
 
#define _CMU_IFC_LFRCOEDGE_DEFAULT   0x00000000UL
 
#define _CMU_IFC_LFRCOEDGE_MASK   0x10000000UL
 
#define _CMU_IFC_LFRCOEDGE_SHIFT   28
 
#define _CMU_IFC_LFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_LFRCORDY_MASK   0x4UL
 
#define _CMU_IFC_LFRCORDY_SHIFT   2
 
#define _CMU_IFC_LFTIMEOUTERR_DEFAULT   0x00000000UL
 
#define _CMU_IFC_LFTIMEOUTERR_MASK   0x4000UL
 
#define _CMU_IFC_LFTIMEOUTERR_SHIFT   14
 
#define _CMU_IFC_LFXOEDGE_DEFAULT   0x00000000UL
 
#define _CMU_IFC_LFXOEDGE_MASK   0x8000000UL
 
#define _CMU_IFC_LFXOEDGE_SHIFT   27
 
#define _CMU_IFC_LFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_LFXORDY_MASK   0x8UL
 
#define _CMU_IFC_LFXORDY_SHIFT   3
 
#define _CMU_IFC_MASK   0xB803EB7FUL
 
#define _CMU_IFC_RESETVALUE   0x00000000UL
 
#define _CMU_IFC_ULFRCOEDGE_DEFAULT   0x00000000UL
 
#define _CMU_IFC_ULFRCOEDGE_MASK   0x20000000UL
 
#define _CMU_IFC_ULFRCOEDGE_SHIFT   29
 
#define _CMU_IFS_AUXHFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_AUXHFRCORDY_MASK   0x10UL
 
#define _CMU_IFS_AUXHFRCORDY_SHIFT   4
 
#define _CMU_IFS_CALOF_DEFAULT   0x00000000UL
 
#define _CMU_IFS_CALOF_MASK   0x40UL
 
#define _CMU_IFS_CALOF_SHIFT   6
 
#define _CMU_IFS_CALRDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_CALRDY_MASK   0x20UL
 
#define _CMU_IFS_CALRDY_SHIFT   5
 
#define _CMU_IFS_CMUERR_DEFAULT   0x00000000UL
 
#define _CMU_IFS_CMUERR_MASK   0x80000000UL
 
#define _CMU_IFS_CMUERR_SHIFT   31
 
#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT   0x00000000UL
 
#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK   0x20000UL
 
#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT   17
 
#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT   0x00000000UL
 
#define _CMU_IFS_DPLLLOCKFAILLOW_MASK   0x10000UL
 
#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT   16
 
#define _CMU_IFS_DPLLRDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_DPLLRDY_MASK   0x8000UL
 
#define _CMU_IFS_DPLLRDY_SHIFT   15
 
#define _CMU_IFS_HFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFRCODIS_MASK   0x2000UL
 
#define _CMU_IFS_HFRCODIS_SHIFT   13
 
#define _CMU_IFS_HFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFRCORDY_MASK   0x1UL
 
#define _CMU_IFS_HFRCORDY_SHIFT   0
 
#define _CMU_IFS_HFXOAUTOSW_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFXOAUTOSW_MASK   0x200UL
 
#define _CMU_IFS_HFXOAUTOSW_SHIFT   9
 
#define _CMU_IFS_HFXODISERR_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFXODISERR_MASK   0x100UL
 
#define _CMU_IFS_HFXODISERR_SHIFT   8
 
#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFXOPEAKDETRDY_MASK   0x800UL
 
#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT   11
 
#define _CMU_IFS_HFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFXORDY_MASK   0x2UL
 
#define _CMU_IFS_HFXORDY_SHIFT   1
 
#define _CMU_IFS_LFRCOEDGE_DEFAULT   0x00000000UL
 
#define _CMU_IFS_LFRCOEDGE_MASK   0x10000000UL
 
#define _CMU_IFS_LFRCOEDGE_SHIFT   28
 
#define _CMU_IFS_LFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_LFRCORDY_MASK   0x4UL
 
#define _CMU_IFS_LFRCORDY_SHIFT   2
 
#define _CMU_IFS_LFTIMEOUTERR_DEFAULT   0x00000000UL
 
#define _CMU_IFS_LFTIMEOUTERR_MASK   0x4000UL
 
#define _CMU_IFS_LFTIMEOUTERR_SHIFT   14
 
#define _CMU_IFS_LFXOEDGE_DEFAULT   0x00000000UL
 
#define _CMU_IFS_LFXOEDGE_MASK   0x8000000UL
 
#define _CMU_IFS_LFXOEDGE_SHIFT   27
 
#define _CMU_IFS_LFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_LFXORDY_MASK   0x8UL
 
#define _CMU_IFS_LFXORDY_SHIFT   3
 
#define _CMU_IFS_MASK   0xB803EB7FUL
 
#define _CMU_IFS_RESETVALUE   0x00000000UL
 
#define _CMU_IFS_ULFRCOEDGE_DEFAULT   0x00000000UL
 
#define _CMU_IFS_ULFRCOEDGE_MASK   0x20000000UL
 
#define _CMU_IFS_ULFRCOEDGE_SHIFT   29
 
#define _CMU_LFACLKEN0_LCD_DEFAULT   0x00000000UL
 
#define _CMU_LFACLKEN0_LCD_MASK   0x4UL
 
#define _CMU_LFACLKEN0_LCD_SHIFT   2
 
#define _CMU_LFACLKEN0_LESENSE_DEFAULT   0x00000000UL
 
#define _CMU_LFACLKEN0_LESENSE_MASK   0x1UL
 
#define _CMU_LFACLKEN0_LESENSE_SHIFT   0
 
#define _CMU_LFACLKEN0_LETIMER0_DEFAULT   0x00000000UL
 
#define _CMU_LFACLKEN0_LETIMER0_MASK   0x2UL
 
#define _CMU_LFACLKEN0_LETIMER0_SHIFT   1
 
#define _CMU_LFACLKEN0_MASK   0x00000007UL
 
#define _CMU_LFACLKEN0_RESETVALUE   0x00000000UL
 
#define _CMU_LFACLKSEL_LFA_DEFAULT   0x00000000UL
 
#define _CMU_LFACLKSEL_LFA_DISABLED   0x00000000UL
 
#define _CMU_LFACLKSEL_LFA_LFRCO   0x00000001UL
 
#define _CMU_LFACLKSEL_LFA_LFXO   0x00000002UL
 
#define _CMU_LFACLKSEL_LFA_MASK   0x7UL
 
#define _CMU_LFACLKSEL_LFA_SHIFT   0
 
#define _CMU_LFACLKSEL_LFA_ULFRCO   0x00000004UL
 
#define _CMU_LFACLKSEL_MASK   0x00000007UL
 
#define _CMU_LFACLKSEL_RESETVALUE   0x00000000UL
 
#define _CMU_LFAPRESC0_LCD_DIV1   0x00000000UL
 
#define _CMU_LFAPRESC0_LCD_DIV128   0x00000007UL
 
#define _CMU_LFAPRESC0_LCD_DIV16   0x00000004UL
 
#define _CMU_LFAPRESC0_LCD_DIV2   0x00000001UL
 
#define _CMU_LFAPRESC0_LCD_DIV32   0x00000005UL
 
#define _CMU_LFAPRESC0_LCD_DIV4   0x00000002UL
 
#define _CMU_LFAPRESC0_LCD_DIV64   0x00000006UL
 
#define _CMU_LFAPRESC0_LCD_DIV8   0x00000003UL
 
#define _CMU_LFAPRESC0_LCD_MASK   0x700UL
 
#define _CMU_LFAPRESC0_LCD_SHIFT   8
 
#define _CMU_LFAPRESC0_LESENSE_DIV1   0x00000000UL
 
#define _CMU_LFAPRESC0_LESENSE_DIV2   0x00000001UL
 
#define _CMU_LFAPRESC0_LESENSE_DIV4   0x00000002UL
 
#define _CMU_LFAPRESC0_LESENSE_DIV8   0x00000003UL
 
#define _CMU_LFAPRESC0_LESENSE_MASK   0x3UL
 
#define _CMU_LFAPRESC0_LESENSE_SHIFT   0
 
#define _CMU_LFAPRESC0_LETIMER0_DIV1   0x00000000UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV1024   0x0000000AUL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV128   0x00000007UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV16   0x00000004UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV16384   0x0000000EUL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV2   0x00000001UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV2048   0x0000000BUL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV256   0x00000008UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV32   0x00000005UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV32768   0x0000000FUL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV4   0x00000002UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV4096   0x0000000CUL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV512   0x00000009UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV64   0x00000006UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV8   0x00000003UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV8192   0x0000000DUL
 
#define _CMU_LFAPRESC0_LETIMER0_MASK   0xF0UL
 
#define _CMU_LFAPRESC0_LETIMER0_SHIFT   4
 
#define _CMU_LFAPRESC0_MASK   0x000007F3UL
 
#define _CMU_LFAPRESC0_RESETVALUE   0x00000000UL
 
#define _CMU_LFBCLKEN0_CSEN_DEFAULT   0x00000000UL
 
#define _CMU_LFBCLKEN0_CSEN_MASK   0x4UL
 
#define _CMU_LFBCLKEN0_CSEN_SHIFT   2
 
#define _CMU_LFBCLKEN0_LEUART0_DEFAULT   0x00000000UL
 
#define _CMU_LFBCLKEN0_LEUART0_MASK   0x2UL
 
#define _CMU_LFBCLKEN0_LEUART0_SHIFT   1
 
#define _CMU_LFBCLKEN0_MASK   0x00000007UL
 
#define _CMU_LFBCLKEN0_RESETVALUE   0x00000000UL
 
#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT   0x00000000UL
 
#define _CMU_LFBCLKEN0_SYSTICK_MASK   0x1UL
 
#define _CMU_LFBCLKEN0_SYSTICK_SHIFT   0
 
#define _CMU_LFBCLKSEL_LFB_DEFAULT   0x00000000UL
 
#define _CMU_LFBCLKSEL_LFB_DISABLED   0x00000000UL
 
#define _CMU_LFBCLKSEL_LFB_HFCLKLE   0x00000003UL
 
#define _CMU_LFBCLKSEL_LFB_LFRCO   0x00000001UL
 
#define _CMU_LFBCLKSEL_LFB_LFXO   0x00000002UL
 
#define _CMU_LFBCLKSEL_LFB_MASK   0x7UL
 
#define _CMU_LFBCLKSEL_LFB_SHIFT   0
 
#define _CMU_LFBCLKSEL_LFB_ULFRCO   0x00000004UL
 
#define _CMU_LFBCLKSEL_MASK   0x00000007UL
 
#define _CMU_LFBCLKSEL_RESETVALUE   0x00000000UL
 
#define _CMU_LFBPRESC0_CSEN_DIV128   0x00000003UL
 
#define _CMU_LFBPRESC0_CSEN_DIV16   0x00000000UL
 
#define _CMU_LFBPRESC0_CSEN_DIV32   0x00000001UL
 
#define _CMU_LFBPRESC0_CSEN_DIV64   0x00000002UL
 
#define _CMU_LFBPRESC0_CSEN_MASK   0x300UL
 
#define _CMU_LFBPRESC0_CSEN_SHIFT   8
 
#define _CMU_LFBPRESC0_LEUART0_DIV1   0x00000000UL
 
#define _CMU_LFBPRESC0_LEUART0_DIV2   0x00000001UL
 
#define _CMU_LFBPRESC0_LEUART0_DIV4   0x00000002UL
 
#define _CMU_LFBPRESC0_LEUART0_DIV8   0x00000003UL
 
#define _CMU_LFBPRESC0_LEUART0_MASK   0x30UL
 
#define _CMU_LFBPRESC0_LEUART0_SHIFT   4
 
#define _CMU_LFBPRESC0_MASK   0x0000033FUL
 
#define _CMU_LFBPRESC0_RESETVALUE   0x00000000UL
 
#define _CMU_LFBPRESC0_SYSTICK_DIV1   0x00000000UL
 
#define _CMU_LFBPRESC0_SYSTICK_MASK   0xFUL
 
#define _CMU_LFBPRESC0_SYSTICK_SHIFT   0
 
#define _CMU_LFECLKEN0_MASK   0x00000001UL
 
#define _CMU_LFECLKEN0_RESETVALUE   0x00000000UL
 
#define _CMU_LFECLKEN0_RTCC_DEFAULT   0x00000000UL
 
#define _CMU_LFECLKEN0_RTCC_MASK   0x1UL
 
#define _CMU_LFECLKEN0_RTCC_SHIFT   0
 
#define _CMU_LFECLKSEL_LFE_DEFAULT   0x00000000UL
 
#define _CMU_LFECLKSEL_LFE_DISABLED   0x00000000UL
 
#define _CMU_LFECLKSEL_LFE_LFRCO   0x00000001UL
 
#define _CMU_LFECLKSEL_LFE_LFXO   0x00000002UL
 
#define _CMU_LFECLKSEL_LFE_MASK   0x7UL
 
#define _CMU_LFECLKSEL_LFE_SHIFT   0
 
#define _CMU_LFECLKSEL_LFE_ULFRCO   0x00000004UL
 
#define _CMU_LFECLKSEL_MASK   0x00000007UL
 
#define _CMU_LFECLKSEL_RESETVALUE   0x00000000UL
 
#define _CMU_LFEPRESC0_MASK   0x00000003UL
 
#define _CMU_LFEPRESC0_RESETVALUE   0x00000000UL
 
#define _CMU_LFEPRESC0_RTCC_DIV1   0x00000000UL
 
#define _CMU_LFEPRESC0_RTCC_DIV2   0x00000001UL
 
#define _CMU_LFEPRESC0_RTCC_DIV4   0x00000002UL
 
#define _CMU_LFEPRESC0_RTCC_MASK   0x3UL
 
#define _CMU_LFEPRESC0_RTCC_SHIFT   0
 
#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT   0x00000001UL
 
#define _CMU_LFRCOCTRL_ENCHOP_MASK   0x20000UL
 
#define _CMU_LFRCOCTRL_ENCHOP_SHIFT   17
 
#define _CMU_LFRCOCTRL_ENDEM_DEFAULT   0x00000001UL
 
#define _CMU_LFRCOCTRL_ENDEM_MASK   0x40000UL
 
#define _CMU_LFRCOCTRL_ENDEM_SHIFT   18
 
#define _CMU_LFRCOCTRL_ENVREF_DEFAULT   0x00000000UL
 
#define _CMU_LFRCOCTRL_ENVREF_MASK   0x10000UL
 
#define _CMU_LFRCOCTRL_ENVREF_SHIFT   16
 
#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT   0x00000008UL
 
#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK   0xF0000000UL
 
#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT   28
 
#define _CMU_LFRCOCTRL_MASK   0xF33701FFUL
 
#define _CMU_LFRCOCTRL_RESETVALUE   0x81060100UL
 
#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES   0x00000001UL
 
#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES   0x00000000UL
 
#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES   0x00000002UL
 
#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT   0x00000001UL
 
#define _CMU_LFRCOCTRL_TIMEOUT_MASK   0x3000000UL
 
#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT   24
 
#define _CMU_LFRCOCTRL_TUNING_DEFAULT   0x00000100UL
 
#define _CMU_LFRCOCTRL_TUNING_MASK   0x1FFUL
 
#define _CMU_LFRCOCTRL_TUNING_SHIFT   0
 
#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES   0x00000002UL
 
#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES   0x00000003UL
 
#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES   0x00000000UL
 
#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES   0x00000001UL
 
#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT   0x00000000UL
 
#define _CMU_LFRCOCTRL_VREFUPDATE_MASK   0x300000UL
 
#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT   20
 
#define _CMU_LFXOCTRL_AGC_DEFAULT   0x00000001UL
 
#define _CMU_LFXOCTRL_AGC_MASK   0x8000UL
 
#define _CMU_LFXOCTRL_AGC_SHIFT   15
 
#define _CMU_LFXOCTRL_BUFCUR_DEFAULT   0x00000000UL
 
#define _CMU_LFXOCTRL_BUFCUR_MASK   0x100000UL
 
#define _CMU_LFXOCTRL_BUFCUR_SHIFT   20
 
#define _CMU_LFXOCTRL_CUR_DEFAULT   0x00000000UL
 
#define _CMU_LFXOCTRL_CUR_MASK   0x30000UL
 
#define _CMU_LFXOCTRL_CUR_SHIFT   16
 
#define _CMU_LFXOCTRL_GAIN_DEFAULT   0x00000002UL
 
#define _CMU_LFXOCTRL_GAIN_MASK   0x1800UL
 
#define _CMU_LFXOCTRL_GAIN_SHIFT   11
 
#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT   0x00000000UL
 
#define _CMU_LFXOCTRL_HIGHAMPL_MASK   0x4000UL
 
#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT   14
 
#define _CMU_LFXOCTRL_MASK   0x0713DB7FUL
 
#define _CMU_LFXOCTRL_MODE_BUFEXTCLK   0x00000001UL
 
#define _CMU_LFXOCTRL_MODE_DEFAULT   0x00000000UL
 
#define _CMU_LFXOCTRL_MODE_DIGEXTCLK   0x00000002UL
 
#define _CMU_LFXOCTRL_MODE_MASK   0x300UL
 
#define _CMU_LFXOCTRL_MODE_SHIFT   8
 
#define _CMU_LFXOCTRL_MODE_XTAL   0x00000000UL
 
#define _CMU_LFXOCTRL_RESETVALUE   0x07009000UL
 
#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES   0x00000006UL
 
#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES   0x00000002UL
 
#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES   0x00000001UL
 
#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES   0x00000000UL
 
#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES   0x00000003UL
 
#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES   0x00000007UL
 
#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES   0x00000004UL
 
#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES   0x00000005UL
 
#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT   0x00000007UL
 
#define _CMU_LFXOCTRL_TIMEOUT_MASK   0x7000000UL
 
#define _CMU_LFXOCTRL_TIMEOUT_SHIFT   24
 
#define _CMU_LFXOCTRL_TUNING_DEFAULT   0x00000000UL
 
#define _CMU_LFXOCTRL_TUNING_MASK   0x7FUL
 
#define _CMU_LFXOCTRL_TUNING_SHIFT   0
 
#define _CMU_LOCK_LOCKKEY_DEFAULT   0x00000000UL
 
#define _CMU_LOCK_LOCKKEY_LOCK   0x00000000UL
 
#define _CMU_LOCK_LOCKKEY_LOCKED   0x00000001UL
 
#define _CMU_LOCK_LOCKKEY_MASK   0xFFFFUL
 
#define _CMU_LOCK_LOCKKEY_SHIFT   0
 
#define _CMU_LOCK_LOCKKEY_UNLOCK   0x0000580EUL
 
#define _CMU_LOCK_LOCKKEY_UNLOCKED   0x00000000UL
 
#define _CMU_LOCK_MASK   0x0000FFFFUL
 
#define _CMU_LOCK_RESETVALUE   0x00000000UL
 
#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_AUXHFRCODIS_MASK   0x20UL
 
#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT   5
 
#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_AUXHFRCOEN_MASK   0x10UL
 
#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT   4
 
#define _CMU_OSCENCMD_DPLLDIS_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_DPLLDIS_MASK   0x2000UL
 
#define _CMU_OSCENCMD_DPLLDIS_SHIFT   13
 
#define _CMU_OSCENCMD_DPLLEN_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_DPLLEN_MASK   0x1000UL
 
#define _CMU_OSCENCMD_DPLLEN_SHIFT   12
 
#define _CMU_OSCENCMD_HFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_HFRCODIS_MASK   0x2UL
 
#define _CMU_OSCENCMD_HFRCODIS_SHIFT   1
 
#define _CMU_OSCENCMD_HFRCOEN_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_HFRCOEN_MASK   0x1UL
 
#define _CMU_OSCENCMD_HFRCOEN_SHIFT   0
 
#define _CMU_OSCENCMD_HFXODIS_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_HFXODIS_MASK   0x8UL
 
#define _CMU_OSCENCMD_HFXODIS_SHIFT   3
 
#define _CMU_OSCENCMD_HFXOEN_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_HFXOEN_MASK   0x4UL
 
#define _CMU_OSCENCMD_HFXOEN_SHIFT   2
 
#define _CMU_OSCENCMD_LFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_LFRCODIS_MASK   0x80UL
 
#define _CMU_OSCENCMD_LFRCODIS_SHIFT   7
 
#define _CMU_OSCENCMD_LFRCOEN_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_LFRCOEN_MASK   0x40UL
 
#define _CMU_OSCENCMD_LFRCOEN_SHIFT   6
 
#define _CMU_OSCENCMD_LFXODIS_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_LFXODIS_MASK   0x200UL
 
#define _CMU_OSCENCMD_LFXODIS_SHIFT   9
 
#define _CMU_OSCENCMD_LFXOEN_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_LFXOEN_MASK   0x100UL
 
#define _CMU_OSCENCMD_LFXOEN_SHIFT   8
 
#define _CMU_OSCENCMD_MASK   0x000033FFUL
 
#define _CMU_OSCENCMD_RESETVALUE   0x00000000UL
 
#define _CMU_PCNTCTRL_MASK   0x00000003UL
 
#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT   0x00000000UL
 
#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK   0x1UL
 
#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT   0
 
#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT   0x00000000UL
 
#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK   0x00000000UL
 
#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK   0x2UL
 
#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0   0x00000001UL
 
#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT   1
 
#define _CMU_PCNTCTRL_RESETVALUE   0x00000000UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT   0x00000000UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0   0x00000000UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1   0x00000001UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2   0x00000002UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3   0x00000003UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4   0x00000004UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5   0x00000005UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK   0x7UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT   0
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT   0x00000000UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0   0x00000000UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1   0x00000001UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2   0x00000002UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3   0x00000003UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4   0x00000004UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5   0x00000005UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK   0x700UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT   8
 
#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT   0x00000000UL
 
#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0   0x00000000UL
 
#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1   0x00000001UL
 
#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2   0x00000002UL
 
#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3   0x00000003UL
 
#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4   0x00000004UL
 
#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5   0x00000005UL
 
#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK   0x70000UL
 
#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT   16
 
#define _CMU_ROUTELOC0_MASK   0x00070707UL
 
#define _CMU_ROUTELOC0_RESETVALUE   0x00000000UL
 
#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT   0x00000000UL
 
#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0   0x00000000UL
 
#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1   0x00000001UL
 
#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2   0x00000002UL
 
#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3   0x00000003UL
 
#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4   0x00000004UL
 
#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5   0x00000005UL
 
#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6   0x00000006UL
 
#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7   0x00000007UL
 
#define _CMU_ROUTELOC1_CLKIN0LOC_MASK   0x7UL
 
#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT   0
 
#define _CMU_ROUTELOC1_MASK   0x00000007UL
 
#define _CMU_ROUTELOC1_RESETVALUE   0x00000000UL
 
#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT   0x00000000UL
 
#define _CMU_ROUTEPEN_CLKIN0PEN_MASK   0x10000000UL
 
#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT   28
 
#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT   0x00000000UL
 
#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK   0x1UL
 
#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT   0
 
#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT   0x00000000UL
 
#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK   0x2UL
 
#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT   1
 
#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT   0x00000000UL
 
#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK   0x4UL
 
#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT   2
 
#define _CMU_ROUTEPEN_MASK   0x10000007UL
 
#define _CMU_ROUTEPEN_RESETVALUE   0x00000000UL
 
#define _CMU_STATUS_AUXHFRCOENS_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_AUXHFRCOENS_MASK   0x10UL
 
#define _CMU_STATUS_AUXHFRCOENS_SHIFT   4
 
#define _CMU_STATUS_AUXHFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_AUXHFRCORDY_MASK   0x20UL
 
#define _CMU_STATUS_AUXHFRCORDY_SHIFT   5
 
#define _CMU_STATUS_CALRDY_DEFAULT   0x00000001UL
 
#define _CMU_STATUS_CALRDY_MASK   0x10000UL
 
#define _CMU_STATUS_CALRDY_SHIFT   16
 
#define _CMU_STATUS_DPLLENS_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_DPLLENS_MASK   0x1000UL
 
#define _CMU_STATUS_DPLLENS_SHIFT   12
 
#define _CMU_STATUS_DPLLRDY_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_DPLLRDY_MASK   0x2000UL
 
#define _CMU_STATUS_DPLLRDY_SHIFT   13
 
#define _CMU_STATUS_HFRCOENS_DEFAULT   0x00000001UL
 
#define _CMU_STATUS_HFRCOENS_MASK   0x1UL
 
#define _CMU_STATUS_HFRCOENS_SHIFT   0
 
#define _CMU_STATUS_HFRCORDY_DEFAULT   0x00000001UL
 
#define _CMU_STATUS_HFRCORDY_MASK   0x2UL
 
#define _CMU_STATUS_HFRCORDY_SHIFT   1
 
#define _CMU_STATUS_HFXOAMPLOW_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_HFXOAMPLOW_MASK   0x2000000UL
 
#define _CMU_STATUS_HFXOAMPLOW_SHIFT   25
 
#define _CMU_STATUS_HFXOENS_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_HFXOENS_MASK   0x4UL
 
#define _CMU_STATUS_HFXOENS_SHIFT   2
 
#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_HFXOPEAKDETRDY_MASK   0x400000UL
 
#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT   22
 
#define _CMU_STATUS_HFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_HFXORDY_MASK   0x8UL
 
#define _CMU_STATUS_HFXORDY_SHIFT   3
 
#define _CMU_STATUS_LFRCOENS_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_LFRCOENS_MASK   0x40UL
 
#define _CMU_STATUS_LFRCOENS_SHIFT   6
 
#define _CMU_STATUS_LFRCOPHASE_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_LFRCOPHASE_MASK   0x10000000UL
 
#define _CMU_STATUS_LFRCOPHASE_SHIFT   28
 
#define _CMU_STATUS_LFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_LFRCORDY_MASK   0x80UL
 
#define _CMU_STATUS_LFRCORDY_SHIFT   7
 
#define _CMU_STATUS_LFXOENS_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_LFXOENS_MASK   0x100UL
 
#define _CMU_STATUS_LFXOENS_SHIFT   8
 
#define _CMU_STATUS_LFXOPHASE_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_LFXOPHASE_MASK   0x8000000UL
 
#define _CMU_STATUS_LFXOPHASE_SHIFT   27
 
#define _CMU_STATUS_LFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_LFXORDY_MASK   0x200UL
 
#define _CMU_STATUS_LFXORDY_SHIFT   9
 
#define _CMU_STATUS_MASK   0x3A4133FFUL
 
#define _CMU_STATUS_RESETVALUE   0x00010003UL
 
#define _CMU_STATUS_ULFRCOPHASE_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_ULFRCOPHASE_MASK   0x20000000UL
 
#define _CMU_STATUS_ULFRCOPHASE_SHIFT   29
 
#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK   0x2000000UL
 
#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT   25
 
#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_HFRCOBSY_MASK   0x1000000UL
 
#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT   24
 
#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_HFXOBSY_MASK   0x10000000UL
 
#define _CMU_SYNCBUSY_HFXOBSY_SHIFT   28
 
#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFACLKEN0_MASK   0x1UL
 
#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT   0
 
#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFAPRESC0_MASK   0x4UL
 
#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT   2
 
#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFBCLKEN0_MASK   0x10UL
 
#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT   4
 
#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFBPRESC0_MASK   0x40UL
 
#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT   6
 
#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFECLKEN0_MASK   0x10000UL
 
#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT   16
 
#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFEPRESC0_MASK   0x40000UL
 
#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT   18
 
#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFRCOBSY_MASK   0x4000000UL
 
#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT   26
 
#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK   0x8000000UL
 
#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT   27
 
#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFXOBSY_MASK   0x20000000UL
 
#define _CMU_SYNCBUSY_LFXOBSY_SHIFT   29
 
#define _CMU_SYNCBUSY_MASK   0x3F050055UL
 
#define _CMU_SYNCBUSY_RESETVALUE   0x00000000UL
 
#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT   (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0)
 
#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION   (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0)
 
#define CMU_ADCCTRL_ADC0CLKINV   (0x1UL << 8)
 
#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT   (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8)
 
#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO   (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4)
 
#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT   (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4)
 
#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED   (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4)
 
#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK   (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4)
 
#define CMU_ADCCTRL_ADC0CLKSEL_HFXO   (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4)
 
#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT   (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25)
 
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1   (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25)
 
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2   (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25)
 
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4   (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25)
 
#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT   (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21)
 
#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT   (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8)
 
#define CMU_AUXHFRCOCTRL_FINETUNINGEN   (0x1UL << 27)
 
#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT   (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27)
 
#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT   (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16)
 
#define CMU_AUXHFRCOCTRL_LDOHP   (0x1UL << 24)
 
#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT   (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24)
 
#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT   (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
 
#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT   (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28)
 
#define CMU_CALCNT_CALCNT_DEFAULT   (_CMU_CALCNT_CALCNT_DEFAULT << 0)
 
#define CMU_CALCTRL_CONT   (0x1UL << 8)
 
#define CMU_CALCTRL_CONT_DEFAULT   (_CMU_CALCTRL_CONT_DEFAULT << 8)
 
#define CMU_CALCTRL_DOWNSEL_AUXHFRCO   (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4)
 
#define CMU_CALCTRL_DOWNSEL_DEFAULT   (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4)
 
#define CMU_CALCTRL_DOWNSEL_HFCLK   (_CMU_CALCTRL_DOWNSEL_HFCLK << 4)
 
#define CMU_CALCTRL_DOWNSEL_HFRCO   (_CMU_CALCTRL_DOWNSEL_HFRCO << 4)
 
#define CMU_CALCTRL_DOWNSEL_HFXO   (_CMU_CALCTRL_DOWNSEL_HFXO << 4)
 
#define CMU_CALCTRL_DOWNSEL_LFRCO   (_CMU_CALCTRL_DOWNSEL_LFRCO << 4)
 
#define CMU_CALCTRL_DOWNSEL_LFXO   (_CMU_CALCTRL_DOWNSEL_LFXO << 4)
 
#define CMU_CALCTRL_DOWNSEL_PRS   (_CMU_CALCTRL_DOWNSEL_PRS << 4)
 
#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT   (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24)
 
#define CMU_CALCTRL_PRSUPSEL_DEFAULT   (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH0   (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH1   (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH2   (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH3   (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH4   (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH5   (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH6   (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH7   (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16)
 
#define CMU_CALCTRL_UPSEL_AUXHFRCO   (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
 
#define CMU_CALCTRL_UPSEL_DEFAULT   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
 
#define CMU_CALCTRL_UPSEL_HFRCO   (_CMU_CALCTRL_UPSEL_HFRCO << 0)
 
#define CMU_CALCTRL_UPSEL_HFXO   (_CMU_CALCTRL_UPSEL_HFXO << 0)
 
#define CMU_CALCTRL_UPSEL_LFRCO   (_CMU_CALCTRL_UPSEL_LFRCO << 0)
 
#define CMU_CALCTRL_UPSEL_LFXO   (_CMU_CALCTRL_UPSEL_LFXO << 0)
 
#define CMU_CALCTRL_UPSEL_PRS   (_CMU_CALCTRL_UPSEL_PRS << 0)
 
#define CMU_CMD_CALSTART   (0x1UL << 0)
 
#define CMU_CMD_CALSTART_DEFAULT   (_CMU_CMD_CALSTART_DEFAULT << 0)
 
#define CMU_CMD_CALSTOP   (0x1UL << 1)
 
#define CMU_CMD_CALSTOP_DEFAULT   (_CMU_CMD_CALSTOP_DEFAULT << 1)
 
#define CMU_CMD_HFXOPEAKDETSTART   (0x1UL << 4)
 
#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT   (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4)
 
#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ   (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0)
 
#define CMU_CTRL_CLKOUTSEL0_DEFAULT   (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0)
 
#define CMU_CTRL_CLKOUTSEL0_DISABLED   (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0)
 
#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK   (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0)
 
#define CMU_CTRL_CLKOUTSEL0_HFRCOQ   (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0)
 
#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK   (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0)
 
#define CMU_CTRL_CLKOUTSEL0_HFXO   (_CMU_CTRL_CLKOUTSEL0_HFXO << 0)
 
#define CMU_CTRL_CLKOUTSEL0_HFXOQ   (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0)
 
#define CMU_CTRL_CLKOUTSEL0_LFRCO   (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0)
 
#define CMU_CTRL_CLKOUTSEL0_LFRCOQ   (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0)
 
#define CMU_CTRL_CLKOUTSEL0_LFXO   (_CMU_CTRL_CLKOUTSEL0_LFXO << 0)
 
#define CMU_CTRL_CLKOUTSEL0_LFXOQ   (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0)
 
#define CMU_CTRL_CLKOUTSEL0_ULFRCO   (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0)
 
#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ   (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0)
 
#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ   (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5)
 
#define CMU_CTRL_CLKOUTSEL1_DEFAULT   (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5)
 
#define CMU_CTRL_CLKOUTSEL1_DISABLED   (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5)
 
#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK   (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5)
 
#define CMU_CTRL_CLKOUTSEL1_HFRCOQ   (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5)
 
#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK   (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5)
 
#define CMU_CTRL_CLKOUTSEL1_HFXO   (_CMU_CTRL_CLKOUTSEL1_HFXO << 5)
 
#define CMU_CTRL_CLKOUTSEL1_HFXOQ   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5)
 
#define CMU_CTRL_CLKOUTSEL1_LFRCO   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5)
 
#define CMU_CTRL_CLKOUTSEL1_LFRCOQ   (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5)
 
#define CMU_CTRL_CLKOUTSEL1_LFXO   (_CMU_CTRL_CLKOUTSEL1_LFXO << 5)
 
#define CMU_CTRL_CLKOUTSEL1_LFXOQ   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5)
 
#define CMU_CTRL_CLKOUTSEL1_ULFRCO   (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5)
 
#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ   (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5)
 
#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ   (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10)
 
#define CMU_CTRL_CLKOUTSEL2_DEFAULT   (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10)
 
#define CMU_CTRL_CLKOUTSEL2_DISABLED   (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10)
 
#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK   (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10)
 
#define CMU_CTRL_CLKOUTSEL2_HFRCOQ   (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10)
 
#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK   (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10)
 
#define CMU_CTRL_CLKOUTSEL2_HFXO   (_CMU_CTRL_CLKOUTSEL2_HFXO << 10)
 
#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q   (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10)
 
#define CMU_CTRL_CLKOUTSEL2_HFXOQ   (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10)
 
#define CMU_CTRL_CLKOUTSEL2_LFRCO   (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10)
 
#define CMU_CTRL_CLKOUTSEL2_LFRCOQ   (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10)
 
#define CMU_CTRL_CLKOUTSEL2_LFXO   (_CMU_CTRL_CLKOUTSEL2_LFXO << 10)
 
#define CMU_CTRL_CLKOUTSEL2_LFXOQ   (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10)
 
#define CMU_CTRL_CLKOUTSEL2_ULFRCO   (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10)
 
#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ   (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10)
 
#define CMU_CTRL_HFPERCLKEN   (0x1UL << 20)
 
#define CMU_CTRL_HFPERCLKEN_DEFAULT   (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20)
 
#define CMU_CTRL_WSHFLE   (0x1UL << 16)
 
#define CMU_CTRL_WSHFLE_DEFAULT   (_CMU_CTRL_WSHFLE_DEFAULT << 16)
 
#define CMU_DBGCLKSEL_DBG_AUXHFRCO   (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0)
 
#define CMU_DBGCLKSEL_DBG_DEFAULT   (_CMU_DBGCLKSEL_DBG_DEFAULT << 0)
 
#define CMU_DBGCLKSEL_DBG_HFCLK   (_CMU_DBGCLKSEL_DBG_HFCLK << 0)
 
#define CMU_DBGCLKSEL_DBG_HFRCODIV2   (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0)
 
#define CMU_DPLLCTRL1_M_DEFAULT   (_CMU_DPLLCTRL1_M_DEFAULT << 0)
 
#define CMU_DPLLCTRL1_N_DEFAULT   (_CMU_DPLLCTRL1_N_DEFAULT << 16)
 
#define CMU_DPLLCTRL_AUTORECOVER   (0x1UL << 2)
 
#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT   (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2)
 
#define CMU_DPLLCTRL_DITHEN   (0x1UL << 6)
 
#define CMU_DPLLCTRL_DITHEN_DEFAULT   (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6)
 
#define CMU_DPLLCTRL_EDGESEL   (0x1UL << 1)
 
#define CMU_DPLLCTRL_EDGESEL_DEFAULT   (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1)
 
#define CMU_DPLLCTRL_EDGESEL_FALL   (_CMU_DPLLCTRL_EDGESEL_FALL << 1)
 
#define CMU_DPLLCTRL_EDGESEL_RISE   (_CMU_DPLLCTRL_EDGESEL_RISE << 1)
 
#define CMU_DPLLCTRL_MODE   (0x1UL << 0)
 
#define CMU_DPLLCTRL_MODE_DEFAULT   (_CMU_DPLLCTRL_MODE_DEFAULT << 0)
 
#define CMU_DPLLCTRL_MODE_FREQLL   (_CMU_DPLLCTRL_MODE_FREQLL << 0)
 
#define CMU_DPLLCTRL_MODE_PHASELL   (_CMU_DPLLCTRL_MODE_PHASELL << 0)
 
#define CMU_DPLLCTRL_REFSEL_CLKIN0   (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3)
 
#define CMU_DPLLCTRL_REFSEL_DEFAULT   (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3)
 
#define CMU_DPLLCTRL_REFSEL_HFXO   (_CMU_DPLLCTRL_REFSEL_HFXO << 3)
 
#define CMU_DPLLCTRL_REFSEL_LFXO   (_CMU_DPLLCTRL_REFSEL_LFXO << 3)
 
#define CMU_FREEZE_REGFREEZE   (0x1UL << 0)
 
#define CMU_FREEZE_REGFREEZE_DEFAULT   (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
 
#define CMU_FREEZE_REGFREEZE_FREEZE   (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
 
#define CMU_FREEZE_REGFREEZE_UPDATE   (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
 
#define CMU_HFBUSCLKEN0_CRYPTO0   (0x1UL << 1)
 
#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT   (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1)
 
#define CMU_HFBUSCLKEN0_GPCRC   (0x1UL << 5)
 
#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT   (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 5)
 
#define CMU_HFBUSCLKEN0_GPIO   (0x1UL << 2)
 
#define CMU_HFBUSCLKEN0_GPIO_DEFAULT   (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 2)
 
#define CMU_HFBUSCLKEN0_LDMA   (0x1UL << 4)
 
#define CMU_HFBUSCLKEN0_LDMA_DEFAULT   (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 4)
 
#define CMU_HFBUSCLKEN0_LE   (0x1UL << 0)
 
#define CMU_HFBUSCLKEN0_LE_DEFAULT   (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0)
 
#define CMU_HFBUSCLKEN0_PRS   (0x1UL << 3)
 
#define CMU_HFBUSCLKEN0_PRS_DEFAULT   (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 3)
 
#define CMU_HFBUSPRESC_PRESC_DEFAULT   (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8)
 
#define CMU_HFBUSPRESC_PRESC_NODIVISION   (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8)
 
#define CMU_HFCLKSEL_HF_CLKIN0   (_CMU_HFCLKSEL_HF_CLKIN0 << 0)
 
#define CMU_HFCLKSEL_HF_DEFAULT   (_CMU_HFCLKSEL_HF_DEFAULT << 0)
 
#define CMU_HFCLKSEL_HF_HFRCO   (_CMU_HFCLKSEL_HF_HFRCO << 0)
 
#define CMU_HFCLKSEL_HF_HFRCODIV2   (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0)
 
#define CMU_HFCLKSEL_HF_HFXO   (_CMU_HFCLKSEL_HF_HFXO << 0)
 
#define CMU_HFCLKSEL_HF_LFRCO   (_CMU_HFCLKSEL_HF_LFRCO << 0)
 
#define CMU_HFCLKSEL_HF_LFXO   (_CMU_HFCLKSEL_HF_LFXO << 0)
 
#define CMU_HFCLKSTATUS_SELECTED_CLKIN0   (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0)
 
#define CMU_HFCLKSTATUS_SELECTED_DEFAULT   (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0)
 
#define CMU_HFCLKSTATUS_SELECTED_HFRCO   (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0)
 
#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2   (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0)
 
#define CMU_HFCLKSTATUS_SELECTED_HFXO   (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0)
 
#define CMU_HFCLKSTATUS_SELECTED_LFRCO   (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0)
 
#define CMU_HFCLKSTATUS_SELECTED_LFXO   (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0)
 
#define CMU_HFCOREPRESC_PRESC_DEFAULT   (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8)
 
#define CMU_HFCOREPRESC_PRESC_NODIVISION   (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8)
 
#define CMU_HFEXPPRESC_PRESC_DEFAULT   (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8)
 
#define CMU_HFEXPPRESC_PRESC_NODIVISION   (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8)
 
#define CMU_HFPERCLKEN0_ACMP0   (0x1UL << 8)
 
#define CMU_HFPERCLKEN0_ACMP0_DEFAULT   (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 8)
 
#define CMU_HFPERCLKEN0_ACMP1   (0x1UL << 9)
 
#define CMU_HFPERCLKEN0_ACMP1_DEFAULT   (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 9)
 
#define CMU_HFPERCLKEN0_ADC0   (0x1UL << 11)
 
#define CMU_HFPERCLKEN0_ADC0_DEFAULT   (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 11)
 
#define CMU_HFPERCLKEN0_CRYOTIMER   (0x1UL << 10)
 
#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT   (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 10)
 
#define CMU_HFPERCLKEN0_I2C0   (0x1UL << 6)
 
#define CMU_HFPERCLKEN0_I2C0_DEFAULT   (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 6)
 
#define CMU_HFPERCLKEN0_I2C1   (0x1UL << 7)
 
#define CMU_HFPERCLKEN0_I2C1_DEFAULT   (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 7)
 
#define CMU_HFPERCLKEN0_TIMER0   (0x1UL << 4)
 
#define CMU_HFPERCLKEN0_TIMER0_DEFAULT   (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 4)
 
#define CMU_HFPERCLKEN0_TIMER1   (0x1UL << 5)
 
#define CMU_HFPERCLKEN0_TIMER1_DEFAULT   (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 5)
 
#define CMU_HFPERCLKEN0_TRNG0   (0x1UL << 12)
 
#define CMU_HFPERCLKEN0_TRNG0_DEFAULT   (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 12)
 
#define CMU_HFPERCLKEN0_USART0   (0x1UL << 0)
 
#define CMU_HFPERCLKEN0_USART0_DEFAULT   (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0)
 
#define CMU_HFPERCLKEN0_USART1   (0x1UL << 1)
 
#define CMU_HFPERCLKEN0_USART1_DEFAULT   (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1)
 
#define CMU_HFPERCLKEN0_USART2   (0x1UL << 2)
 
#define CMU_HFPERCLKEN0_USART2_DEFAULT   (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2)
 
#define CMU_HFPERCLKEN0_USART3   (0x1UL << 3)
 
#define CMU_HFPERCLKEN0_USART3_DEFAULT   (_CMU_HFPERCLKEN0_USART3_DEFAULT << 3)
 
#define CMU_HFPERCLKEN1_CAN0   (0x1UL << 3)
 
#define CMU_HFPERCLKEN1_CAN0_DEFAULT   (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 3)
 
#define CMU_HFPERCLKEN1_CSEN   (0x1UL << 5)
 
#define CMU_HFPERCLKEN1_CSEN_DEFAULT   (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 5)
 
#define CMU_HFPERCLKEN1_UART0   (0x1UL << 0)
 
#define CMU_HFPERCLKEN1_UART0_DEFAULT   (_CMU_HFPERCLKEN1_UART0_DEFAULT << 0)
 
#define CMU_HFPERCLKEN1_VDAC0   (0x1UL << 4)
 
#define CMU_HFPERCLKEN1_VDAC0_DEFAULT   (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 4)
 
#define CMU_HFPERCLKEN1_WTIMER0   (0x1UL << 1)
 
#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT   (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 1)
 
#define CMU_HFPERCLKEN1_WTIMER1   (0x1UL << 2)
 
#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT   (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 2)
 
#define CMU_HFPERPRESC_PRESC_DEFAULT   (_CMU_HFPERPRESC_PRESC_DEFAULT << 8)
 
#define CMU_HFPERPRESC_PRESC_NODIVISION   (_CMU_HFPERPRESC_PRESC_NODIVISION << 8)
 
#define CMU_HFPERPRESCB_PRESC_DEFAULT   (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8)
 
#define CMU_HFPERPRESCB_PRESC_NODIVISION   (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8)
 
#define CMU_HFPERPRESCC_PRESC_DEFAULT   (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8)
 
#define CMU_HFPERPRESCC_PRESC_NODIVISION   (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8)
 
#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT   (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24)
 
#define CMU_HFPRESC_HFCLKLEPRESC_DIV2   (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24)
 
#define CMU_HFPRESC_HFCLKLEPRESC_DIV4   (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24)
 
#define CMU_HFPRESC_HFCLKLEPRESC_DIV8   (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24)
 
#define CMU_HFPRESC_PRESC_DEFAULT   (_CMU_HFPRESC_PRESC_DEFAULT << 8)
 
#define CMU_HFPRESC_PRESC_NODIVISION   (_CMU_HFPRESC_PRESC_NODIVISION << 8)
 
#define CMU_HFRCOCTRL_CLKDIV_DEFAULT   (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25)
 
#define CMU_HFRCOCTRL_CLKDIV_DIV1   (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25)
 
#define CMU_HFRCOCTRL_CLKDIV_DIV2   (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25)
 
#define CMU_HFRCOCTRL_CLKDIV_DIV4   (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25)
 
#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT   (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21)
 
#define CMU_HFRCOCTRL_FINETUNING_DEFAULT   (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8)
 
#define CMU_HFRCOCTRL_FINETUNINGEN   (0x1UL << 27)
 
#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT   (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27)
 
#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT   (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16)
 
#define CMU_HFRCOCTRL_LDOHP   (0x1UL << 24)
 
#define CMU_HFRCOCTRL_LDOHP_DEFAULT   (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24)
 
#define CMU_HFRCOCTRL_TUNING_DEFAULT   (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
 
#define CMU_HFRCOCTRL_VREFTC_DEFAULT   (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28)
 
#define CMU_HFRCOSS_SSAMP_DEFAULT   (_CMU_HFRCOSS_SSAMP_DEFAULT << 0)
 
#define CMU_HFRCOSS_SSINV_DEFAULT   (_CMU_HFRCOSS_SSINV_DEFAULT << 8)
 
#define CMU_HFXOCTRL_AUTOSTARTEM0EM1   (0x1UL << 28)
 
#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT   (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28)
 
#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1   (0x1UL << 29)
 
#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT   (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29)
 
#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT   (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24)
 
#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK   (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0)
 
#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK   (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0)
 
#define CMU_HFXOCTRL_MODE_DEFAULT   (_CMU_HFXOCTRL_MODE_DEFAULT << 0)
 
#define CMU_HFXOCTRL_MODE_DIGEXTCLK   (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0)
 
#define CMU_HFXOCTRL_MODE_XTAL   (_CMU_HFXOCTRL_MODE_XTAL << 0)
 
#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD   (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4)
 
#define CMU_HFXOCTRL_PEAKDETMODE_CMD   (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4)
 
#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT   (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4)
 
#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL   (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4)
 
#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD   (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4)
 
#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT   (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11)
 
#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT   (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0)
 
#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT   (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11)
 
#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT   (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0)
 
#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN   (0x1UL << 26)
 
#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT   (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26)
 
#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN   (0x1UL << 27)
 
#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT   (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4)
 
#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT   (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0)
 
#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT   (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16)
 
#define CMU_HFXOTRIMSTATUS_MONVALID   (0x1UL << 31)
 
#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT   (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31)
 
#define CMU_HFXOTRIMSTATUS_VALID   (0x1UL << 30)
 
#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT   (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30)
 
#define CMU_IEN_AUXHFRCORDY   (0x1UL << 4)
 
#define CMU_IEN_AUXHFRCORDY_DEFAULT   (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
 
#define CMU_IEN_CALOF   (0x1UL << 6)
 
#define CMU_IEN_CALOF_DEFAULT   (_CMU_IEN_CALOF_DEFAULT << 6)
 
#define CMU_IEN_CALRDY   (0x1UL << 5)
 
#define CMU_IEN_CALRDY_DEFAULT   (_CMU_IEN_CALRDY_DEFAULT << 5)
 
#define CMU_IEN_CMUERR   (0x1UL << 31)
 
#define CMU_IEN_CMUERR_DEFAULT   (_CMU_IEN_CMUERR_DEFAULT << 31)
 
#define CMU_IEN_DPLLLOCKFAILHIGH   (0x1UL << 17)
 
#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT   (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17)
 
#define CMU_IEN_DPLLLOCKFAILLOW   (0x1UL << 16)
 
#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT   (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16)
 
#define CMU_IEN_DPLLRDY   (0x1UL << 15)
 
#define CMU_IEN_DPLLRDY_DEFAULT   (_CMU_IEN_DPLLRDY_DEFAULT << 15)
 
#define CMU_IEN_HFRCODIS   (0x1UL << 13)
 
#define CMU_IEN_HFRCODIS_DEFAULT   (_CMU_IEN_HFRCODIS_DEFAULT << 13)
 
#define CMU_IEN_HFRCORDY   (0x1UL << 0)
 
#define CMU_IEN_HFRCORDY_DEFAULT   (_CMU_IEN_HFRCORDY_DEFAULT << 0)
 
#define CMU_IEN_HFXOAUTOSW   (0x1UL << 9)
 
#define CMU_IEN_HFXOAUTOSW_DEFAULT   (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9)
 
#define CMU_IEN_HFXODISERR   (0x1UL << 8)
 
#define CMU_IEN_HFXODISERR_DEFAULT   (_CMU_IEN_HFXODISERR_DEFAULT << 8)
 
#define CMU_IEN_HFXOPEAKDETRDY   (0x1UL << 11)
 
#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT   (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11)
 
#define CMU_IEN_HFXORDY   (0x1UL << 1)
 
#define CMU_IEN_HFXORDY_DEFAULT   (_CMU_IEN_HFXORDY_DEFAULT << 1)
 
#define CMU_IEN_LFRCOEDGE   (0x1UL << 28)
 
#define CMU_IEN_LFRCOEDGE_DEFAULT   (_CMU_IEN_LFRCOEDGE_DEFAULT << 28)
 
#define CMU_IEN_LFRCORDY   (0x1UL << 2)
 
#define CMU_IEN_LFRCORDY_DEFAULT   (_CMU_IEN_LFRCORDY_DEFAULT << 2)
 
#define CMU_IEN_LFTIMEOUTERR   (0x1UL << 14)
 
#define CMU_IEN_LFTIMEOUTERR_DEFAULT   (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14)
 
#define CMU_IEN_LFXOEDGE   (0x1UL << 27)
 
#define CMU_IEN_LFXOEDGE_DEFAULT   (_CMU_IEN_LFXOEDGE_DEFAULT << 27)
 
#define CMU_IEN_LFXORDY   (0x1UL << 3)
 
#define CMU_IEN_LFXORDY_DEFAULT   (_CMU_IEN_LFXORDY_DEFAULT << 3)
 
#define CMU_IEN_ULFRCOEDGE   (0x1UL << 29)
 
#define CMU_IEN_ULFRCOEDGE_DEFAULT   (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29)
 
#define CMU_IF_AUXHFRCORDY   (0x1UL << 4)
 
#define CMU_IF_AUXHFRCORDY_DEFAULT   (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
 
#define CMU_IF_CALOF   (0x1UL << 6)
 
#define CMU_IF_CALOF_DEFAULT   (_CMU_IF_CALOF_DEFAULT << 6)
 
#define CMU_IF_CALRDY   (0x1UL << 5)
 
#define CMU_IF_CALRDY_DEFAULT   (_CMU_IF_CALRDY_DEFAULT << 5)
 
#define CMU_IF_CMUERR   (0x1UL << 31)
 
#define CMU_IF_CMUERR_DEFAULT   (_CMU_IF_CMUERR_DEFAULT << 31)
 
#define CMU_IF_DPLLLOCKFAILHIGH   (0x1UL << 17)
 
#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT   (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17)
 
#define CMU_IF_DPLLLOCKFAILLOW   (0x1UL << 16)
 
#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT   (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16)
 
#define CMU_IF_DPLLRDY   (0x1UL << 15)
 
#define CMU_IF_DPLLRDY_DEFAULT   (_CMU_IF_DPLLRDY_DEFAULT << 15)
 
#define CMU_IF_HFRCODIS   (0x1UL << 13)
 
#define CMU_IF_HFRCODIS_DEFAULT   (_CMU_IF_HFRCODIS_DEFAULT << 13)
 
#define CMU_IF_HFRCORDY   (0x1UL << 0)
 
#define CMU_IF_HFRCORDY_DEFAULT   (_CMU_IF_HFRCORDY_DEFAULT << 0)
 
#define CMU_IF_HFXOAUTOSW   (0x1UL << 9)
 
#define CMU_IF_HFXOAUTOSW_DEFAULT   (_CMU_IF_HFXOAUTOSW_DEFAULT << 9)
 
#define CMU_IF_HFXODISERR   (0x1UL << 8)
 
#define CMU_IF_HFXODISERR_DEFAULT   (_CMU_IF_HFXODISERR_DEFAULT << 8)
 
#define CMU_IF_HFXOPEAKDETRDY   (0x1UL << 11)
 
#define CMU_IF_HFXOPEAKDETRDY_DEFAULT   (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11)
 
#define CMU_IF_HFXORDY   (0x1UL << 1)
 
#define CMU_IF_HFXORDY_DEFAULT   (_CMU_IF_HFXORDY_DEFAULT << 1)
 
#define CMU_IF_LFRCOEDGE   (0x1UL << 28)
 
#define CMU_IF_LFRCOEDGE_DEFAULT   (_CMU_IF_LFRCOEDGE_DEFAULT << 28)
 
#define CMU_IF_LFRCORDY   (0x1UL << 2)
 
#define CMU_IF_LFRCORDY_DEFAULT   (_CMU_IF_LFRCORDY_DEFAULT << 2)
 
#define CMU_IF_LFTIMEOUTERR   (0x1UL << 14)
 
#define CMU_IF_LFTIMEOUTERR_DEFAULT   (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14)
 
#define CMU_IF_LFXOEDGE   (0x1UL << 27)
 
#define CMU_IF_LFXOEDGE_DEFAULT   (_CMU_IF_LFXOEDGE_DEFAULT << 27)
 
#define CMU_IF_LFXORDY   (0x1UL << 3)
 
#define CMU_IF_LFXORDY_DEFAULT   (_CMU_IF_LFXORDY_DEFAULT << 3)
 
#define CMU_IF_ULFRCOEDGE   (0x1UL << 29)
 
#define CMU_IF_ULFRCOEDGE_DEFAULT   (_CMU_IF_ULFRCOEDGE_DEFAULT << 29)
 
#define CMU_IFC_AUXHFRCORDY   (0x1UL << 4)
 
#define CMU_IFC_AUXHFRCORDY_DEFAULT   (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
 
#define CMU_IFC_CALOF   (0x1UL << 6)
 
#define CMU_IFC_CALOF_DEFAULT   (_CMU_IFC_CALOF_DEFAULT << 6)
 
#define CMU_IFC_CALRDY   (0x1UL << 5)
 
#define CMU_IFC_CALRDY_DEFAULT   (_CMU_IFC_CALRDY_DEFAULT << 5)
 
#define CMU_IFC_CMUERR   (0x1UL << 31)
 
#define CMU_IFC_CMUERR_DEFAULT   (_CMU_IFC_CMUERR_DEFAULT << 31)
 
#define CMU_IFC_DPLLLOCKFAILHIGH   (0x1UL << 17)
 
#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT   (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17)
 
#define CMU_IFC_DPLLLOCKFAILLOW   (0x1UL << 16)
 
#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT   (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16)
 
#define CMU_IFC_DPLLRDY   (0x1UL << 15)
 
#define CMU_IFC_DPLLRDY_DEFAULT   (_CMU_IFC_DPLLRDY_DEFAULT << 15)
 
#define CMU_IFC_HFRCODIS   (0x1UL << 13)
 
#define CMU_IFC_HFRCODIS_DEFAULT   (_CMU_IFC_HFRCODIS_DEFAULT << 13)
 
#define CMU_IFC_HFRCORDY   (0x1UL << 0)
 
#define CMU_IFC_HFRCORDY_DEFAULT   (_CMU_IFC_HFRCORDY_DEFAULT << 0)
 
#define CMU_IFC_HFXOAUTOSW   (0x1UL << 9)
 
#define CMU_IFC_HFXOAUTOSW_DEFAULT   (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9)
 
#define CMU_IFC_HFXODISERR   (0x1UL << 8)
 
#define CMU_IFC_HFXODISERR_DEFAULT   (_CMU_IFC_HFXODISERR_DEFAULT << 8)
 
#define CMU_IFC_HFXOPEAKDETRDY   (0x1UL << 11)
 
#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT   (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11)
 
#define CMU_IFC_HFXORDY   (0x1UL << 1)
 
#define CMU_IFC_HFXORDY_DEFAULT   (_CMU_IFC_HFXORDY_DEFAULT << 1)
 
#define CMU_IFC_LFRCOEDGE   (0x1UL << 28)
 
#define CMU_IFC_LFRCOEDGE_DEFAULT   (_CMU_IFC_LFRCOEDGE_DEFAULT << 28)
 
#define CMU_IFC_LFRCORDY   (0x1UL << 2)
 
#define CMU_IFC_LFRCORDY_DEFAULT   (_CMU_IFC_LFRCORDY_DEFAULT << 2)
 
#define CMU_IFC_LFTIMEOUTERR   (0x1UL << 14)
 
#define CMU_IFC_LFTIMEOUTERR_DEFAULT   (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14)
 
#define CMU_IFC_LFXOEDGE   (0x1UL << 27)
 
#define CMU_IFC_LFXOEDGE_DEFAULT   (_CMU_IFC_LFXOEDGE_DEFAULT << 27)
 
#define CMU_IFC_LFXORDY   (0x1UL << 3)
 
#define CMU_IFC_LFXORDY_DEFAULT   (_CMU_IFC_LFXORDY_DEFAULT << 3)
 
#define CMU_IFC_ULFRCOEDGE   (0x1UL << 29)
 
#define CMU_IFC_ULFRCOEDGE_DEFAULT   (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29)
 
#define CMU_IFS_AUXHFRCORDY   (0x1UL << 4)
 
#define CMU_IFS_AUXHFRCORDY_DEFAULT   (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
 
#define CMU_IFS_CALOF   (0x1UL << 6)
 
#define CMU_IFS_CALOF_DEFAULT   (_CMU_IFS_CALOF_DEFAULT << 6)
 
#define CMU_IFS_CALRDY   (0x1UL << 5)
 
#define CMU_IFS_CALRDY_DEFAULT   (_CMU_IFS_CALRDY_DEFAULT << 5)
 
#define CMU_IFS_CMUERR   (0x1UL << 31)
 
#define CMU_IFS_CMUERR_DEFAULT   (_CMU_IFS_CMUERR_DEFAULT << 31)
 
#define CMU_IFS_DPLLLOCKFAILHIGH   (0x1UL << 17)
 
#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT   (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17)
 
#define CMU_IFS_DPLLLOCKFAILLOW   (0x1UL << 16)
 
#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT   (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16)
 
#define CMU_IFS_DPLLRDY   (0x1UL << 15)
 
#define CMU_IFS_DPLLRDY_DEFAULT   (_CMU_IFS_DPLLRDY_DEFAULT << 15)
 
#define CMU_IFS_HFRCODIS   (0x1UL << 13)
 
#define CMU_IFS_HFRCODIS_DEFAULT   (_CMU_IFS_HFRCODIS_DEFAULT << 13)
 
#define CMU_IFS_HFRCORDY   (0x1UL << 0)
 
#define CMU_IFS_HFRCORDY_DEFAULT   (_CMU_IFS_HFRCORDY_DEFAULT << 0)
 
#define CMU_IFS_HFXOAUTOSW   (0x1UL << 9)
 
#define CMU_IFS_HFXOAUTOSW_DEFAULT   (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9)
 
#define CMU_IFS_HFXODISERR   (0x1UL << 8)
 
#define CMU_IFS_HFXODISERR_DEFAULT   (_CMU_IFS_HFXODISERR_DEFAULT << 8)
 
#define CMU_IFS_HFXOPEAKDETRDY   (0x1UL << 11)
 
#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT   (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11)
 
#define CMU_IFS_HFXORDY   (0x1UL << 1)
 
#define CMU_IFS_HFXORDY_DEFAULT   (_CMU_IFS_HFXORDY_DEFAULT << 1)
 
#define CMU_IFS_LFRCOEDGE   (0x1UL << 28)
 
#define CMU_IFS_LFRCOEDGE_DEFAULT   (_CMU_IFS_LFRCOEDGE_DEFAULT << 28)
 
#define CMU_IFS_LFRCORDY   (0x1UL << 2)
 
#define CMU_IFS_LFRCORDY_DEFAULT   (_CMU_IFS_LFRCORDY_DEFAULT << 2)
 
#define CMU_IFS_LFTIMEOUTERR   (0x1UL << 14)
 
#define CMU_IFS_LFTIMEOUTERR_DEFAULT   (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14)
 
#define CMU_IFS_LFXOEDGE   (0x1UL << 27)
 
#define CMU_IFS_LFXOEDGE_DEFAULT   (_CMU_IFS_LFXOEDGE_DEFAULT << 27)
 
#define CMU_IFS_LFXORDY   (0x1UL << 3)
 
#define CMU_IFS_LFXORDY_DEFAULT   (_CMU_IFS_LFXORDY_DEFAULT << 3)
 
#define CMU_IFS_ULFRCOEDGE   (0x1UL << 29)
 
#define CMU_IFS_ULFRCOEDGE_DEFAULT   (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29)
 
#define CMU_LFACLKEN0_LCD   (0x1UL << 2)
 
#define CMU_LFACLKEN0_LCD_DEFAULT   (_CMU_LFACLKEN0_LCD_DEFAULT << 2)
 
#define CMU_LFACLKEN0_LESENSE   (0x1UL << 0)
 
#define CMU_LFACLKEN0_LESENSE_DEFAULT   (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0)
 
#define CMU_LFACLKEN0_LETIMER0   (0x1UL << 1)
 
#define CMU_LFACLKEN0_LETIMER0_DEFAULT   (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 1)
 
#define CMU_LFACLKSEL_LFA_DEFAULT   (_CMU_LFACLKSEL_LFA_DEFAULT << 0)
 
#define CMU_LFACLKSEL_LFA_DISABLED   (_CMU_LFACLKSEL_LFA_DISABLED << 0)
 
#define CMU_LFACLKSEL_LFA_LFRCO   (_CMU_LFACLKSEL_LFA_LFRCO << 0)
 
#define CMU_LFACLKSEL_LFA_LFXO   (_CMU_LFACLKSEL_LFA_LFXO << 0)
 
#define CMU_LFACLKSEL_LFA_ULFRCO   (_CMU_LFACLKSEL_LFA_ULFRCO << 0)
 
#define CMU_LFAPRESC0_LCD_DIV1   (_CMU_LFAPRESC0_LCD_DIV1 << 8)
 
#define CMU_LFAPRESC0_LCD_DIV128   (_CMU_LFAPRESC0_LCD_DIV128 << 8)
 
#define CMU_LFAPRESC0_LCD_DIV16   (_CMU_LFAPRESC0_LCD_DIV16 << 8)
 
#define CMU_LFAPRESC0_LCD_DIV2   (_CMU_LFAPRESC0_LCD_DIV2 << 8)
 
#define CMU_LFAPRESC0_LCD_DIV32   (_CMU_LFAPRESC0_LCD_DIV32 << 8)
 
#define CMU_LFAPRESC0_LCD_DIV4   (_CMU_LFAPRESC0_LCD_DIV4 << 8)
 
#define CMU_LFAPRESC0_LCD_DIV64   (_CMU_LFAPRESC0_LCD_DIV64 << 8)
 
#define CMU_LFAPRESC0_LCD_DIV8   (_CMU_LFAPRESC0_LCD_DIV8 << 8)
 
#define CMU_LFAPRESC0_LESENSE_DIV1   (_CMU_LFAPRESC0_LESENSE_DIV1 << 0)
 
#define CMU_LFAPRESC0_LESENSE_DIV2   (_CMU_LFAPRESC0_LESENSE_DIV2 << 0)
 
#define CMU_LFAPRESC0_LESENSE_DIV4   (_CMU_LFAPRESC0_LESENSE_DIV4 << 0)
 
#define CMU_LFAPRESC0_LESENSE_DIV8   (_CMU_LFAPRESC0_LESENSE_DIV8 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV1   (_CMU_LFAPRESC0_LETIMER0_DIV1 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV1024   (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV128   (_CMU_LFAPRESC0_LETIMER0_DIV128 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV16   (_CMU_LFAPRESC0_LETIMER0_DIV16 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV16384   (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV2   (_CMU_LFAPRESC0_LETIMER0_DIV2 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV2048   (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV256   (_CMU_LFAPRESC0_LETIMER0_DIV256 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV32   (_CMU_LFAPRESC0_LETIMER0_DIV32 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV32768   (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV4   (_CMU_LFAPRESC0_LETIMER0_DIV4 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV4096   (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV512   (_CMU_LFAPRESC0_LETIMER0_DIV512 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV64   (_CMU_LFAPRESC0_LETIMER0_DIV64 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV8   (_CMU_LFAPRESC0_LETIMER0_DIV8 << 4)
 
#define CMU_LFAPRESC0_LETIMER0_DIV8192   (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 4)
 
#define CMU_LFBCLKEN0_CSEN   (0x1UL << 2)
 
#define CMU_LFBCLKEN0_CSEN_DEFAULT   (_CMU_LFBCLKEN0_CSEN_DEFAULT << 2)
 
#define CMU_LFBCLKEN0_LEUART0   (0x1UL << 1)
 
#define CMU_LFBCLKEN0_LEUART0_DEFAULT   (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 1)
 
#define CMU_LFBCLKEN0_SYSTICK   (0x1UL << 0)
 
#define CMU_LFBCLKEN0_SYSTICK_DEFAULT   (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 0)
 
#define CMU_LFBCLKSEL_LFB_DEFAULT   (_CMU_LFBCLKSEL_LFB_DEFAULT << 0)
 
#define CMU_LFBCLKSEL_LFB_DISABLED   (_CMU_LFBCLKSEL_LFB_DISABLED << 0)
 
#define CMU_LFBCLKSEL_LFB_HFCLKLE   (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0)
 
#define CMU_LFBCLKSEL_LFB_LFRCO   (_CMU_LFBCLKSEL_LFB_LFRCO << 0)
 
#define CMU_LFBCLKSEL_LFB_LFXO   (_CMU_LFBCLKSEL_LFB_LFXO << 0)
 
#define CMU_LFBCLKSEL_LFB_ULFRCO   (_CMU_LFBCLKSEL_LFB_ULFRCO << 0)
 
#define CMU_LFBPRESC0_CSEN_DIV128   (_CMU_LFBPRESC0_CSEN_DIV128 << 8)
 
#define CMU_LFBPRESC0_CSEN_DIV16   (_CMU_LFBPRESC0_CSEN_DIV16 << 8)
 
#define CMU_LFBPRESC0_CSEN_DIV32   (_CMU_LFBPRESC0_CSEN_DIV32 << 8)
 
#define CMU_LFBPRESC0_CSEN_DIV64   (_CMU_LFBPRESC0_CSEN_DIV64 << 8)
 
#define CMU_LFBPRESC0_LEUART0_DIV1   (_CMU_LFBPRESC0_LEUART0_DIV1 << 4)
 
#define CMU_LFBPRESC0_LEUART0_DIV2   (_CMU_LFBPRESC0_LEUART0_DIV2 << 4)
 
#define CMU_LFBPRESC0_LEUART0_DIV4   (_CMU_LFBPRESC0_LEUART0_DIV4 << 4)
 
#define CMU_LFBPRESC0_LEUART0_DIV8   (_CMU_LFBPRESC0_LEUART0_DIV8 << 4)
 
#define CMU_LFBPRESC0_SYSTICK_DIV1   (_CMU_LFBPRESC0_SYSTICK_DIV1 << 0)
 
#define CMU_LFECLKEN0_RTCC   (0x1UL << 0)
 
#define CMU_LFECLKEN0_RTCC_DEFAULT   (_CMU_LFECLKEN0_RTCC_DEFAULT << 0)
 
#define CMU_LFECLKSEL_LFE_DEFAULT   (_CMU_LFECLKSEL_LFE_DEFAULT << 0)
 
#define CMU_LFECLKSEL_LFE_DISABLED   (_CMU_LFECLKSEL_LFE_DISABLED << 0)
 
#define CMU_LFECLKSEL_LFE_LFRCO   (_CMU_LFECLKSEL_LFE_LFRCO << 0)
 
#define CMU_LFECLKSEL_LFE_LFXO   (_CMU_LFECLKSEL_LFE_LFXO << 0)
 
#define CMU_LFECLKSEL_LFE_ULFRCO   (_CMU_LFECLKSEL_LFE_ULFRCO << 0)
 
#define CMU_LFEPRESC0_RTCC_DIV1   (_CMU_LFEPRESC0_RTCC_DIV1 << 0)
 
#define CMU_LFEPRESC0_RTCC_DIV2   (_CMU_LFEPRESC0_RTCC_DIV2 << 0)
 
#define CMU_LFEPRESC0_RTCC_DIV4   (_CMU_LFEPRESC0_RTCC_DIV4 << 0)
 
#define CMU_LFRCOCTRL_ENCHOP   (0x1UL << 17)
 
#define CMU_LFRCOCTRL_ENCHOP_DEFAULT   (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17)
 
#define CMU_LFRCOCTRL_ENDEM   (0x1UL << 18)
 
#define CMU_LFRCOCTRL_ENDEM_DEFAULT   (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18)
 
#define CMU_LFRCOCTRL_ENVREF   (0x1UL << 16)
 
#define CMU_LFRCOCTRL_ENVREF_DEFAULT   (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16)
 
#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT   (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28)
 
#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES   (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24)
 
#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES   (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24)
 
#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES   (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24)
 
#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT   (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24)
 
#define CMU_LFRCOCTRL_TUNING_DEFAULT   (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
 
#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES   (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20)
 
#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES   (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20)
 
#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES   (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20)
 
#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES   (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20)
 
#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT   (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20)
 
#define CMU_LFXOCTRL_AGC   (0x1UL << 15)
 
#define CMU_LFXOCTRL_AGC_DEFAULT   (_CMU_LFXOCTRL_AGC_DEFAULT << 15)
 
#define CMU_LFXOCTRL_BUFCUR   (0x1UL << 20)
 
#define CMU_LFXOCTRL_BUFCUR_DEFAULT   (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20)
 
#define CMU_LFXOCTRL_CUR_DEFAULT   (_CMU_LFXOCTRL_CUR_DEFAULT << 16)
 
#define CMU_LFXOCTRL_GAIN_DEFAULT   (_CMU_LFXOCTRL_GAIN_DEFAULT << 11)
 
#define CMU_LFXOCTRL_HIGHAMPL   (0x1UL << 14)
 
#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT   (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14)
 
#define CMU_LFXOCTRL_MODE_BUFEXTCLK   (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8)
 
#define CMU_LFXOCTRL_MODE_DEFAULT   (_CMU_LFXOCTRL_MODE_DEFAULT << 8)
 
#define CMU_LFXOCTRL_MODE_DIGEXTCLK   (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8)
 
#define CMU_LFXOCTRL_MODE_XTAL   (_CMU_LFXOCTRL_MODE_XTAL << 8)
 
#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES   (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES   (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_256CYCLES   (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_2CYCLES   (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES   (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES   (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES   (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES   (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_DEFAULT   (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24)
 
#define CMU_LFXOCTRL_TUNING_DEFAULT   (_CMU_LFXOCTRL_TUNING_DEFAULT << 0)
 
#define CMU_LOCK_LOCKKEY_DEFAULT   (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
 
#define CMU_LOCK_LOCKKEY_LOCK   (_CMU_LOCK_LOCKKEY_LOCK << 0)
 
#define CMU_LOCK_LOCKKEY_LOCKED   (_CMU_LOCK_LOCKKEY_LOCKED << 0)
 
#define CMU_LOCK_LOCKKEY_UNLOCK   (_CMU_LOCK_LOCKKEY_UNLOCK << 0)
 
#define CMU_LOCK_LOCKKEY_UNLOCKED   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
 
#define CMU_OSCENCMD_AUXHFRCODIS   (0x1UL << 5)
 
#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT   (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
 
#define CMU_OSCENCMD_AUXHFRCOEN   (0x1UL << 4)
 
#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT   (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
 
#define CMU_OSCENCMD_DPLLDIS   (0x1UL << 13)
 
#define CMU_OSCENCMD_DPLLDIS_DEFAULT   (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13)
 
#define CMU_OSCENCMD_DPLLEN   (0x1UL << 12)
 
#define CMU_OSCENCMD_DPLLEN_DEFAULT   (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12)
 
#define CMU_OSCENCMD_HFRCODIS   (0x1UL << 1)
 
#define CMU_OSCENCMD_HFRCODIS_DEFAULT   (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
 
#define CMU_OSCENCMD_HFRCOEN   (0x1UL << 0)
 
#define CMU_OSCENCMD_HFRCOEN_DEFAULT   (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
 
#define CMU_OSCENCMD_HFXODIS   (0x1UL << 3)
 
#define CMU_OSCENCMD_HFXODIS_DEFAULT   (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
 
#define CMU_OSCENCMD_HFXOEN   (0x1UL << 2)
 
#define CMU_OSCENCMD_HFXOEN_DEFAULT   (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
 
#define CMU_OSCENCMD_LFRCODIS   (0x1UL << 7)
 
#define CMU_OSCENCMD_LFRCODIS_DEFAULT   (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
 
#define CMU_OSCENCMD_LFRCOEN   (0x1UL << 6)
 
#define CMU_OSCENCMD_LFRCOEN_DEFAULT   (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
 
#define CMU_OSCENCMD_LFXODIS   (0x1UL << 9)
 
#define CMU_OSCENCMD_LFXODIS_DEFAULT   (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
 
#define CMU_OSCENCMD_LFXOEN   (0x1UL << 8)
 
#define CMU_OSCENCMD_LFXOEN_DEFAULT   (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
 
#define CMU_PCNTCTRL_PCNT0CLKEN   (0x1UL << 0)
 
#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT   (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
 
#define CMU_PCNTCTRL_PCNT0CLKSEL   (0x1UL << 1)
 
#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT   (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
 
#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK   (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
 
#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0   (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT   (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT   (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8)
 
#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT   (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16)
 
#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0   (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16)
 
#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1   (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16)
 
#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2   (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16)
 
#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3   (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16)
 
#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4   (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16)
 
#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5   (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16)
 
#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT   (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0)
 
#define CMU_ROUTELOC1_CLKIN0LOC_LOC0   (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0)
 
#define CMU_ROUTELOC1_CLKIN0LOC_LOC1   (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0)
 
#define CMU_ROUTELOC1_CLKIN0LOC_LOC2   (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0)
 
#define CMU_ROUTELOC1_CLKIN0LOC_LOC3   (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0)
 
#define CMU_ROUTELOC1_CLKIN0LOC_LOC4   (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0)
 
#define CMU_ROUTELOC1_CLKIN0LOC_LOC5   (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0)
 
#define CMU_ROUTELOC1_CLKIN0LOC_LOC6   (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0)
 
#define CMU_ROUTELOC1_CLKIN0LOC_LOC7   (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0)
 
#define CMU_ROUTEPEN_CLKIN0PEN   (0x1UL << 28)
 
#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT   (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28)
 
#define CMU_ROUTEPEN_CLKOUT0PEN   (0x1UL << 0)
 
#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT   (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0)
 
#define CMU_ROUTEPEN_CLKOUT1PEN   (0x1UL << 1)
 
#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT   (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1)
 
#define CMU_ROUTEPEN_CLKOUT2PEN   (0x1UL << 2)
 
#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT   (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2)
 
#define CMU_STATUS_AUXHFRCOENS   (0x1UL << 4)
 
#define CMU_STATUS_AUXHFRCOENS_DEFAULT   (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
 
#define CMU_STATUS_AUXHFRCORDY   (0x1UL << 5)
 
#define CMU_STATUS_AUXHFRCORDY_DEFAULT   (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
 
#define CMU_STATUS_CALRDY   (0x1UL << 16)
 
#define CMU_STATUS_CALRDY_DEFAULT   (_CMU_STATUS_CALRDY_DEFAULT << 16)
 
#define CMU_STATUS_DPLLENS   (0x1UL << 12)
 
#define CMU_STATUS_DPLLENS_DEFAULT   (_CMU_STATUS_DPLLENS_DEFAULT << 12)
 
#define CMU_STATUS_DPLLRDY   (0x1UL << 13)
 
#define CMU_STATUS_DPLLRDY_DEFAULT   (_CMU_STATUS_DPLLRDY_DEFAULT << 13)
 
#define CMU_STATUS_HFRCOENS   (0x1UL << 0)
 
#define CMU_STATUS_HFRCOENS_DEFAULT   (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
 
#define CMU_STATUS_HFRCORDY   (0x1UL << 1)
 
#define CMU_STATUS_HFRCORDY_DEFAULT   (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
 
#define CMU_STATUS_HFXOAMPLOW   (0x1UL << 25)
 
#define CMU_STATUS_HFXOAMPLOW_DEFAULT   (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25)
 
#define CMU_STATUS_HFXOENS   (0x1UL << 2)
 
#define CMU_STATUS_HFXOENS_DEFAULT   (_CMU_STATUS_HFXOENS_DEFAULT << 2)
 
#define CMU_STATUS_HFXOPEAKDETRDY   (0x1UL << 22)
 
#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT   (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22)
 
#define CMU_STATUS_HFXORDY   (0x1UL << 3)
 
#define CMU_STATUS_HFXORDY_DEFAULT   (_CMU_STATUS_HFXORDY_DEFAULT << 3)
 
#define CMU_STATUS_LFRCOENS   (0x1UL << 6)
 
#define CMU_STATUS_LFRCOENS_DEFAULT   (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
 
#define CMU_STATUS_LFRCOPHASE   (0x1UL << 28)
 
#define CMU_STATUS_LFRCOPHASE_DEFAULT   (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28)
 
#define CMU_STATUS_LFRCORDY   (0x1UL << 7)
 
#define CMU_STATUS_LFRCORDY_DEFAULT   (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
 
#define CMU_STATUS_LFXOENS   (0x1UL << 8)
 
#define CMU_STATUS_LFXOENS_DEFAULT   (_CMU_STATUS_LFXOENS_DEFAULT << 8)
 
#define CMU_STATUS_LFXOPHASE   (0x1UL << 27)
 
#define CMU_STATUS_LFXOPHASE_DEFAULT   (_CMU_STATUS_LFXOPHASE_DEFAULT << 27)
 
#define CMU_STATUS_LFXORDY   (0x1UL << 9)
 
#define CMU_STATUS_LFXORDY_DEFAULT   (_CMU_STATUS_LFXORDY_DEFAULT << 9)
 
#define CMU_STATUS_ULFRCOPHASE   (0x1UL << 29)
 
#define CMU_STATUS_ULFRCOPHASE_DEFAULT   (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29)
 
#define CMU_SYNCBUSY_AUXHFRCOBSY   (0x1UL << 25)
 
#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT   (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25)
 
#define CMU_SYNCBUSY_HFRCOBSY   (0x1UL << 24)
 
#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT   (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24)
 
#define CMU_SYNCBUSY_HFXOBSY   (0x1UL << 28)
 
#define CMU_SYNCBUSY_HFXOBSY_DEFAULT   (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28)
 
#define CMU_SYNCBUSY_LFACLKEN0   (0x1UL << 0)
 
#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT   (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
 
#define CMU_SYNCBUSY_LFAPRESC0   (0x1UL << 2)
 
#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT   (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
 
#define CMU_SYNCBUSY_LFBCLKEN0   (0x1UL << 4)
 
#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT   (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
 
#define CMU_SYNCBUSY_LFBPRESC0   (0x1UL << 6)
 
#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT   (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
 
#define CMU_SYNCBUSY_LFECLKEN0   (0x1UL << 16)
 
#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT   (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16)
 
#define CMU_SYNCBUSY_LFEPRESC0   (0x1UL << 18)
 
#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT   (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18)
 
#define CMU_SYNCBUSY_LFRCOBSY   (0x1UL << 26)
 
#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT   (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26)
 
#define CMU_SYNCBUSY_LFRCOVREFBSY   (0x1UL << 27)
 
#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT   (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27)
 
#define CMU_SYNCBUSY_LFXOBSY   (0x1UL << 29)
 
#define CMU_SYNCBUSY_LFXOBSY_DEFAULT   (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29)
 

Macro Definition Documentation

#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_ADCCTRL

Definition at line 1964 of file efm32tg11b_cmu.h.

#define _CMU_ADCCTRL_ADC0CLKDIV_MASK   0x3UL

Bit mask for CMU_ADC0CLKDIV

Definition at line 1963 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION   0x00000000UL

Mode NODIVISION for CMU_ADCCTRL

Definition at line 1965 of file efm32tg11b_cmu.h.

#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT   0

Shift value for CMU_ADC0CLKDIV

Definition at line 1962 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_ADCCTRL

Definition at line 1983 of file efm32tg11b_cmu.h.

#define _CMU_ADCCTRL_ADC0CLKINV_MASK   0x100UL

Bit mask for CMU_ADC0CLKINV

Definition at line 1982 of file efm32tg11b_cmu.h.

#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT   8

Shift value for CMU_ADC0CLKINV

Definition at line 1981 of file efm32tg11b_cmu.h.

#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO   0x00000001UL

Mode AUXHFRCO for CMU_ADCCTRL

Definition at line 1972 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_ADCCTRL

Definition at line 1970 of file efm32tg11b_cmu.h.

#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED   0x00000000UL

Mode DISABLED for CMU_ADCCTRL

Definition at line 1971 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK   0x00000003UL

Mode HFSRCCLK for CMU_ADCCTRL

Definition at line 1974 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO   0x00000002UL

Mode HFXO for CMU_ADCCTRL

Definition at line 1973 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_ADCCTRL_ADC0CLKSEL_MASK   0x30UL

Bit mask for CMU_ADC0CLKSEL

Definition at line 1969 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockSelectGet(), and CMU_ClockSelectSet().

#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT   4

Shift value for CMU_ADC0CLKSEL

Definition at line 1968 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_ADCCTRL_MASK   0x00000133UL

Mask for CMU_ADCCTRL

Definition at line 1961 of file efm32tg11b_cmu.h.

#define _CMU_ADCCTRL_RESETVALUE   0x00000000UL

Default value for CMU_ADCCTRL

Definition at line 1960 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 324 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1   0x00000000UL

Mode DIV1 for CMU_AUXHFRCOCTRL

Definition at line 325 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2   0x00000001UL

Mode DIV2 for CMU_AUXHFRCOCTRL

Definition at line 326 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4   0x00000002UL

Mode DIV4 for CMU_AUXHFRCOCTRL

Definition at line 327 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK   0x6000000UL

Bit mask for CMU_CLKDIV

Definition at line 323 of file efm32tg11b_cmu.h.

Referenced by CMU_AUXHFRCOBandSet().

#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT   25

Shift value for CMU_CLKDIV

Definition at line 322 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT   0x00000002UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 315 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK   0xE00000UL

Bit mask for CMU_CMPBIAS

Definition at line 314 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT   21

Shift value for CMU_CMPBIAS

Definition at line 313 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT   0x0000001FUL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 307 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK   0x3F00UL

Bit mask for CMU_FINETUNING

Definition at line 306 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT   8

Shift value for CMU_FINETUNING

Definition at line 305 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 335 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK   0x8000000UL

Bit mask for CMU_FINETUNINGEN

Definition at line 334 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT   27

Shift value for CMU_FINETUNINGEN

Definition at line 333 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT   0x00000008UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 311 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK   0x1F0000UL

Bit mask for CMU_FREQRANGE

Definition at line 310 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT   16

Shift value for CMU_FREQRANGE

Definition at line 309 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 320 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_LDOHP_MASK   0x1000000UL

Bit mask for CMU_LDOHP

Definition at line 319 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT   24

Shift value for CMU_LDOHP

Definition at line 318 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_MASK   0xFFFF3F7FUL

Mask for CMU_AUXHFRCOCTRL

Definition at line 300 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_RESETVALUE   0xB1481F7FUL

Default value for CMU_AUXHFRCOCTRL

Definition at line 299 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT   0x0000007FUL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 303 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_TUNING_MASK   0x7FUL

Bit mask for CMU_TUNING

Definition at line 302 of file efm32tg11b_cmu.h.

Referenced by CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT   0

Shift value for CMU_TUNING

Definition at line 301 of file efm32tg11b_cmu.h.

Referenced by CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT   0x0000000BUL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 339 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_VREFTC_MASK   0xF0000000UL

Bit mask for CMU_VREFTC

Definition at line 338 of file efm32tg11b_cmu.h.

#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT   28

Shift value for CMU_VREFTC

Definition at line 337 of file efm32tg11b_cmu.h.

#define _CMU_CALCNT_CALCNT_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCNT

Definition at line 792 of file efm32tg11b_cmu.h.

#define _CMU_CALCNT_CALCNT_MASK   0xFFFFFUL

Bit mask for CMU_CALCNT

Definition at line 791 of file efm32tg11b_cmu.h.

Referenced by CMU_Calibrate(), and CMU_CalibrateConfig().

#define _CMU_CALCNT_CALCNT_SHIFT   0

Shift value for CMU_CALCNT

Definition at line 790 of file efm32tg11b_cmu.h.

Referenced by CMU_Calibrate(), and CMU_CalibrateConfig().

#define _CMU_CALCNT_MASK   0x000FFFFFUL

Mask for CMU_CALCNT

Definition at line 789 of file efm32tg11b_cmu.h.

#define _CMU_CALCNT_RESETVALUE   0x00000000UL

Default value for CMU_CALCNT

Definition at line 788 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_CONT_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 744 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_CONT_MASK   0x100UL

Bit mask for CMU_CONT

Definition at line 743 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_CONT_SHIFT   8

Shift value for CMU_CONT

Definition at line 742 of file efm32tg11b_cmu.h.

Referenced by CMU_CalibrateCont(), and CMU_CalibrateCountGet().

#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO   0x00000005UL

Mode AUXHFRCO for CMU_CALCTRL

Definition at line 731 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 725 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_HFCLK   0x00000000UL

Mode HFCLK for CMU_CALCTRL

Definition at line 726 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_HFRCO   0x00000003UL

Mode HFRCO for CMU_CALCTRL

Definition at line 729 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_HFXO   0x00000001UL

Mode HFXO for CMU_CALCTRL

Definition at line 727 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_LFRCO   0x00000004UL

Mode LFRCO for CMU_CALCTRL

Definition at line 730 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_LFXO   0x00000002UL

Mode LFXO for CMU_CALCTRL

Definition at line 728 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_MASK   0x70UL

Bit mask for CMU_DOWNSEL

Definition at line 724 of file efm32tg11b_cmu.h.

Referenced by CMU_CalibrateConfig().

#define _CMU_CALCTRL_DOWNSEL_PRS   0x00000006UL

Mode PRS for CMU_CALCTRL

Definition at line 732 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_SHIFT   4

Shift value for CMU_DOWNSEL

Definition at line 723 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_MASK   0x07070177UL

Mask for CMU_CALCTRL

Definition at line 706 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 768 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_MASK   0x7000000UL

Bit mask for CMU_PRSDOWNSEL

Definition at line 767 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0   0x00000000UL

Mode PRSCH0 for CMU_CALCTRL

Definition at line 769 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1   0x00000001UL

Mode PRSCH1 for CMU_CALCTRL

Definition at line 770 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2   0x00000002UL

Mode PRSCH2 for CMU_CALCTRL

Definition at line 771 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3   0x00000003UL

Mode PRSCH3 for CMU_CALCTRL

Definition at line 772 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4   0x00000004UL

Mode PRSCH4 for CMU_CALCTRL

Definition at line 773 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5   0x00000005UL

Mode PRSCH5 for CMU_CALCTRL

Definition at line 774 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6   0x00000006UL

Mode PRSCH6 for CMU_CALCTRL

Definition at line 775 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7   0x00000007UL

Mode PRSCH7 for CMU_CALCTRL

Definition at line 776 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT   24

Shift value for CMU_PRSDOWNSEL

Definition at line 766 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 748 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_MASK   0x70000UL

Bit mask for CMU_PRSUPSEL

Definition at line 747 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH0   0x00000000UL

Mode PRSCH0 for CMU_CALCTRL

Definition at line 749 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH1   0x00000001UL

Mode PRSCH1 for CMU_CALCTRL

Definition at line 750 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH2   0x00000002UL

Mode PRSCH2 for CMU_CALCTRL

Definition at line 751 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH3   0x00000003UL

Mode PRSCH3 for CMU_CALCTRL

Definition at line 752 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH4   0x00000004UL

Mode PRSCH4 for CMU_CALCTRL

Definition at line 753 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH5   0x00000005UL

Mode PRSCH5 for CMU_CALCTRL

Definition at line 754 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH6   0x00000006UL

Mode PRSCH6 for CMU_CALCTRL

Definition at line 755 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH7   0x00000007UL

Mode PRSCH7 for CMU_CALCTRL

Definition at line 756 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_SHIFT   16

Shift value for CMU_PRSUPSEL

Definition at line 746 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_RESETVALUE   0x00000000UL

Default value for CMU_CALCTRL

Definition at line 705 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_UPSEL_AUXHFRCO   0x00000004UL

Mode AUXHFRCO for CMU_CALCTRL

Definition at line 714 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_UPSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 709 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_UPSEL_HFRCO   0x00000002UL

Mode HFRCO for CMU_CALCTRL

Definition at line 712 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_UPSEL_HFXO   0x00000000UL

Mode HFXO for CMU_CALCTRL

Definition at line 710 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_UPSEL_LFRCO   0x00000003UL

Mode LFRCO for CMU_CALCTRL

Definition at line 713 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_UPSEL_LFXO   0x00000001UL

Mode LFXO for CMU_CALCTRL

Definition at line 711 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_UPSEL_MASK   0x7UL

Bit mask for CMU_UPSEL

Definition at line 708 of file efm32tg11b_cmu.h.

Referenced by CMU_CalibrateConfig().

#define _CMU_CALCTRL_UPSEL_PRS   0x00000005UL

Mode PRS for CMU_CALCTRL

Definition at line 715 of file efm32tg11b_cmu.h.

#define _CMU_CALCTRL_UPSEL_SHIFT   0

Shift value for CMU_UPSEL

Definition at line 707 of file efm32tg11b_cmu.h.

#define _CMU_CMD_CALSTART_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 865 of file efm32tg11b_cmu.h.

#define _CMU_CMD_CALSTART_MASK   0x1UL

Bit mask for CMU_CALSTART

Definition at line 864 of file efm32tg11b_cmu.h.

#define _CMU_CMD_CALSTART_SHIFT   0

Shift value for CMU_CALSTART

Definition at line 863 of file efm32tg11b_cmu.h.

#define _CMU_CMD_CALSTOP_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 870 of file efm32tg11b_cmu.h.

#define _CMU_CMD_CALSTOP_MASK   0x2UL

Bit mask for CMU_CALSTOP

Definition at line 869 of file efm32tg11b_cmu.h.

#define _CMU_CMD_CALSTOP_SHIFT   1

Shift value for CMU_CALSTOP

Definition at line 868 of file efm32tg11b_cmu.h.

#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 875 of file efm32tg11b_cmu.h.

#define _CMU_CMD_HFXOPEAKDETSTART_MASK   0x10UL

Bit mask for CMU_HFXOPEAKDETSTART

Definition at line 874 of file efm32tg11b_cmu.h.

#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT   4

Shift value for CMU_HFXOPEAKDETSTART

Definition at line 873 of file efm32tg11b_cmu.h.

#define _CMU_CMD_MASK   0x00000013UL

Mask for CMU_CMD

Definition at line 861 of file efm32tg11b_cmu.h.

#define _CMU_CMD_RESETVALUE   0x00000000UL

Default value for CMU_CMD

Definition at line 860 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ   0x0000000DUL

Mode AUXHFRCOQ for CMU_CTRL

Definition at line 164 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 153 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_DISABLED   0x00000000UL

Mode DISABLED for CMU_CTRL

Definition at line 154 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK   0x00000007UL

Mode HFEXPCLK for CMU_CTRL

Definition at line 159 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ   0x0000000CUL

Mode HFRCOQ for CMU_CTRL

Definition at line 163 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK   0x0000000FUL

Mode HFSRCCLK for CMU_CTRL

Definition at line 166 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFXO   0x00000006UL

Mode HFXO for CMU_CTRL

Definition at line 158 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFXOQ   0x0000000EUL

Mode HFXOQ for CMU_CTRL

Definition at line 165 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_LFRCO   0x00000002UL

Mode LFRCO for CMU_CTRL

Definition at line 156 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ   0x0000000AUL

Mode LFRCOQ for CMU_CTRL

Definition at line 161 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_LFXO   0x00000003UL

Mode LFXO for CMU_CTRL

Definition at line 157 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_LFXOQ   0x0000000BUL

Mode LFXOQ for CMU_CTRL

Definition at line 162 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_MASK   0xFUL

Bit mask for CMU_CLKOUTSEL0

Definition at line 152 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_SHIFT   0

Shift value for CMU_CLKOUTSEL0

Definition at line 151 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_ULFRCO   0x00000001UL

Mode ULFRCO for CMU_CTRL

Definition at line 155 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ   0x00000009UL

Mode ULFRCOQ for CMU_CTRL

Definition at line 160 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ   0x0000000DUL

Mode AUXHFRCOQ for CMU_CTRL

Definition at line 194 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 183 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_DISABLED   0x00000000UL

Mode DISABLED for CMU_CTRL

Definition at line 184 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK   0x00000007UL

Mode HFEXPCLK for CMU_CTRL

Definition at line 189 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ   0x0000000CUL

Mode HFRCOQ for CMU_CTRL

Definition at line 193 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK   0x0000000FUL

Mode HFSRCCLK for CMU_CTRL

Definition at line 196 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_HFXO   0x00000006UL

Mode HFXO for CMU_CTRL

Definition at line 188 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_HFXOQ   0x0000000EUL

Mode HFXOQ for CMU_CTRL

Definition at line 195 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_LFRCO   0x00000002UL

Mode LFRCO for CMU_CTRL

Definition at line 186 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ   0x0000000AUL

Mode LFRCOQ for CMU_CTRL

Definition at line 191 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_LFXO   0x00000003UL

Mode LFXO for CMU_CTRL

Definition at line 187 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_LFXOQ   0x0000000BUL

Mode LFXOQ for CMU_CTRL

Definition at line 192 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_MASK   0x1E0UL

Bit mask for CMU_CLKOUTSEL1

Definition at line 182 of file efm32tg11b_cmu.h.

Referenced by adcDeInit().

#define _CMU_CTRL_CLKOUTSEL1_SHIFT   5

Shift value for CMU_CLKOUTSEL1

Definition at line 181 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_ULFRCO   0x00000001UL

Mode ULFRCO for CMU_CTRL

Definition at line 185 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ   0x00000009UL

Mode ULFRCOQ for CMU_CTRL

Definition at line 190 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ   0x0000000DUL

Mode AUXHFRCOQ for CMU_CTRL

Definition at line 225 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 213 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_DISABLED   0x00000000UL

Mode DISABLED for CMU_CTRL

Definition at line 214 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK   0x00000007UL

Mode HFEXPCLK for CMU_CTRL

Definition at line 220 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ   0x0000000CUL

Mode HFRCOQ for CMU_CTRL

Definition at line 224 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK   0x0000000FUL

Mode HFSRCCLK for CMU_CTRL

Definition at line 227 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_HFXO   0x00000006UL

Mode HFXO for CMU_CTRL

Definition at line 219 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q   0x00000005UL

Mode HFXODIV2Q for CMU_CTRL

Definition at line 218 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_HFXOQ   0x0000000EUL

Mode HFXOQ for CMU_CTRL

Definition at line 226 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_LFRCO   0x00000002UL

Mode LFRCO for CMU_CTRL

Definition at line 216 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ   0x0000000AUL

Mode LFRCOQ for CMU_CTRL

Definition at line 222 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_LFXO   0x00000003UL

Mode LFXO for CMU_CTRL

Definition at line 217 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_LFXOQ   0x0000000BUL

Mode LFXOQ for CMU_CTRL

Definition at line 223 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_MASK   0x3C00UL

Bit mask for CMU_CLKOUTSEL2

Definition at line 212 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_SHIFT   10

Shift value for CMU_CLKOUTSEL2

Definition at line 211 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_ULFRCO   0x00000001UL

Mode ULFRCO for CMU_CTRL

Definition at line 215 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ   0x00000009UL

Mode ULFRCOQ for CMU_CTRL

Definition at line 221 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_HFPERCLKEN_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_CTRL

Definition at line 251 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_HFPERCLKEN_MASK   0x100000UL

Bit mask for CMU_HFPERCLKEN

Definition at line 250 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_HFPERCLKEN_SHIFT   20

Shift value for CMU_HFPERCLKEN

Definition at line 249 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_MASK   0x00113DEFUL

Mask for CMU_CTRL

Definition at line 150 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_RESETVALUE   0x00100000UL

Default value for CMU_CTRL

Definition at line 149 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_WSHFLE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 246 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_WSHFLE_MASK   0x10000UL

Bit mask for CMU_WSHFLE

Definition at line 245 of file efm32tg11b_cmu.h.

#define _CMU_CTRL_WSHFLE_SHIFT   16

Shift value for CMU_WSHFLE

Definition at line 244 of file efm32tg11b_cmu.h.

#define _CMU_DBGCLKSEL_DBG_AUXHFRCO   0x00000000UL

Mode AUXHFRCO for CMU_DBGCLKSEL

Definition at line 884 of file efm32tg11b_cmu.h.

#define _CMU_DBGCLKSEL_DBG_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_DBGCLKSEL

Definition at line 883 of file efm32tg11b_cmu.h.

#define _CMU_DBGCLKSEL_DBG_HFCLK   0x00000001UL

Mode HFCLK for CMU_DBGCLKSEL

Definition at line 885 of file efm32tg11b_cmu.h.

#define _CMU_DBGCLKSEL_DBG_HFRCODIV2   0x00000002UL

Mode HFRCODIV2 for CMU_DBGCLKSEL

Definition at line 886 of file efm32tg11b_cmu.h.

#define _CMU_DBGCLKSEL_DBG_MASK   0x3UL

Bit mask for CMU_DBG

Definition at line 882 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockSelectGet().

#define _CMU_DBGCLKSEL_DBG_SHIFT   0

Shift value for CMU_DBG

Definition at line 881 of file efm32tg11b_cmu.h.

#define _CMU_DBGCLKSEL_MASK   0x00000003UL

Mask for CMU_DBGCLKSEL

Definition at line 880 of file efm32tg11b_cmu.h.

#define _CMU_DBGCLKSEL_RESETVALUE   0x00000000UL

Default value for CMU_DBGCLKSEL

Definition at line 879 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL1_M_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_DPLLCTRL1

Definition at line 697 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL1_M_MASK   0xFFFUL

Bit mask for CMU_M

Definition at line 696 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock().

#define _CMU_DPLLCTRL1_M_SHIFT   0

Shift value for CMU_M

Definition at line 695 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock().

#define _CMU_DPLLCTRL1_MASK   0x0FFF0FFFUL

Mask for CMU_DPLLCTRL1

Definition at line 694 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL1_N_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_DPLLCTRL1

Definition at line 701 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL1_N_MASK   0xFFF0000UL

Bit mask for CMU_N

Definition at line 700 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock().

#define _CMU_DPLLCTRL1_N_SHIFT   16

Shift value for CMU_N

Definition at line 699 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock().

#define _CMU_DPLLCTRL1_RESETVALUE   0x00000000UL

Default value for CMU_DPLLCTRL1

Definition at line 693 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_DPLLCTRL

Definition at line 674 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_AUTORECOVER_MASK   0x4UL

Bit mask for CMU_AUTORECOVER

Definition at line 673 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT   2

Shift value for CMU_AUTORECOVER

Definition at line 672 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock().

#define _CMU_DPLLCTRL_DITHEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_DPLLCTRL

Definition at line 689 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_DITHEN_MASK   0x40UL

Bit mask for CMU_DITHEN

Definition at line 688 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_DITHEN_SHIFT   6

Shift value for CMU_DITHEN

Definition at line 687 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_EDGESEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_DPLLCTRL

Definition at line 665 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_EDGESEL_FALL   0x00000000UL

Mode FALL for CMU_DPLLCTRL

Definition at line 666 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_EDGESEL_MASK   0x2UL

Bit mask for CMU_EDGESEL

Definition at line 664 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_EDGESEL_RISE   0x00000001UL

Mode RISE for CMU_DPLLCTRL

Definition at line 667 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_EDGESEL_SHIFT   1

Shift value for CMU_EDGESEL

Definition at line 663 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock().

#define _CMU_DPLLCTRL_MASK   0x0000005FUL

Mask for CMU_DPLLCTRL

Definition at line 652 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_MODE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_DPLLCTRL

Definition at line 656 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_MODE_FREQLL   0x00000000UL

Mode FREQLL for CMU_DPLLCTRL

Definition at line 657 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_MODE_MASK   0x1UL

Bit mask for CMU_MODE

Definition at line 655 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_MODE_PHASELL   0x00000001UL

Mode PHASELL for CMU_DPLLCTRL

Definition at line 658 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_MODE_SHIFT   0

Shift value for CMU_MODE

Definition at line 654 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock().

#define _CMU_DPLLCTRL_REFSEL_CLKIN0   0x00000003UL

Mode CLKIN0 for CMU_DPLLCTRL

Definition at line 681 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_REFSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_DPLLCTRL

Definition at line 678 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_REFSEL_HFXO   0x00000000UL

Mode HFXO for CMU_DPLLCTRL

Definition at line 679 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_REFSEL_LFXO   0x00000001UL

Mode LFXO for CMU_DPLLCTRL

Definition at line 680 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_REFSEL_MASK   0x18UL

Bit mask for CMU_REFSEL

Definition at line 677 of file efm32tg11b_cmu.h.

#define _CMU_DPLLCTRL_REFSEL_SHIFT   3

Shift value for CMU_REFSEL

Definition at line 676 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock().

#define _CMU_DPLLCTRL_RESETVALUE   0x00000000UL

Default value for CMU_DPLLCTRL

Definition at line 651 of file efm32tg11b_cmu.h.

#define _CMU_FREEZE_MASK   0x00000001UL

Mask for CMU_FREEZE

Definition at line 1930 of file efm32tg11b_cmu.h.

#define _CMU_FREEZE_REGFREEZE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_FREEZE

Definition at line 1934 of file efm32tg11b_cmu.h.

#define _CMU_FREEZE_REGFREEZE_FREEZE   0x00000001UL

Mode FREEZE for CMU_FREEZE

Definition at line 1936 of file efm32tg11b_cmu.h.

#define _CMU_FREEZE_REGFREEZE_MASK   0x1UL

Bit mask for CMU_REGFREEZE

Definition at line 1933 of file efm32tg11b_cmu.h.

#define _CMU_FREEZE_REGFREEZE_SHIFT   0

Shift value for CMU_REGFREEZE

Definition at line 1932 of file efm32tg11b_cmu.h.

#define _CMU_FREEZE_REGFREEZE_UPDATE   0x00000000UL

Mode UPDATE for CMU_FREEZE

Definition at line 1935 of file efm32tg11b_cmu.h.

#define _CMU_FREEZE_RESETVALUE   0x00000000UL

Default value for CMU_FREEZE

Definition at line 1929 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFBUSCLKEN0

Definition at line 1505 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK   0x2UL

Bit mask for CMU_CRYPTO0

Definition at line 1504 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT   1

Shift value for CMU_CRYPTO0

Definition at line 1503 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFBUSCLKEN0

Definition at line 1525 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_GPCRC_MASK   0x20UL

Bit mask for CMU_GPCRC

Definition at line 1524 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT   5

Shift value for CMU_GPCRC

Definition at line 1523 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFBUSCLKEN0

Definition at line 1510 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_GPIO_MASK   0x4UL

Bit mask for CMU_GPIO

Definition at line 1509 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_GPIO_SHIFT   2

Shift value for CMU_GPIO

Definition at line 1508 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFBUSCLKEN0

Definition at line 1520 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_LDMA_MASK   0x10UL

Bit mask for CMU_LDMA

Definition at line 1519 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_LDMA_SHIFT   4

Shift value for CMU_LDMA

Definition at line 1518 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_LE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFBUSCLKEN0

Definition at line 1500 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_LE_MASK   0x1UL

Bit mask for CMU_LE

Definition at line 1499 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_LE_SHIFT   0

Shift value for CMU_LE

Definition at line 1498 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_HFBUSCLKEN0_MASK   0x0000003FUL

Mask for CMU_HFBUSCLKEN0

Definition at line 1496 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_PRS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFBUSCLKEN0

Definition at line 1515 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_PRS_MASK   0x8UL

Bit mask for CMU_PRS

Definition at line 1514 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_PRS_SHIFT   3

Shift value for CMU_PRS

Definition at line 1513 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSCLKEN0_RESETVALUE   0x00000000UL

Default value for CMU_HFBUSCLKEN0

Definition at line 1495 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSPRESC_MASK   0x0001FF00UL

Mask for CMU_HFBUSPRESC

Definition at line 1700 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSPRESC_PRESC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFBUSPRESC

Definition at line 1703 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSPRESC_PRESC_MASK   0x1FF00UL

Bit mask for CMU_PRESC

Definition at line 1702 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSPRESC_PRESC_NODIVISION   0x00000000UL

Mode NODIVISION for CMU_HFBUSPRESC

Definition at line 1704 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSPRESC_PRESC_SHIFT   8

Shift value for CMU_PRESC

Definition at line 1701 of file efm32tg11b_cmu.h.

#define _CMU_HFBUSPRESC_RESETVALUE   0x00000000UL

Default value for CMU_HFBUSPRESC

Definition at line 1699 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSEL_HF_CLKIN0   0x00000007UL

Mode CLKIN0 for CMU_HFCLKSEL

Definition at line 903 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSEL_HF_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFCLKSEL

Definition at line 897 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSEL_HF_HFRCO   0x00000001UL

Mode HFRCO for CMU_HFCLKSEL

Definition at line 898 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSEL_HF_HFRCODIV2   0x00000005UL

Mode HFRCODIV2 for CMU_HFCLKSEL

Definition at line 902 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSEL_HF_HFXO   0x00000002UL

Mode HFXO for CMU_HFCLKSEL

Definition at line 899 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSEL_HF_LFRCO   0x00000003UL

Mode LFRCO for CMU_HFCLKSEL

Definition at line 900 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSEL_HF_LFXO   0x00000004UL

Mode LFXO for CMU_HFCLKSEL

Definition at line 901 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSEL_HF_MASK   0x7UL

Bit mask for CMU_HF

Definition at line 896 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSEL_HF_SHIFT   0

Shift value for CMU_HF

Definition at line 895 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSEL_MASK   0x00000007UL

Mask for CMU_HFCLKSEL

Definition at line 894 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSEL_RESETVALUE   0x00000000UL

Default value for CMU_HFCLKSEL

Definition at line 893 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSTATUS_MASK   0x00000007UL

Mask for CMU_HFCLKSTATUS

Definition at line 1058 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSTATUS_RESETVALUE   0x00000001UL

Default value for CMU_HFCLKSTATUS

Definition at line 1057 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0   0x00000007UL

Mode CLKIN0 for CMU_HFCLKSTATUS

Definition at line 1067 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_HFCLKSTATUS

Definition at line 1061 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_HFRCO   0x00000001UL

Mode HFRCO for CMU_HFCLKSTATUS

Definition at line 1062 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2   0x00000005UL

Mode HFRCODIV2 for CMU_HFCLKSTATUS

Definition at line 1066 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_HFXO   0x00000002UL

Mode HFXO for CMU_HFCLKSTATUS

Definition at line 1063 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_LFRCO   0x00000003UL

Mode LFRCO for CMU_HFCLKSTATUS

Definition at line 1064 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_LFXO   0x00000004UL

Mode LFXO for CMU_HFCLKSTATUS

Definition at line 1065 of file efm32tg11b_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_MASK   0x7UL

Bit mask for CMU_SELECTED

Definition at line 1060 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockSelectGet(), CMU_DPLLLock(), SystemHFClockGet(), SystemHFXOClockSet(), and SystemLFXOClockSet().

#define _CMU_HFCLKSTATUS_SELECTED_SHIFT   0

Shift value for CMU_SELECTED

Definition at line 1059 of file efm32tg11b_cmu.h.

#define _CMU_HFCOREPRESC_MASK   0x0001FF00UL

Mask for CMU_HFCOREPRESC

Definition at line 1710 of file efm32tg11b_cmu.h.

#define _CMU_HFCOREPRESC_PRESC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFCOREPRESC

Definition at line 1713 of file efm32tg11b_cmu.h.

#define _CMU_HFCOREPRESC_PRESC_MASK   0x1FF00UL

Bit mask for CMU_PRESC

Definition at line 1712 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), CMU_ClockPrescSet(), and SystemCoreClockGet().

#define _CMU_HFCOREPRESC_PRESC_NODIVISION   0x00000000UL

Mode NODIVISION for CMU_HFCOREPRESC

Definition at line 1714 of file efm32tg11b_cmu.h.

#define _CMU_HFCOREPRESC_PRESC_SHIFT   8

Shift value for CMU_PRESC

Definition at line 1711 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), CMU_ClockPrescSet(), and SystemCoreClockGet().

#define _CMU_HFCOREPRESC_RESETVALUE   0x00000000UL

Default value for CMU_HFCOREPRESC

Definition at line 1709 of file efm32tg11b_cmu.h.

#define _CMU_HFEXPPRESC_MASK   0x00001F00UL

Mask for CMU_HFEXPPRESC

Definition at line 1730 of file efm32tg11b_cmu.h.

#define _CMU_HFEXPPRESC_PRESC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFEXPPRESC

Definition at line 1733 of file efm32tg11b_cmu.h.

#define _CMU_HFEXPPRESC_PRESC_MASK   0x1F00UL

Bit mask for CMU_PRESC

Definition at line 1732 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_HFEXPPRESC_PRESC_NODIVISION   0x00000000UL

Mode NODIVISION for CMU_HFEXPPRESC

Definition at line 1734 of file efm32tg11b_cmu.h.

#define _CMU_HFEXPPRESC_PRESC_SHIFT   8

Shift value for CMU_PRESC

Definition at line 1731 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_HFEXPPRESC_RESETVALUE   0x00000000UL

Default value for CMU_HFEXPPRESC

Definition at line 1729 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1574 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP0_MASK   0x100UL

Bit mask for CMU_ACMP0

Definition at line 1573 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP0_SHIFT   8

Shift value for CMU_ACMP0

Definition at line 1572 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1579 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP1_MASK   0x200UL

Bit mask for CMU_ACMP1

Definition at line 1578 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP1_SHIFT   9

Shift value for CMU_ACMP1

Definition at line 1577 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_ADC0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1589 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_ADC0_MASK   0x800UL

Bit mask for CMU_ADC0

Definition at line 1588 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_ADC0_SHIFT   11

Shift value for CMU_ADC0

Definition at line 1587 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1584 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK   0x400UL

Bit mask for CMU_CRYOTIMER

Definition at line 1583 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT   10

Shift value for CMU_CRYOTIMER

Definition at line 1582 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_I2C0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1564 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_I2C0_MASK   0x40UL

Bit mask for CMU_I2C0

Definition at line 1563 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_I2C0_SHIFT   6

Shift value for CMU_I2C0

Definition at line 1562 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_I2C1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1569 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_I2C1_MASK   0x80UL

Bit mask for CMU_I2C1

Definition at line 1568 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_I2C1_SHIFT   7

Shift value for CMU_I2C1

Definition at line 1567 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_MASK   0x00001FFFUL

Mask for CMU_HFPERCLKEN0

Definition at line 1530 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_RESETVALUE   0x00000000UL

Default value for CMU_HFPERCLKEN0

Definition at line 1529 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1554 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER0_MASK   0x10UL

Bit mask for CMU_TIMER0

Definition at line 1553 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER0_SHIFT   4

Shift value for CMU_TIMER0

Definition at line 1552 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1559 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER1_MASK   0x20UL

Bit mask for CMU_TIMER1

Definition at line 1558 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER1_SHIFT   5

Shift value for CMU_TIMER1

Definition at line 1557 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1594 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_TRNG0_MASK   0x1000UL

Bit mask for CMU_TRNG0

Definition at line 1593 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_TRNG0_SHIFT   12

Shift value for CMU_TRNG0

Definition at line 1592 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_USART0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1534 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_USART0_MASK   0x1UL

Bit mask for CMU_USART0

Definition at line 1533 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_USART0_SHIFT   0

Shift value for CMU_USART0

Definition at line 1532 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_USART1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1539 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_USART1_MASK   0x2UL

Bit mask for CMU_USART1

Definition at line 1538 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_USART1_SHIFT   1

Shift value for CMU_USART1

Definition at line 1537 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_USART2_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1544 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_USART2_MASK   0x4UL

Bit mask for CMU_USART2

Definition at line 1543 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_USART2_SHIFT   2

Shift value for CMU_USART2

Definition at line 1542 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_USART3_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1549 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_USART3_MASK   0x8UL

Bit mask for CMU_USART3

Definition at line 1548 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN0_USART3_SHIFT   3

Shift value for CMU_USART3

Definition at line 1547 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_CAN0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN1

Definition at line 1618 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_CAN0_MASK   0x8UL

Bit mask for CMU_CAN0

Definition at line 1617 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_CAN0_SHIFT   3

Shift value for CMU_CAN0

Definition at line 1616 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_CSEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN1

Definition at line 1628 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_CSEN_MASK   0x20UL

Bit mask for CMU_CSEN

Definition at line 1627 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_CSEN_SHIFT   5

Shift value for CMU_CSEN

Definition at line 1626 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_MASK   0x0000003FUL

Mask for CMU_HFPERCLKEN1

Definition at line 1599 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_RESETVALUE   0x00000000UL

Default value for CMU_HFPERCLKEN1

Definition at line 1598 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_UART0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN1

Definition at line 1603 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_UART0_MASK   0x1UL

Bit mask for CMU_UART0

Definition at line 1602 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_UART0_SHIFT   0

Shift value for CMU_UART0

Definition at line 1601 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN1

Definition at line 1623 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_VDAC0_MASK   0x10UL

Bit mask for CMU_VDAC0

Definition at line 1622 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_VDAC0_SHIFT   4

Shift value for CMU_VDAC0

Definition at line 1621 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN1

Definition at line 1608 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_WTIMER0_MASK   0x2UL

Bit mask for CMU_WTIMER0

Definition at line 1607 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT   1

Shift value for CMU_WTIMER0

Definition at line 1606 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN1

Definition at line 1613 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_WTIMER1_MASK   0x4UL

Bit mask for CMU_WTIMER1

Definition at line 1612 of file efm32tg11b_cmu.h.

#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT   2

Shift value for CMU_WTIMER1

Definition at line 1611 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESC_MASK   0x0001FF00UL

Mask for CMU_HFPERPRESC

Definition at line 1720 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESC_PRESC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERPRESC

Definition at line 1723 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESC_PRESC_MASK   0x1FF00UL

Bit mask for CMU_PRESC

Definition at line 1722 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_HFPERPRESC_PRESC_NODIVISION   0x00000000UL

Mode NODIVISION for CMU_HFPERPRESC

Definition at line 1724 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESC_PRESC_SHIFT   8

Shift value for CMU_PRESC

Definition at line 1721 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_HFPERPRESC_RESETVALUE   0x00000000UL

Default value for CMU_HFPERPRESC

Definition at line 1719 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESCB_MASK   0x0001FF00UL

Mask for CMU_HFPERPRESCB

Definition at line 1740 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESCB_PRESC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERPRESCB

Definition at line 1743 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESCB_PRESC_MASK   0x1FF00UL

Bit mask for CMU_PRESC

Definition at line 1742 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESCB_PRESC_NODIVISION   0x00000000UL

Mode NODIVISION for CMU_HFPERPRESCB

Definition at line 1744 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESCB_PRESC_SHIFT   8

Shift value for CMU_PRESC

Definition at line 1741 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESCB_RESETVALUE   0x00000000UL

Default value for CMU_HFPERPRESCB

Definition at line 1739 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESCC_MASK   0x0001FF00UL

Mask for CMU_HFPERPRESCC

Definition at line 1750 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESCC_PRESC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERPRESCC

Definition at line 1753 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESCC_PRESC_MASK   0x1FF00UL

Bit mask for CMU_PRESC

Definition at line 1752 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESCC_PRESC_NODIVISION   0x00000000UL

Mode NODIVISION for CMU_HFPERPRESCC

Definition at line 1754 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESCC_PRESC_SHIFT   8

Shift value for CMU_PRESC

Definition at line 1751 of file efm32tg11b_cmu.h.

#define _CMU_HFPERPRESCC_RESETVALUE   0x00000000UL

Default value for CMU_HFPERPRESCC

Definition at line 1749 of file efm32tg11b_cmu.h.

#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPRESC

Definition at line 1689 of file efm32tg11b_cmu.h.

#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2   0x00000000UL

Mode DIV2 for CMU_HFPRESC

Definition at line 1690 of file efm32tg11b_cmu.h.

#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4   0x00000001UL

Mode DIV4 for CMU_HFPRESC

Definition at line 1691 of file efm32tg11b_cmu.h.

#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8   0x00000002UL

Mode DIV8 for CMU_HFPRESC

Definition at line 1692 of file efm32tg11b_cmu.h.

#define _CMU_HFPRESC_HFCLKLEPRESC_MASK   0x3000000UL

Bit mask for CMU_HFCLKLEPRESC

Definition at line 1688 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT   24

Shift value for CMU_HFCLKLEPRESC

Definition at line 1687 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_HFPRESC_MASK   0x03001F00UL

Mask for CMU_HFPRESC

Definition at line 1680 of file efm32tg11b_cmu.h.

#define _CMU_HFPRESC_PRESC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPRESC

Definition at line 1683 of file efm32tg11b_cmu.h.

#define _CMU_HFPRESC_PRESC_MASK   0x1F00UL

Bit mask for CMU_PRESC

Definition at line 1682 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockPrescGet(), CMU_ClockPrescSet(), EMU_VScaleEM01(), EMU_VScaleEM01ByClock(), and SystemHFClockGet().

#define _CMU_HFPRESC_PRESC_NODIVISION   0x00000000UL

Mode NODIVISION for CMU_HFPRESC

Definition at line 1684 of file efm32tg11b_cmu.h.

#define _CMU_HFPRESC_PRESC_SHIFT   8

Shift value for CMU_PRESC

Definition at line 1681 of file efm32tg11b_cmu.h.

Referenced by CMU_ClockPrescGet(), CMU_ClockPrescSet(), EMU_VScaleEM01(), EMU_VScaleEM01ByClock(), and SystemHFClockGet().

#define _CMU_HFPRESC_RESETVALUE   0x00000000UL

Default value for CMU_HFPRESC

Definition at line 1679 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 280 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_CLKDIV_DIV1   0x00000000UL

Mode DIV1 for CMU_HFRCOCTRL

Definition at line 281 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_CLKDIV_DIV2   0x00000001UL

Mode DIV2 for CMU_HFRCOCTRL

Definition at line 282 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_CLKDIV_DIV4   0x00000002UL

Mode DIV4 for CMU_HFRCOCTRL

Definition at line 283 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_CLKDIV_MASK   0x6000000UL

Bit mask for CMU_CLKDIV

Definition at line 279 of file efm32tg11b_cmu.h.

Referenced by CMU_HFRCOBandSet(), and EMU_EnterEM4().

#define _CMU_HFRCOCTRL_CLKDIV_SHIFT   25

Shift value for CMU_CLKDIV

Definition at line 278 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT   0x00000002UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 271 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_CMPBIAS_MASK   0xE00000UL

Bit mask for CMU_CMPBIAS

Definition at line 270 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT   21

Shift value for CMU_CMPBIAS

Definition at line 269 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT   0x0000001FUL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 263 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_FINETUNING_MASK   0x3F00UL

Bit mask for CMU_FINETUNING

Definition at line 262 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_FINETUNING_SHIFT   8

Shift value for CMU_FINETUNING

Definition at line 261 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 291 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK   0x8000000UL

Bit mask for CMU_FINETUNINGEN

Definition at line 290 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT   27

Shift value for CMU_FINETUNINGEN

Definition at line 289 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT   0x00000008UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 267 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_FREQRANGE_MASK   0x1F0000UL

Bit mask for CMU_FREQRANGE

Definition at line 266 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT   16

Shift value for CMU_FREQRANGE

Definition at line 265 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_LDOHP_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 276 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_LDOHP_MASK   0x1000000UL

Bit mask for CMU_LDOHP

Definition at line 275 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_LDOHP_SHIFT   24

Shift value for CMU_LDOHP

Definition at line 274 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_MASK   0xFFFF3F7FUL

Mask for CMU_HFRCOCTRL

Definition at line 256 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_RESETVALUE   0xB1481F7FUL

Default value for CMU_HFRCOCTRL

Definition at line 255 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_TUNING_DEFAULT   0x0000007FUL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 259 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_TUNING_MASK   0x7FUL

Bit mask for CMU_TUNING

Definition at line 258 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock(), CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_HFRCOCTRL_TUNING_SHIFT   0

Shift value for CMU_TUNING

Definition at line 257 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock(), CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_HFRCOCTRL_VREFTC_DEFAULT   0x0000000BUL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 295 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_VREFTC_MASK   0xF0000000UL

Bit mask for CMU_VREFTC

Definition at line 294 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOCTRL_VREFTC_SHIFT   28

Shift value for CMU_VREFTC

Definition at line 293 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOSS_MASK   0x00001F07UL

Mask for CMU_HFRCOSS

Definition at line 2104 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOSS_RESETVALUE   0x00000000UL

Default value for CMU_HFRCOSS

Definition at line 2103 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOSS_SSAMP_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFRCOSS

Definition at line 2107 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOSS_SSAMP_MASK   0x7UL

Bit mask for CMU_SSAMP

Definition at line 2106 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock().

#define _CMU_HFRCOSS_SSAMP_SHIFT   0

Shift value for CMU_SSAMP

Definition at line 2105 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock().

#define _CMU_HFRCOSS_SSINV_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFRCOSS

Definition at line 2111 of file efm32tg11b_cmu.h.

#define _CMU_HFRCOSS_SSINV_MASK   0x1F00UL

Bit mask for CMU_SSINV

Definition at line 2110 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock().

#define _CMU_HFRCOSS_SSINV_SHIFT   8

Shift value for CMU_SSINV

Definition at line 2109 of file efm32tg11b_cmu.h.

Referenced by CMU_DPLLLock().

#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL

Definition at line 441 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK   0x10000000UL

Bit mask for CMU_AUTOSTARTEM0EM1

Definition at line 440 of file efm32tg11b_cmu.h.

Referenced by CMU_HFXOAutostartEnable().

#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT   28

Shift value for CMU_AUTOSTARTEM0EM1

Definition at line 439 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL

Definition at line 446 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK   0x20000000UL

Bit mask for CMU_AUTOSTARTSELEM0EM1

Definition at line 445 of file efm32tg11b_cmu.h.

Referenced by CMU_HFXOAutostartEnable().

#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT   29

Shift value for CMU_AUTOSTARTSELEM0EM1

Definition at line 444 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES   0x00000000UL

Mode 0CYCLES for CMU_HFXOCTRL

Definition at line 421 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES   0x00000003UL

Mode 16CYCLES for CMU_HFXOCTRL

Definition at line 424 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES   0x00000006UL

Mode 1KCYCLES for CMU_HFXOCTRL

Definition at line 427 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES   0x00000001UL

Mode 2CYCLES for CMU_HFXOCTRL

Definition at line 422 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES   0x00000004UL

Mode 32CYCLES for CMU_HFXOCTRL

Definition at line 425 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES   0x00000002UL

Mode 4CYCLES for CMU_HFXOCTRL

Definition at line 423 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES   0x00000007UL

Mode 4KCYCLES for CMU_HFXOCTRL

Definition at line 428 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES   0x00000005UL

Mode 64CYCLES for CMU_HFXOCTRL

Definition at line 426 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL

Definition at line 420 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_MASK   0x7000000UL

Bit mask for CMU_LFTIMEOUT

Definition at line 419 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT   24

Shift value for CMU_LFTIMEOUT

Definition at line 418 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_MASK   0x37000033UL

Mask for CMU_HFXOCTRL

Definition at line 393 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK   0x00000001UL

Mode ACBUFEXTCLK for CMU_HFXOCTRL

Definition at line 398 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK   0x00000002UL

Mode DCBUFEXTCLK for CMU_HFXOCTRL

Definition at line 399 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_MODE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL

Definition at line 396 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_MODE_DIGEXTCLK   0x00000003UL

Mode DIGEXTCLK for CMU_HFXOCTRL

Definition at line 400 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_MODE_MASK   0x3UL

Bit mask for CMU_MODE

Definition at line 395 of file efm32tg11b_cmu.h.

Referenced by CMU_HFXOInit(), and CMU_OscillatorEnable().

#define _CMU_HFXOCTRL_MODE_SHIFT   0

Shift value for CMU_MODE

Definition at line 394 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_MODE_XTAL   0x00000000UL

Mode XTAL for CMU_HFXOCTRL

Definition at line 397 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD   0x00000001UL

Mode AUTOCMD for CMU_HFXOCTRL

Definition at line 410 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_PEAKDETMODE_CMD   0x00000002UL

Mode CMD for CMU_HFXOCTRL

Definition at line 411 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL

Definition at line 408 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL   0x00000003UL

Mode MANUAL for CMU_HFXOCTRL

Definition at line 412 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_PEAKDETMODE_MASK   0x30UL

Bit mask for CMU_PEAKDETMODE

Definition at line 407 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD   0x00000000UL

Mode ONCECMD for CMU_HFXOCTRL

Definition at line 409 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT   4

Shift value for CMU_PEAKDETMODE

Definition at line 406 of file efm32tg11b_cmu.h.

#define _CMU_HFXOCTRL_RESETVALUE   0x00000000UL

Default value for CMU_HFXOCTRL

Definition at line 392 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOSTARTUPCTRL

Definition at line 458 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK   0xFF800UL

Bit mask for CMU_CTUNE

Definition at line 457 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT   11

Shift value for CMU_CTUNE

Definition at line 456 of file efm32tg11b_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT   0x00000600UL

Mode DEFAULT for CMU_HFXOSTARTUPCTRL

Definition at line 454 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK   0x7FFUL

Bit mask for CMU_IBTRIMXOCORE

Definition at line 453 of file efm32tg11b_cmu.h.

Referenced by CHIP_Init().

#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT   0

Shift value for CMU_IBTRIMXOCORE

Definition at line 452 of file efm32tg11b_cmu.h.

Referenced by CHIP_Init(), and CMU_HFXOInit().

#define _CMU_HFXOSTARTUPCTRL_MASK   0x000FFFFFUL

Mask for CMU_HFXOSTARTUPCTRL

Definition at line 451 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_RESETVALUE   0x00000600UL

Default value for CMU_HFXOSTARTUPCTRL

Definition at line 450 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL

Definition at line 470 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK   0xFF800UL

Bit mask for CMU_CTUNE

Definition at line 469 of file efm32tg11b_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT   11

Shift value for CMU_CTUNE

Definition at line 468 of file efm32tg11b_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT   0x00000100UL

Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL

Definition at line 466 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK   0x7FFUL

Bit mask for CMU_IBTRIMXOCORE

Definition at line 465 of file efm32tg11b_cmu.h.

Referenced by CMU_HFXOInit(), and CMU_OscillatorTuningSet().

#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT   0

Shift value for CMU_IBTRIMXOCORE

Definition at line 464 of file efm32tg11b_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOSTEADYSTATECTRL_MASK   0x0C0FFFFFUL

Mask for CMU_HFXOSTEADYSTATECTRL

Definition at line 463 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL

Definition at line 475 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK   0x4000000UL

Bit mask for CMU_PEAKDETEN

Definition at line 474 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT   26

Shift value for CMU_PEAKDETEN

Definition at line 473 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL

Definition at line 480 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK   0x8000000UL

Bit mask for CMU_PEAKMONEN

Definition at line 479 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT   27

Shift value for CMU_PEAKMONEN

Definition at line 478 of file efm32tg11b_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE   0x08000100UL

Default value for CMU_HFXOSTEADYSTATECTRL

Definition at line 462 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_MASK   0x0000F0FFUL

Mask for CMU_HFXOTIMEOUTCTRL

Definition at line 485 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES   0x00000005UL

Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 561 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES   0x0000000EUL

Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 571 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES   0x00000002UL

Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 558 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES   0x0000000BUL

Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 567 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES   0x00000007UL

Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 563 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES   0x00000006UL

Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 562 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES   0x00000000UL

Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 556 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES   0x00000008UL

Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 564 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES   0x00000003UL

Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 559 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES   0x0000000CUL

Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 568 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES   0x00000001UL

Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 557 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES   0x00000009UL

Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 565 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES   0x00000004UL

Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 560 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES   0x0000000DUL

Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 570 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES   0x0000000AUL

Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 566 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT   0x0000000DUL

Mode DEFAULT for CMU_HFXOTIMEOUTCTRL

Definition at line 569 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK   0xF000UL

Bit mask for CMU_PEAKDETTIMEOUT

Definition at line 555 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT   12

Shift value for CMU_PEAKDETTIMEOUT

Definition at line 554 of file efm32tg11b_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE   0x0000D04EUL

Default value for CMU_HFXOTIMEOUTCTRL

Definition at line 484 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES   0x00000005UL

Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 493 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES   0x0000000EUL

Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 503 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES   0x00000002UL

Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 490 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES   0x0000000BUL

Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 499 of file efm32tg11b_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES   0x00000007UL