|
#define
|
_UART_CLKDIV_AUTOBAUDEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CLKDIV_AUTOBAUDEN_MASK
0x80000000UL
|
|
#define
|
_UART_CLKDIV_AUTOBAUDEN_SHIFT
31
|
|
#define
|
_UART_CLKDIV_DIV_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CLKDIV_DIV_MASK
0x7FFFF8UL
|
|
#define
|
_UART_CLKDIV_DIV_SHIFT
3
|
|
#define
|
_UART_CLKDIV_MASK
0x807FFFF8UL
|
|
#define
|
_UART_CLKDIV_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_CMD_CLEARRX_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CMD_CLEARRX_MASK
0x800UL
|
|
#define
|
_UART_CMD_CLEARRX_SHIFT
11
|
|
#define
|
_UART_CMD_CLEARTX_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CMD_CLEARTX_MASK
0x400UL
|
|
#define
|
_UART_CMD_CLEARTX_SHIFT
10
|
|
#define
|
_UART_CMD_MASK
0x00000FFFUL
|
|
#define
|
_UART_CMD_MASTERDIS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CMD_MASTERDIS_MASK
0x20UL
|
|
#define
|
_UART_CMD_MASTERDIS_SHIFT
5
|
|
#define
|
_UART_CMD_MASTEREN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CMD_MASTEREN_MASK
0x10UL
|
|
#define
|
_UART_CMD_MASTEREN_SHIFT
4
|
|
#define
|
_UART_CMD_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_CMD_RXBLOCKDIS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CMD_RXBLOCKDIS_MASK
0x80UL
|
|
#define
|
_UART_CMD_RXBLOCKDIS_SHIFT
7
|
|
#define
|
_UART_CMD_RXBLOCKEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CMD_RXBLOCKEN_MASK
0x40UL
|
|
#define
|
_UART_CMD_RXBLOCKEN_SHIFT
6
|
|
#define
|
_UART_CMD_RXDIS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CMD_RXDIS_MASK
0x2UL
|
|
#define
|
_UART_CMD_RXDIS_SHIFT
1
|
|
#define
|
_UART_CMD_RXEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CMD_RXEN_MASK
0x1UL
|
|
#define
|
_UART_CMD_RXEN_SHIFT
0
|
|
#define
|
_UART_CMD_TXDIS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CMD_TXDIS_MASK
0x8UL
|
|
#define
|
_UART_CMD_TXDIS_SHIFT
3
|
|
#define
|
_UART_CMD_TXEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CMD_TXEN_MASK
0x4UL
|
|
#define
|
_UART_CMD_TXEN_SHIFT
2
|
|
#define
|
_UART_CMD_TXTRIDIS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CMD_TXTRIDIS_MASK
0x200UL
|
|
#define
|
_UART_CMD_TXTRIDIS_SHIFT
9
|
|
#define
|
_UART_CMD_TXTRIEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CMD_TXTRIEN_MASK
0x100UL
|
|
#define
|
_UART_CMD_TXTRIEN_SHIFT
8
|
|
#define
|
_UART_CTRL_AUTOCS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_AUTOCS_MASK
0x10000UL
|
|
#define
|
_UART_CTRL_AUTOCS_SHIFT
16
|
|
#define
|
_UART_CTRL_AUTOTRI_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_AUTOTRI_MASK
0x20000UL
|
|
#define
|
_UART_CTRL_AUTOTRI_SHIFT
17
|
|
#define
|
_UART_CTRL_AUTOTX_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_AUTOTX_MASK
0x20000000UL
|
|
#define
|
_UART_CTRL_AUTOTX_SHIFT
29
|
|
#define
|
_UART_CTRL_BIT8DV_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_BIT8DV_MASK
0x200000UL
|
|
#define
|
_UART_CTRL_BIT8DV_SHIFT
21
|
|
#define
|
_UART_CTRL_BYTESWAP_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_BYTESWAP_MASK
0x10000000UL
|
|
#define
|
_UART_CTRL_BYTESWAP_SHIFT
28
|
|
#define
|
_UART_CTRL_CCEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_CCEN_MASK
0x4UL
|
|
#define
|
_UART_CTRL_CCEN_SHIFT
2
|
|
#define
|
_UART_CTRL_CLKPHA_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_CLKPHA_MASK
0x200UL
|
|
#define
|
_UART_CTRL_CLKPHA_SAMPLELEADING
0x00000000UL
|
|
#define
|
_UART_CTRL_CLKPHA_SAMPLETRAILING
0x00000001UL
|
|
#define
|
_UART_CTRL_CLKPHA_SHIFT
9
|
|
#define
|
_UART_CTRL_CLKPOL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_CLKPOL_IDLEHIGH
0x00000001UL
|
|
#define
|
_UART_CTRL_CLKPOL_IDLELOW
0x00000000UL
|
|
#define
|
_UART_CTRL_CLKPOL_MASK
0x100UL
|
|
#define
|
_UART_CTRL_CLKPOL_SHIFT
8
|
|
#define
|
_UART_CTRL_CSINV_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_CSINV_MASK
0x8000UL
|
|
#define
|
_UART_CTRL_CSINV_SHIFT
15
|
|
#define
|
_UART_CTRL_CSMA_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_CSMA_GOTOSLAVEMODE
0x00000001UL
|
|
#define
|
_UART_CTRL_CSMA_MASK
0x800UL
|
|
#define
|
_UART_CTRL_CSMA_NOACTION
0x00000000UL
|
|
#define
|
_UART_CTRL_CSMA_SHIFT
11
|
|
#define
|
_UART_CTRL_ERRSDMA_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_ERRSDMA_MASK
0x400000UL
|
|
#define
|
_UART_CTRL_ERRSDMA_SHIFT
22
|
|
#define
|
_UART_CTRL_ERRSRX_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_ERRSRX_MASK
0x800000UL
|
|
#define
|
_UART_CTRL_ERRSRX_SHIFT
23
|
|
#define
|
_UART_CTRL_ERRSTX_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_ERRSTX_MASK
0x1000000UL
|
|
#define
|
_UART_CTRL_ERRSTX_SHIFT
24
|
|
#define
|
_UART_CTRL_LOOPBK_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_LOOPBK_MASK
0x2UL
|
|
#define
|
_UART_CTRL_LOOPBK_SHIFT
1
|
|
#define
|
_UART_CTRL_MASK
0xF3FFFF7FUL
|
|
#define
|
_UART_CTRL_MPAB_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_MPAB_MASK
0x10UL
|
|
#define
|
_UART_CTRL_MPAB_SHIFT
4
|
|
#define
|
_UART_CTRL_MPM_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_MPM_MASK
0x8UL
|
|
#define
|
_UART_CTRL_MPM_SHIFT
3
|
|
#define
|
_UART_CTRL_MSBF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_MSBF_MASK
0x400UL
|
|
#define
|
_UART_CTRL_MSBF_SHIFT
10
|
|
#define
|
_UART_CTRL_MVDIS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_MVDIS_MASK
0x40000000UL
|
|
#define
|
_UART_CTRL_MVDIS_SHIFT
30
|
|
#define
|
_UART_CTRL_OVS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_OVS_MASK
0x60UL
|
|
#define
|
_UART_CTRL_OVS_SHIFT
5
|
|
#define
|
_UART_CTRL_OVS_X16
0x00000000UL
|
|
#define
|
_UART_CTRL_OVS_X4
0x00000003UL
|
|
#define
|
_UART_CTRL_OVS_X6
0x00000002UL
|
|
#define
|
_UART_CTRL_OVS_X8
0x00000001UL
|
|
#define
|
_UART_CTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_CTRL_RXINV_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_RXINV_MASK
0x2000UL
|
|
#define
|
_UART_CTRL_RXINV_SHIFT
13
|
|
#define
|
_UART_CTRL_SCMODE_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_SCMODE_MASK
0x40000UL
|
|
#define
|
_UART_CTRL_SCMODE_SHIFT
18
|
|
#define
|
_UART_CTRL_SCRETRANS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_SCRETRANS_MASK
0x80000UL
|
|
#define
|
_UART_CTRL_SCRETRANS_SHIFT
19
|
|
#define
|
_UART_CTRL_SKIPPERRF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_SKIPPERRF_MASK
0x100000UL
|
|
#define
|
_UART_CTRL_SKIPPERRF_SHIFT
20
|
|
#define
|
_UART_CTRL_SMSDELAY_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_SMSDELAY_MASK
0x80000000UL
|
|
#define
|
_UART_CTRL_SMSDELAY_SHIFT
31
|
|
#define
|
_UART_CTRL_SSSEARLY_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_SSSEARLY_MASK
0x2000000UL
|
|
#define
|
_UART_CTRL_SSSEARLY_SHIFT
25
|
|
#define
|
_UART_CTRL_SYNC_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_SYNC_MASK
0x1UL
|
|
#define
|
_UART_CTRL_SYNC_SHIFT
0
|
|
#define
|
_UART_CTRL_TXBIL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_TXBIL_EMPTY
0x00000000UL
|
|
#define
|
_UART_CTRL_TXBIL_HALFFULL
0x00000001UL
|
|
#define
|
_UART_CTRL_TXBIL_MASK
0x1000UL
|
|
#define
|
_UART_CTRL_TXBIL_SHIFT
12
|
|
#define
|
_UART_CTRL_TXINV_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRL_TXINV_MASK
0x4000UL
|
|
#define
|
_UART_CTRL_TXINV_SHIFT
14
|
|
#define
|
_UART_CTRLX_CTSEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRLX_CTSEN_MASK
0x4UL
|
|
#define
|
_UART_CTRLX_CTSEN_SHIFT
2
|
|
#define
|
_UART_CTRLX_CTSINV_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRLX_CTSINV_MASK
0x2UL
|
|
#define
|
_UART_CTRLX_CTSINV_SHIFT
1
|
|
#define
|
_UART_CTRLX_DBGHALT_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRLX_DBGHALT_MASK
0x1UL
|
|
#define
|
_UART_CTRLX_DBGHALT_SHIFT
0
|
|
#define
|
_UART_CTRLX_MASK
0x0000000FUL
|
|
#define
|
_UART_CTRLX_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_CTRLX_RTSINV_DEFAULT
0x00000000UL
|
|
#define
|
_UART_CTRLX_RTSINV_MASK
0x8UL
|
|
#define
|
_UART_CTRLX_RTSINV_SHIFT
3
|
|
#define
|
_UART_FRAME_DATABITS_DEFAULT
0x00000005UL
|
|
#define
|
_UART_FRAME_DATABITS_EIGHT
0x00000005UL
|
|
#define
|
_UART_FRAME_DATABITS_ELEVEN
0x00000008UL
|
|
#define
|
_UART_FRAME_DATABITS_FIFTEEN
0x0000000CUL
|
|
#define
|
_UART_FRAME_DATABITS_FIVE
0x00000002UL
|
|
#define
|
_UART_FRAME_DATABITS_FOUR
0x00000001UL
|
|
#define
|
_UART_FRAME_DATABITS_FOURTEEN
0x0000000BUL
|
|
#define
|
_UART_FRAME_DATABITS_MASK
0xFUL
|
|
#define
|
_UART_FRAME_DATABITS_NINE
0x00000006UL
|
|
#define
|
_UART_FRAME_DATABITS_SEVEN
0x00000004UL
|
|
#define
|
_UART_FRAME_DATABITS_SHIFT
0
|
|
#define
|
_UART_FRAME_DATABITS_SIX
0x00000003UL
|
|
#define
|
_UART_FRAME_DATABITS_SIXTEEN
0x0000000DUL
|
|
#define
|
_UART_FRAME_DATABITS_TEN
0x00000007UL
|
|
#define
|
_UART_FRAME_DATABITS_THIRTEEN
0x0000000AUL
|
|
#define
|
_UART_FRAME_DATABITS_TWELVE
0x00000009UL
|
|
#define
|
_UART_FRAME_MASK
0x0000330FUL
|
|
#define
|
_UART_FRAME_PARITY_DEFAULT
0x00000000UL
|
|
#define
|
_UART_FRAME_PARITY_EVEN
0x00000002UL
|
|
#define
|
_UART_FRAME_PARITY_MASK
0x300UL
|
|
#define
|
_UART_FRAME_PARITY_NONE
0x00000000UL
|
|
#define
|
_UART_FRAME_PARITY_ODD
0x00000003UL
|
|
#define
|
_UART_FRAME_PARITY_SHIFT
8
|
|
#define
|
_UART_FRAME_RESETVALUE
0x00001005UL
|
|
#define
|
_UART_FRAME_STOPBITS_DEFAULT
0x00000001UL
|
|
#define
|
_UART_FRAME_STOPBITS_HALF
0x00000000UL
|
|
#define
|
_UART_FRAME_STOPBITS_MASK
0x3000UL
|
|
#define
|
_UART_FRAME_STOPBITS_ONE
0x00000001UL
|
|
#define
|
_UART_FRAME_STOPBITS_ONEANDAHALF
0x00000002UL
|
|
#define
|
_UART_FRAME_STOPBITS_SHIFT
12
|
|
#define
|
_UART_FRAME_STOPBITS_TWO
0x00000003UL
|
|
#define
|
_UART_I2SCTRL_DELAY_DEFAULT
0x00000000UL
|
|
#define
|
_UART_I2SCTRL_DELAY_MASK
0x10UL
|
|
#define
|
_UART_I2SCTRL_DELAY_SHIFT
4
|
|
#define
|
_UART_I2SCTRL_DMASPLIT_DEFAULT
0x00000000UL
|
|
#define
|
_UART_I2SCTRL_DMASPLIT_MASK
0x8UL
|
|
#define
|
_UART_I2SCTRL_DMASPLIT_SHIFT
3
|
|
#define
|
_UART_I2SCTRL_EN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_I2SCTRL_EN_MASK
0x1UL
|
|
#define
|
_UART_I2SCTRL_EN_SHIFT
0
|
|
#define
|
_UART_I2SCTRL_FORMAT_DEFAULT
0x00000000UL
|
|
#define
|
_UART_I2SCTRL_FORMAT_MASK
0x700UL
|
|
#define
|
_UART_I2SCTRL_FORMAT_SHIFT
8
|
|
#define
|
_UART_I2SCTRL_FORMAT_W16D16
0x00000005UL
|
|
#define
|
_UART_I2SCTRL_FORMAT_W16D8
0x00000006UL
|
|
#define
|
_UART_I2SCTRL_FORMAT_W32D16
0x00000003UL
|
|
#define
|
_UART_I2SCTRL_FORMAT_W32D24
0x00000002UL
|
|
#define
|
_UART_I2SCTRL_FORMAT_W32D24M
0x00000001UL
|
|
#define
|
_UART_I2SCTRL_FORMAT_W32D32
0x00000000UL
|
|
#define
|
_UART_I2SCTRL_FORMAT_W32D8
0x00000004UL
|
|
#define
|
_UART_I2SCTRL_FORMAT_W8D8
0x00000007UL
|
|
#define
|
_UART_I2SCTRL_JUSTIFY_DEFAULT
0x00000000UL
|
|
#define
|
_UART_I2SCTRL_JUSTIFY_LEFT
0x00000000UL
|
|
#define
|
_UART_I2SCTRL_JUSTIFY_MASK
0x4UL
|
|
#define
|
_UART_I2SCTRL_JUSTIFY_RIGHT
0x00000001UL
|
|
#define
|
_UART_I2SCTRL_JUSTIFY_SHIFT
2
|
|
#define
|
_UART_I2SCTRL_MASK
0x0000071FUL
|
|
#define
|
_UART_I2SCTRL_MONO_DEFAULT
0x00000000UL
|
|
#define
|
_UART_I2SCTRL_MONO_MASK
0x2UL
|
|
#define
|
_UART_I2SCTRL_MONO_SHIFT
1
|
|
#define
|
_UART_I2SCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_IEN_CCF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_CCF_MASK
0x1000UL
|
|
#define
|
_UART_IEN_CCF_SHIFT
12
|
|
#define
|
_UART_IEN_FERR_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_FERR_MASK
0x200UL
|
|
#define
|
_UART_IEN_FERR_SHIFT
9
|
|
#define
|
_UART_IEN_MASK
0x0001FFFFUL
|
|
#define
|
_UART_IEN_MPAF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_MPAF_MASK
0x400UL
|
|
#define
|
_UART_IEN_MPAF_SHIFT
10
|
|
#define
|
_UART_IEN_PERR_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_PERR_MASK
0x100UL
|
|
#define
|
_UART_IEN_PERR_SHIFT
8
|
|
#define
|
_UART_IEN_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_IEN_RXDATAV_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_RXDATAV_MASK
0x4UL
|
|
#define
|
_UART_IEN_RXDATAV_SHIFT
2
|
|
#define
|
_UART_IEN_RXFULL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_RXFULL_MASK
0x8UL
|
|
#define
|
_UART_IEN_RXFULL_SHIFT
3
|
|
#define
|
_UART_IEN_RXOF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_RXOF_MASK
0x10UL
|
|
#define
|
_UART_IEN_RXOF_SHIFT
4
|
|
#define
|
_UART_IEN_RXUF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_RXUF_MASK
0x20UL
|
|
#define
|
_UART_IEN_RXUF_SHIFT
5
|
|
#define
|
_UART_IEN_SSM_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_SSM_MASK
0x800UL
|
|
#define
|
_UART_IEN_SSM_SHIFT
11
|
|
#define
|
_UART_IEN_TCMP0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_TCMP0_MASK
0x4000UL
|
|
#define
|
_UART_IEN_TCMP0_SHIFT
14
|
|
#define
|
_UART_IEN_TCMP1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_TCMP1_MASK
0x8000UL
|
|
#define
|
_UART_IEN_TCMP1_SHIFT
15
|
|
#define
|
_UART_IEN_TCMP2_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_TCMP2_MASK
0x10000UL
|
|
#define
|
_UART_IEN_TCMP2_SHIFT
16
|
|
#define
|
_UART_IEN_TXBL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_TXBL_MASK
0x2UL
|
|
#define
|
_UART_IEN_TXBL_SHIFT
1
|
|
#define
|
_UART_IEN_TXC_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_TXC_MASK
0x1UL
|
|
#define
|
_UART_IEN_TXC_SHIFT
0
|
|
#define
|
_UART_IEN_TXIDLE_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_TXIDLE_MASK
0x2000UL
|
|
#define
|
_UART_IEN_TXIDLE_SHIFT
13
|
|
#define
|
_UART_IEN_TXOF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_TXOF_MASK
0x40UL
|
|
#define
|
_UART_IEN_TXOF_SHIFT
6
|
|
#define
|
_UART_IEN_TXUF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IEN_TXUF_MASK
0x80UL
|
|
#define
|
_UART_IEN_TXUF_SHIFT
7
|
|
#define
|
_UART_IF_CCF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_CCF_MASK
0x1000UL
|
|
#define
|
_UART_IF_CCF_SHIFT
12
|
|
#define
|
_UART_IF_FERR_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_FERR_MASK
0x200UL
|
|
#define
|
_UART_IF_FERR_SHIFT
9
|
|
#define
|
_UART_IF_MASK
0x0001FFFFUL
|
|
#define
|
_UART_IF_MPAF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_MPAF_MASK
0x400UL
|
|
#define
|
_UART_IF_MPAF_SHIFT
10
|
|
#define
|
_UART_IF_PERR_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_PERR_MASK
0x100UL
|
|
#define
|
_UART_IF_PERR_SHIFT
8
|
|
#define
|
_UART_IF_RESETVALUE
0x00000002UL
|
|
#define
|
_UART_IF_RXDATAV_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_RXDATAV_MASK
0x4UL
|
|
#define
|
_UART_IF_RXDATAV_SHIFT
2
|
|
#define
|
_UART_IF_RXFULL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_RXFULL_MASK
0x8UL
|
|
#define
|
_UART_IF_RXFULL_SHIFT
3
|
|
#define
|
_UART_IF_RXOF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_RXOF_MASK
0x10UL
|
|
#define
|
_UART_IF_RXOF_SHIFT
4
|
|
#define
|
_UART_IF_RXUF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_RXUF_MASK
0x20UL
|
|
#define
|
_UART_IF_RXUF_SHIFT
5
|
|
#define
|
_UART_IF_SSM_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_SSM_MASK
0x800UL
|
|
#define
|
_UART_IF_SSM_SHIFT
11
|
|
#define
|
_UART_IF_TCMP0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_TCMP0_MASK
0x4000UL
|
|
#define
|
_UART_IF_TCMP0_SHIFT
14
|
|
#define
|
_UART_IF_TCMP1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_TCMP1_MASK
0x8000UL
|
|
#define
|
_UART_IF_TCMP1_SHIFT
15
|
|
#define
|
_UART_IF_TCMP2_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_TCMP2_MASK
0x10000UL
|
|
#define
|
_UART_IF_TCMP2_SHIFT
16
|
|
#define
|
_UART_IF_TXBL_DEFAULT
0x00000001UL
|
|
#define
|
_UART_IF_TXBL_MASK
0x2UL
|
|
#define
|
_UART_IF_TXBL_SHIFT
1
|
|
#define
|
_UART_IF_TXC_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_TXC_MASK
0x1UL
|
|
#define
|
_UART_IF_TXC_SHIFT
0
|
|
#define
|
_UART_IF_TXIDLE_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_TXIDLE_MASK
0x2000UL
|
|
#define
|
_UART_IF_TXIDLE_SHIFT
13
|
|
#define
|
_UART_IF_TXOF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_TXOF_MASK
0x40UL
|
|
#define
|
_UART_IF_TXOF_SHIFT
6
|
|
#define
|
_UART_IF_TXUF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IF_TXUF_MASK
0x80UL
|
|
#define
|
_UART_IF_TXUF_SHIFT
7
|
|
#define
|
_UART_IFC_CCF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_CCF_MASK
0x1000UL
|
|
#define
|
_UART_IFC_CCF_SHIFT
12
|
|
#define
|
_UART_IFC_FERR_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_FERR_MASK
0x200UL
|
|
#define
|
_UART_IFC_FERR_SHIFT
9
|
|
#define
|
_UART_IFC_MASK
0x0001FFF9UL
|
|
#define
|
_UART_IFC_MPAF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_MPAF_MASK
0x400UL
|
|
#define
|
_UART_IFC_MPAF_SHIFT
10
|
|
#define
|
_UART_IFC_PERR_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_PERR_MASK
0x100UL
|
|
#define
|
_UART_IFC_PERR_SHIFT
8
|
|
#define
|
_UART_IFC_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_IFC_RXFULL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_RXFULL_MASK
0x8UL
|
|
#define
|
_UART_IFC_RXFULL_SHIFT
3
|
|
#define
|
_UART_IFC_RXOF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_RXOF_MASK
0x10UL
|
|
#define
|
_UART_IFC_RXOF_SHIFT
4
|
|
#define
|
_UART_IFC_RXUF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_RXUF_MASK
0x20UL
|
|
#define
|
_UART_IFC_RXUF_SHIFT
5
|
|
#define
|
_UART_IFC_SSM_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_SSM_MASK
0x800UL
|
|
#define
|
_UART_IFC_SSM_SHIFT
11
|
|
#define
|
_UART_IFC_TCMP0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_TCMP0_MASK
0x4000UL
|
|
#define
|
_UART_IFC_TCMP0_SHIFT
14
|
|
#define
|
_UART_IFC_TCMP1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_TCMP1_MASK
0x8000UL
|
|
#define
|
_UART_IFC_TCMP1_SHIFT
15
|
|
#define
|
_UART_IFC_TCMP2_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_TCMP2_MASK
0x10000UL
|
|
#define
|
_UART_IFC_TCMP2_SHIFT
16
|
|
#define
|
_UART_IFC_TXC_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_TXC_MASK
0x1UL
|
|
#define
|
_UART_IFC_TXC_SHIFT
0
|
|
#define
|
_UART_IFC_TXIDLE_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_TXIDLE_MASK
0x2000UL
|
|
#define
|
_UART_IFC_TXIDLE_SHIFT
13
|
|
#define
|
_UART_IFC_TXOF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_TXOF_MASK
0x40UL
|
|
#define
|
_UART_IFC_TXOF_SHIFT
6
|
|
#define
|
_UART_IFC_TXUF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFC_TXUF_MASK
0x80UL
|
|
#define
|
_UART_IFC_TXUF_SHIFT
7
|
|
#define
|
_UART_IFS_CCF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_CCF_MASK
0x1000UL
|
|
#define
|
_UART_IFS_CCF_SHIFT
12
|
|
#define
|
_UART_IFS_FERR_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_FERR_MASK
0x200UL
|
|
#define
|
_UART_IFS_FERR_SHIFT
9
|
|
#define
|
_UART_IFS_MASK
0x0001FFF9UL
|
|
#define
|
_UART_IFS_MPAF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_MPAF_MASK
0x400UL
|
|
#define
|
_UART_IFS_MPAF_SHIFT
10
|
|
#define
|
_UART_IFS_PERR_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_PERR_MASK
0x100UL
|
|
#define
|
_UART_IFS_PERR_SHIFT
8
|
|
#define
|
_UART_IFS_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_IFS_RXFULL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_RXFULL_MASK
0x8UL
|
|
#define
|
_UART_IFS_RXFULL_SHIFT
3
|
|
#define
|
_UART_IFS_RXOF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_RXOF_MASK
0x10UL
|
|
#define
|
_UART_IFS_RXOF_SHIFT
4
|
|
#define
|
_UART_IFS_RXUF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_RXUF_MASK
0x20UL
|
|
#define
|
_UART_IFS_RXUF_SHIFT
5
|
|
#define
|
_UART_IFS_SSM_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_SSM_MASK
0x800UL
|
|
#define
|
_UART_IFS_SSM_SHIFT
11
|
|
#define
|
_UART_IFS_TCMP0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_TCMP0_MASK
0x4000UL
|
|
#define
|
_UART_IFS_TCMP0_SHIFT
14
|
|
#define
|
_UART_IFS_TCMP1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_TCMP1_MASK
0x8000UL
|
|
#define
|
_UART_IFS_TCMP1_SHIFT
15
|
|
#define
|
_UART_IFS_TCMP2_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_TCMP2_MASK
0x10000UL
|
|
#define
|
_UART_IFS_TCMP2_SHIFT
16
|
|
#define
|
_UART_IFS_TXC_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_TXC_MASK
0x1UL
|
|
#define
|
_UART_IFS_TXC_SHIFT
0
|
|
#define
|
_UART_IFS_TXIDLE_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_TXIDLE_MASK
0x2000UL
|
|
#define
|
_UART_IFS_TXIDLE_SHIFT
13
|
|
#define
|
_UART_IFS_TXOF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_TXOF_MASK
0x40UL
|
|
#define
|
_UART_IFS_TXOF_SHIFT
6
|
|
#define
|
_UART_IFS_TXUF_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IFS_TXUF_MASK
0x80UL
|
|
#define
|
_UART_IFS_TXUF_SHIFT
7
|
|
#define
|
_UART_INPUT_CLKPRS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_INPUT_CLKPRS_MASK
0x8000UL
|
|
#define
|
_UART_INPUT_CLKPRS_SHIFT
15
|
|
#define
|
_UART_INPUT_CLKPRSSEL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_INPUT_CLKPRSSEL_MASK
0x700UL
|
|
#define
|
_UART_INPUT_CLKPRSSEL_PRSCH0
0x00000000UL
|
|
#define
|
_UART_INPUT_CLKPRSSEL_PRSCH1
0x00000001UL
|
|
#define
|
_UART_INPUT_CLKPRSSEL_PRSCH2
0x00000002UL
|
|
#define
|
_UART_INPUT_CLKPRSSEL_PRSCH3
0x00000003UL
|
|
#define
|
_UART_INPUT_CLKPRSSEL_PRSCH4
0x00000004UL
|
|
#define
|
_UART_INPUT_CLKPRSSEL_PRSCH5
0x00000005UL
|
|
#define
|
_UART_INPUT_CLKPRSSEL_PRSCH6
0x00000006UL
|
|
#define
|
_UART_INPUT_CLKPRSSEL_PRSCH7
0x00000007UL
|
|
#define
|
_UART_INPUT_CLKPRSSEL_SHIFT
8
|
|
#define
|
_UART_INPUT_MASK
0x00008787UL
|
|
#define
|
_UART_INPUT_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_INPUT_RXPRS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_INPUT_RXPRS_MASK
0x80UL
|
|
#define
|
_UART_INPUT_RXPRS_SHIFT
7
|
|
#define
|
_UART_INPUT_RXPRSSEL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_INPUT_RXPRSSEL_MASK
0x7UL
|
|
#define
|
_UART_INPUT_RXPRSSEL_PRSCH0
0x00000000UL
|
|
#define
|
_UART_INPUT_RXPRSSEL_PRSCH1
0x00000001UL
|
|
#define
|
_UART_INPUT_RXPRSSEL_PRSCH2
0x00000002UL
|
|
#define
|
_UART_INPUT_RXPRSSEL_PRSCH3
0x00000003UL
|
|
#define
|
_UART_INPUT_RXPRSSEL_PRSCH4
0x00000004UL
|
|
#define
|
_UART_INPUT_RXPRSSEL_PRSCH5
0x00000005UL
|
|
#define
|
_UART_INPUT_RXPRSSEL_PRSCH6
0x00000006UL
|
|
#define
|
_UART_INPUT_RXPRSSEL_PRSCH7
0x00000007UL
|
|
#define
|
_UART_INPUT_RXPRSSEL_SHIFT
0
|
|
#define
|
_UART_IRCTRL_IREN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IRCTRL_IREN_MASK
0x1UL
|
|
#define
|
_UART_IRCTRL_IREN_SHIFT
0
|
|
#define
|
_UART_IRCTRL_IRFILT_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IRCTRL_IRFILT_MASK
0x8UL
|
|
#define
|
_UART_IRCTRL_IRFILT_SHIFT
3
|
|
#define
|
_UART_IRCTRL_IRPRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IRCTRL_IRPRSEN_MASK
0x80UL
|
|
#define
|
_UART_IRCTRL_IRPRSEN_SHIFT
7
|
|
#define
|
_UART_IRCTRL_IRPRSSEL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IRCTRL_IRPRSSEL_MASK
0x700UL
|
|
#define
|
_UART_IRCTRL_IRPRSSEL_PRSCH0
0x00000000UL
|
|
#define
|
_UART_IRCTRL_IRPRSSEL_PRSCH1
0x00000001UL
|
|
#define
|
_UART_IRCTRL_IRPRSSEL_PRSCH2
0x00000002UL
|
|
#define
|
_UART_IRCTRL_IRPRSSEL_PRSCH3
0x00000003UL
|
|
#define
|
_UART_IRCTRL_IRPRSSEL_PRSCH4
0x00000004UL
|
|
#define
|
_UART_IRCTRL_IRPRSSEL_PRSCH5
0x00000005UL
|
|
#define
|
_UART_IRCTRL_IRPRSSEL_PRSCH6
0x00000006UL
|
|
#define
|
_UART_IRCTRL_IRPRSSEL_PRSCH7
0x00000007UL
|
|
#define
|
_UART_IRCTRL_IRPRSSEL_SHIFT
8
|
|
#define
|
_UART_IRCTRL_IRPW_DEFAULT
0x00000000UL
|
|
#define
|
_UART_IRCTRL_IRPW_FOUR
0x00000003UL
|
|
#define
|
_UART_IRCTRL_IRPW_MASK
0x6UL
|
|
#define
|
_UART_IRCTRL_IRPW_ONE
0x00000000UL
|
|
#define
|
_UART_IRCTRL_IRPW_SHIFT
1
|
|
#define
|
_UART_IRCTRL_IRPW_THREE
0x00000002UL
|
|
#define
|
_UART_IRCTRL_IRPW_TWO
0x00000001UL
|
|
#define
|
_UART_IRCTRL_MASK
0x0000078FUL
|
|
#define
|
_UART_IRCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_ROUTELOC0_CLKLOC_DEFAULT
0x00000000UL
|
|
#define
|
_UART_ROUTELOC0_CLKLOC_LOC0
0x00000000UL
|
|
#define
|
_UART_ROUTELOC0_CLKLOC_LOC1
0x00000001UL
|
|
#define
|
_UART_ROUTELOC0_CLKLOC_LOC2
0x00000002UL
|
|
#define
|
_UART_ROUTELOC0_CLKLOC_LOC3
0x00000003UL
|
|
#define
|
_UART_ROUTELOC0_CLKLOC_LOC4
0x00000004UL
|
|
#define
|
_UART_ROUTELOC0_CLKLOC_LOC5
0x00000005UL
|
|
#define
|
_UART_ROUTELOC0_CLKLOC_LOC6
0x00000006UL
|
|
#define
|
_UART_ROUTELOC0_CLKLOC_MASK
0x7000000UL
|
|
#define
|
_UART_ROUTELOC0_CLKLOC_SHIFT
24
|
|
#define
|
_UART_ROUTELOC0_CSLOC_DEFAULT
0x00000000UL
|
|
#define
|
_UART_ROUTELOC0_CSLOC_LOC0
0x00000000UL
|
|
#define
|
_UART_ROUTELOC0_CSLOC_LOC1
0x00000001UL
|
|
#define
|
_UART_ROUTELOC0_CSLOC_LOC2
0x00000002UL
|
|
#define
|
_UART_ROUTELOC0_CSLOC_LOC3
0x00000003UL
|
|
#define
|
_UART_ROUTELOC0_CSLOC_LOC4
0x00000004UL
|
|
#define
|
_UART_ROUTELOC0_CSLOC_LOC5
0x00000005UL
|
|
#define
|
_UART_ROUTELOC0_CSLOC_LOC6
0x00000006UL
|
|
#define
|
_UART_ROUTELOC0_CSLOC_MASK
0x70000UL
|
|
#define
|
_UART_ROUTELOC0_CSLOC_SHIFT
16
|
|
#define
|
_UART_ROUTELOC0_MASK
0x07070707UL
|
|
#define
|
_UART_ROUTELOC0_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_ROUTELOC0_RXLOC_DEFAULT
0x00000000UL
|
|
#define
|
_UART_ROUTELOC0_RXLOC_LOC0
0x00000000UL
|
|
#define
|
_UART_ROUTELOC0_RXLOC_LOC1
0x00000001UL
|
|
#define
|
_UART_ROUTELOC0_RXLOC_LOC2
0x00000002UL
|
|
#define
|
_UART_ROUTELOC0_RXLOC_LOC3
0x00000003UL
|
|
#define
|
_UART_ROUTELOC0_RXLOC_LOC4
0x00000004UL
|
|
#define
|
_UART_ROUTELOC0_RXLOC_LOC5
0x00000005UL
|
|
#define
|
_UART_ROUTELOC0_RXLOC_LOC6
0x00000006UL
|
|
#define
|
_UART_ROUTELOC0_RXLOC_MASK
0x7UL
|
|
#define
|
_UART_ROUTELOC0_RXLOC_SHIFT
0
|
|
#define
|
_UART_ROUTELOC0_TXLOC_DEFAULT
0x00000000UL
|
|
#define
|
_UART_ROUTELOC0_TXLOC_LOC0
0x00000000UL
|
|
#define
|
_UART_ROUTELOC0_TXLOC_LOC1
0x00000001UL
|
|
#define
|
_UART_ROUTELOC0_TXLOC_LOC2
0x00000002UL
|
|
#define
|
_UART_ROUTELOC0_TXLOC_LOC3
0x00000003UL
|
|
#define
|
_UART_ROUTELOC0_TXLOC_LOC4
0x00000004UL
|
|
#define
|
_UART_ROUTELOC0_TXLOC_LOC5
0x00000005UL
|
|
#define
|
_UART_ROUTELOC0_TXLOC_LOC6
0x00000006UL
|
|
#define
|
_UART_ROUTELOC0_TXLOC_MASK
0x700UL
|
|
#define
|
_UART_ROUTELOC0_TXLOC_SHIFT
8
|
|
#define
|
_UART_ROUTELOC1_CTSLOC_DEFAULT
0x00000000UL
|
|
#define
|
_UART_ROUTELOC1_CTSLOC_LOC0
0x00000000UL
|
|
#define
|
_UART_ROUTELOC1_CTSLOC_LOC1
0x00000001UL
|
|
#define
|
_UART_ROUTELOC1_CTSLOC_LOC2
0x00000002UL
|
|
#define
|
_UART_ROUTELOC1_CTSLOC_LOC3
0x00000003UL
|
|
#define
|
_UART_ROUTELOC1_CTSLOC_LOC4
0x00000004UL
|
|
#define
|
_UART_ROUTELOC1_CTSLOC_LOC5
0x00000005UL
|
|
#define
|
_UART_ROUTELOC1_CTSLOC_LOC6
0x00000006UL
|
|
#define
|
_UART_ROUTELOC1_CTSLOC_MASK
0x7UL
|
|
#define
|
_UART_ROUTELOC1_CTSLOC_SHIFT
0
|
|
#define
|
_UART_ROUTELOC1_MASK
0x00000707UL
|
|
#define
|
_UART_ROUTELOC1_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_ROUTELOC1_RTSLOC_DEFAULT
0x00000000UL
|
|
#define
|
_UART_ROUTELOC1_RTSLOC_LOC0
0x00000000UL
|
|
#define
|
_UART_ROUTELOC1_RTSLOC_LOC1
0x00000001UL
|
|
#define
|
_UART_ROUTELOC1_RTSLOC_LOC2
0x00000002UL
|
|
#define
|
_UART_ROUTELOC1_RTSLOC_LOC3
0x00000003UL
|
|
#define
|
_UART_ROUTELOC1_RTSLOC_LOC4
0x00000004UL
|
|
#define
|
_UART_ROUTELOC1_RTSLOC_LOC5
0x00000005UL
|
|
#define
|
_UART_ROUTELOC1_RTSLOC_LOC6
0x00000006UL
|
|
#define
|
_UART_ROUTELOC1_RTSLOC_MASK
0x700UL
|
|
#define
|
_UART_ROUTELOC1_RTSLOC_SHIFT
8
|
|
#define
|
_UART_ROUTEPEN_CLKPEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_ROUTEPEN_CLKPEN_MASK
0x8UL
|
|
#define
|
_UART_ROUTEPEN_CLKPEN_SHIFT
3
|
|
#define
|
_UART_ROUTEPEN_CSPEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_ROUTEPEN_CSPEN_MASK
0x4UL
|
|
#define
|
_UART_ROUTEPEN_CSPEN_SHIFT
2
|
|
#define
|
_UART_ROUTEPEN_CTSPEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_ROUTEPEN_CTSPEN_MASK
0x10UL
|
|
#define
|
_UART_ROUTEPEN_CTSPEN_SHIFT
4
|
|
#define
|
_UART_ROUTEPEN_MASK
0x0000003FUL
|
|
#define
|
_UART_ROUTEPEN_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_ROUTEPEN_RTSPEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_ROUTEPEN_RTSPEN_MASK
0x20UL
|
|
#define
|
_UART_ROUTEPEN_RTSPEN_SHIFT
5
|
|
#define
|
_UART_ROUTEPEN_RXPEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_ROUTEPEN_RXPEN_MASK
0x1UL
|
|
#define
|
_UART_ROUTEPEN_RXPEN_SHIFT
0
|
|
#define
|
_UART_ROUTEPEN_TXPEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_ROUTEPEN_TXPEN_MASK
0x2UL
|
|
#define
|
_UART_ROUTEPEN_TXPEN_SHIFT
1
|
|
#define
|
_UART_RXDATA_MASK
0x000000FFUL
|
|
#define
|
_UART_RXDATA_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_RXDATA_RXDATA_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDATA_RXDATA_MASK
0xFFUL
|
|
#define
|
_UART_RXDATA_RXDATA_SHIFT
0
|
|
#define
|
_UART_RXDATAX_FERR_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDATAX_FERR_MASK
0x8000UL
|
|
#define
|
_UART_RXDATAX_FERR_SHIFT
15
|
|
#define
|
_UART_RXDATAX_MASK
0x0000C1FFUL
|
|
#define
|
_UART_RXDATAX_PERR_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDATAX_PERR_MASK
0x4000UL
|
|
#define
|
_UART_RXDATAX_PERR_SHIFT
14
|
|
#define
|
_UART_RXDATAX_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_RXDATAX_RXDATA_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDATAX_RXDATA_MASK
0x1FFUL
|
|
#define
|
_UART_RXDATAX_RXDATA_SHIFT
0
|
|
#define
|
_UART_RXDATAXP_FERRP_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDATAXP_FERRP_MASK
0x8000UL
|
|
#define
|
_UART_RXDATAXP_FERRP_SHIFT
15
|
|
#define
|
_UART_RXDATAXP_MASK
0x0000C1FFUL
|
|
#define
|
_UART_RXDATAXP_PERRP_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDATAXP_PERRP_MASK
0x4000UL
|
|
#define
|
_UART_RXDATAXP_PERRP_SHIFT
14
|
|
#define
|
_UART_RXDATAXP_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_RXDATAXP_RXDATAP_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDATAXP_RXDATAP_MASK
0x1FFUL
|
|
#define
|
_UART_RXDATAXP_RXDATAP_SHIFT
0
|
|
#define
|
_UART_RXDOUBLE_MASK
0x0000FFFFUL
|
|
#define
|
_UART_RXDOUBLE_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_RXDOUBLE_RXDATA0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLE_RXDATA0_MASK
0xFFUL
|
|
#define
|
_UART_RXDOUBLE_RXDATA0_SHIFT
0
|
|
#define
|
_UART_RXDOUBLE_RXDATA1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLE_RXDATA1_MASK
0xFF00UL
|
|
#define
|
_UART_RXDOUBLE_RXDATA1_SHIFT
8
|
|
#define
|
_UART_RXDOUBLEX_FERR0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEX_FERR0_MASK
0x8000UL
|
|
#define
|
_UART_RXDOUBLEX_FERR0_SHIFT
15
|
|
#define
|
_UART_RXDOUBLEX_FERR1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEX_FERR1_MASK
0x80000000UL
|
|
#define
|
_UART_RXDOUBLEX_FERR1_SHIFT
31
|
|
#define
|
_UART_RXDOUBLEX_MASK
0xC1FFC1FFUL
|
|
#define
|
_UART_RXDOUBLEX_PERR0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEX_PERR0_MASK
0x4000UL
|
|
#define
|
_UART_RXDOUBLEX_PERR0_SHIFT
14
|
|
#define
|
_UART_RXDOUBLEX_PERR1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEX_PERR1_MASK
0x40000000UL
|
|
#define
|
_UART_RXDOUBLEX_PERR1_SHIFT
30
|
|
#define
|
_UART_RXDOUBLEX_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEX_RXDATA0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEX_RXDATA0_MASK
0x1FFUL
|
|
#define
|
_UART_RXDOUBLEX_RXDATA0_SHIFT
0
|
|
#define
|
_UART_RXDOUBLEX_RXDATA1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEX_RXDATA1_MASK
0x1FF0000UL
|
|
#define
|
_UART_RXDOUBLEX_RXDATA1_SHIFT
16
|
|
#define
|
_UART_RXDOUBLEXP_FERRP0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEXP_FERRP0_MASK
0x8000UL
|
|
#define
|
_UART_RXDOUBLEXP_FERRP0_SHIFT
15
|
|
#define
|
_UART_RXDOUBLEXP_FERRP1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEXP_FERRP1_MASK
0x80000000UL
|
|
#define
|
_UART_RXDOUBLEXP_FERRP1_SHIFT
31
|
|
#define
|
_UART_RXDOUBLEXP_MASK
0xC1FFC1FFUL
|
|
#define
|
_UART_RXDOUBLEXP_PERRP0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEXP_PERRP0_MASK
0x4000UL
|
|
#define
|
_UART_RXDOUBLEXP_PERRP0_SHIFT
14
|
|
#define
|
_UART_RXDOUBLEXP_PERRP1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEXP_PERRP1_MASK
0x40000000UL
|
|
#define
|
_UART_RXDOUBLEXP_PERRP1_SHIFT
30
|
|
#define
|
_UART_RXDOUBLEXP_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEXP_RXDATAP0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEXP_RXDATAP0_MASK
0x1FFUL
|
|
#define
|
_UART_RXDOUBLEXP_RXDATAP0_SHIFT
0
|
|
#define
|
_UART_RXDOUBLEXP_RXDATAP1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_RXDOUBLEXP_RXDATAP1_MASK
0x1FF0000UL
|
|
#define
|
_UART_RXDOUBLEXP_RXDATAP1_SHIFT
16
|
|
#define
|
_UART_STATUS_MASK
0x00037FFFUL
|
|
#define
|
_UART_STATUS_MASTER_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_MASTER_MASK
0x4UL
|
|
#define
|
_UART_STATUS_MASTER_SHIFT
2
|
|
#define
|
_UART_STATUS_RESETVALUE
0x00002040UL
|
|
#define
|
_UART_STATUS_RXBLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_RXBLOCK_MASK
0x8UL
|
|
#define
|
_UART_STATUS_RXBLOCK_SHIFT
3
|
|
#define
|
_UART_STATUS_RXDATAV_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_RXDATAV_MASK
0x80UL
|
|
#define
|
_UART_STATUS_RXDATAV_SHIFT
7
|
|
#define
|
_UART_STATUS_RXDATAVRIGHT_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_RXDATAVRIGHT_MASK
0x800UL
|
|
#define
|
_UART_STATUS_RXDATAVRIGHT_SHIFT
11
|
|
#define
|
_UART_STATUS_RXENS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_RXENS_MASK
0x1UL
|
|
#define
|
_UART_STATUS_RXENS_SHIFT
0
|
|
#define
|
_UART_STATUS_RXFULL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_RXFULL_MASK
0x100UL
|
|
#define
|
_UART_STATUS_RXFULL_SHIFT
8
|
|
#define
|
_UART_STATUS_RXFULLRIGHT_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_RXFULLRIGHT_MASK
0x1000UL
|
|
#define
|
_UART_STATUS_RXFULLRIGHT_SHIFT
12
|
|
#define
|
_UART_STATUS_TIMERRESTARTED_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_TIMERRESTARTED_MASK
0x4000UL
|
|
#define
|
_UART_STATUS_TIMERRESTARTED_SHIFT
14
|
|
#define
|
_UART_STATUS_TXBDRIGHT_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_TXBDRIGHT_MASK
0x200UL
|
|
#define
|
_UART_STATUS_TXBDRIGHT_SHIFT
9
|
|
#define
|
_UART_STATUS_TXBL_DEFAULT
0x00000001UL
|
|
#define
|
_UART_STATUS_TXBL_MASK
0x40UL
|
|
#define
|
_UART_STATUS_TXBL_SHIFT
6
|
|
#define
|
_UART_STATUS_TXBSRIGHT_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_TXBSRIGHT_MASK
0x400UL
|
|
#define
|
_UART_STATUS_TXBSRIGHT_SHIFT
10
|
|
#define
|
_UART_STATUS_TXBUFCNT_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_TXBUFCNT_MASK
0x30000UL
|
|
#define
|
_UART_STATUS_TXBUFCNT_SHIFT
16
|
|
#define
|
_UART_STATUS_TXC_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_TXC_MASK
0x20UL
|
|
#define
|
_UART_STATUS_TXC_SHIFT
5
|
|
#define
|
_UART_STATUS_TXENS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_TXENS_MASK
0x2UL
|
|
#define
|
_UART_STATUS_TXENS_SHIFT
1
|
|
#define
|
_UART_STATUS_TXIDLE_DEFAULT
0x00000001UL
|
|
#define
|
_UART_STATUS_TXIDLE_MASK
0x2000UL
|
|
#define
|
_UART_STATUS_TXIDLE_SHIFT
13
|
|
#define
|
_UART_STATUS_TXTRI_DEFAULT
0x00000000UL
|
|
#define
|
_UART_STATUS_TXTRI_MASK
0x10UL
|
|
#define
|
_UART_STATUS_TXTRI_SHIFT
4
|
|
#define
|
_UART_TIMECMP0_MASK
0x017700FFUL
|
|
#define
|
_UART_TIMECMP0_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_TIMECMP0_RESTARTEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMECMP0_RESTARTEN_MASK
0x1000000UL
|
|
#define
|
_UART_TIMECMP0_RESTARTEN_SHIFT
24
|
|
#define
|
_UART_TIMECMP0_TCMPVAL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMECMP0_TCMPVAL_MASK
0xFFUL
|
|
#define
|
_UART_TIMECMP0_TCMPVAL_SHIFT
0
|
|
#define
|
_UART_TIMECMP0_TSTART_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMECMP0_TSTART_DISABLE
0x00000000UL
|
|
#define
|
_UART_TIMECMP0_TSTART_MASK
0x70000UL
|
|
#define
|
_UART_TIMECMP0_TSTART_RXACT
0x00000003UL
|
|
#define
|
_UART_TIMECMP0_TSTART_RXEOF
0x00000004UL
|
|
#define
|
_UART_TIMECMP0_TSTART_SHIFT
16
|
|
#define
|
_UART_TIMECMP0_TSTART_TXC
0x00000002UL
|
|
#define
|
_UART_TIMECMP0_TSTART_TXEOF
0x00000001UL
|
|
#define
|
_UART_TIMECMP0_TSTOP_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMECMP0_TSTOP_MASK
0x700000UL
|
|
#define
|
_UART_TIMECMP0_TSTOP_RXACT
0x00000002UL
|
|
#define
|
_UART_TIMECMP0_TSTOP_RXACTN
0x00000003UL
|
|
#define
|
_UART_TIMECMP0_TSTOP_SHIFT
20
|
|
#define
|
_UART_TIMECMP0_TSTOP_TCMP0
0x00000000UL
|
|
#define
|
_UART_TIMECMP0_TSTOP_TXST
0x00000001UL
|
|
#define
|
_UART_TIMECMP1_MASK
0x017700FFUL
|
|
#define
|
_UART_TIMECMP1_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_TIMECMP1_RESTARTEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMECMP1_RESTARTEN_MASK
0x1000000UL
|
|
#define
|
_UART_TIMECMP1_RESTARTEN_SHIFT
24
|
|
#define
|
_UART_TIMECMP1_TCMPVAL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMECMP1_TCMPVAL_MASK
0xFFUL
|
|
#define
|
_UART_TIMECMP1_TCMPVAL_SHIFT
0
|
|
#define
|
_UART_TIMECMP1_TSTART_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMECMP1_TSTART_DISABLE
0x00000000UL
|
|
#define
|
_UART_TIMECMP1_TSTART_MASK
0x70000UL
|
|
#define
|
_UART_TIMECMP1_TSTART_RXACT
0x00000003UL
|
|
#define
|
_UART_TIMECMP1_TSTART_RXEOF
0x00000004UL
|
|
#define
|
_UART_TIMECMP1_TSTART_SHIFT
16
|
|
#define
|
_UART_TIMECMP1_TSTART_TXC
0x00000002UL
|
|
#define
|
_UART_TIMECMP1_TSTART_TXEOF
0x00000001UL
|
|
#define
|
_UART_TIMECMP1_TSTOP_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMECMP1_TSTOP_MASK
0x700000UL
|
|
#define
|
_UART_TIMECMP1_TSTOP_RXACT
0x00000002UL
|
|
#define
|
_UART_TIMECMP1_TSTOP_RXACTN
0x00000003UL
|
|
#define
|
_UART_TIMECMP1_TSTOP_SHIFT
20
|
|
#define
|
_UART_TIMECMP1_TSTOP_TCMP1
0x00000000UL
|
|
#define
|
_UART_TIMECMP1_TSTOP_TXST
0x00000001UL
|
|
#define
|
_UART_TIMECMP2_MASK
0x017700FFUL
|
|
#define
|
_UART_TIMECMP2_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_TIMECMP2_RESTARTEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMECMP2_RESTARTEN_MASK
0x1000000UL
|
|
#define
|
_UART_TIMECMP2_RESTARTEN_SHIFT
24
|
|
#define
|
_UART_TIMECMP2_TCMPVAL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMECMP2_TCMPVAL_MASK
0xFFUL
|
|
#define
|
_UART_TIMECMP2_TCMPVAL_SHIFT
0
|
|
#define
|
_UART_TIMECMP2_TSTART_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMECMP2_TSTART_DISABLE
0x00000000UL
|
|
#define
|
_UART_TIMECMP2_TSTART_MASK
0x70000UL
|
|
#define
|
_UART_TIMECMP2_TSTART_RXACT
0x00000003UL
|
|
#define
|
_UART_TIMECMP2_TSTART_RXEOF
0x00000004UL
|
|
#define
|
_UART_TIMECMP2_TSTART_SHIFT
16
|
|
#define
|
_UART_TIMECMP2_TSTART_TXC
0x00000002UL
|
|
#define
|
_UART_TIMECMP2_TSTART_TXEOF
0x00000001UL
|
|
#define
|
_UART_TIMECMP2_TSTOP_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMECMP2_TSTOP_MASK
0x700000UL
|
|
#define
|
_UART_TIMECMP2_TSTOP_RXACT
0x00000002UL
|
|
#define
|
_UART_TIMECMP2_TSTOP_RXACTN
0x00000003UL
|
|
#define
|
_UART_TIMECMP2_TSTOP_SHIFT
20
|
|
#define
|
_UART_TIMECMP2_TSTOP_TCMP2
0x00000000UL
|
|
#define
|
_UART_TIMECMP2_TSTOP_TXST
0x00000001UL
|
|
#define
|
_UART_TIMING_CSHOLD_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMING_CSHOLD_MASK
0x70000000UL
|
|
#define
|
_UART_TIMING_CSHOLD_ONE
0x00000001UL
|
|
#define
|
_UART_TIMING_CSHOLD_SEVEN
0x00000004UL
|
|
#define
|
_UART_TIMING_CSHOLD_SHIFT
28
|
|
#define
|
_UART_TIMING_CSHOLD_TCMP0
0x00000005UL
|
|
#define
|
_UART_TIMING_CSHOLD_TCMP1
0x00000006UL
|
|
#define
|
_UART_TIMING_CSHOLD_TCMP2
0x00000007UL
|
|
#define
|
_UART_TIMING_CSHOLD_THREE
0x00000003UL
|
|
#define
|
_UART_TIMING_CSHOLD_TWO
0x00000002UL
|
|
#define
|
_UART_TIMING_CSHOLD_ZERO
0x00000000UL
|
|
#define
|
_UART_TIMING_CSSETUP_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMING_CSSETUP_MASK
0x700000UL
|
|
#define
|
_UART_TIMING_CSSETUP_ONE
0x00000001UL
|
|
#define
|
_UART_TIMING_CSSETUP_SEVEN
0x00000004UL
|
|
#define
|
_UART_TIMING_CSSETUP_SHIFT
20
|
|
#define
|
_UART_TIMING_CSSETUP_TCMP0
0x00000005UL
|
|
#define
|
_UART_TIMING_CSSETUP_TCMP1
0x00000006UL
|
|
#define
|
_UART_TIMING_CSSETUP_TCMP2
0x00000007UL
|
|
#define
|
_UART_TIMING_CSSETUP_THREE
0x00000003UL
|
|
#define
|
_UART_TIMING_CSSETUP_TWO
0x00000002UL
|
|
#define
|
_UART_TIMING_CSSETUP_ZERO
0x00000000UL
|
|
#define
|
_UART_TIMING_ICS_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMING_ICS_MASK
0x7000000UL
|
|
#define
|
_UART_TIMING_ICS_ONE
0x00000001UL
|
|
#define
|
_UART_TIMING_ICS_SEVEN
0x00000004UL
|
|
#define
|
_UART_TIMING_ICS_SHIFT
24
|
|
#define
|
_UART_TIMING_ICS_TCMP0
0x00000005UL
|
|
#define
|
_UART_TIMING_ICS_TCMP1
0x00000006UL
|
|
#define
|
_UART_TIMING_ICS_TCMP2
0x00000007UL
|
|
#define
|
_UART_TIMING_ICS_THREE
0x00000003UL
|
|
#define
|
_UART_TIMING_ICS_TWO
0x00000002UL
|
|
#define
|
_UART_TIMING_ICS_ZERO
0x00000000UL
|
|
#define
|
_UART_TIMING_MASK
0x77770000UL
|
|
#define
|
_UART_TIMING_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_TIMING_TXDELAY_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TIMING_TXDELAY_DISABLE
0x00000000UL
|
|
#define
|
_UART_TIMING_TXDELAY_MASK
0x70000UL
|
|
#define
|
_UART_TIMING_TXDELAY_ONE
0x00000001UL
|
|
#define
|
_UART_TIMING_TXDELAY_SEVEN
0x00000004UL
|
|
#define
|
_UART_TIMING_TXDELAY_SHIFT
16
|
|
#define
|
_UART_TIMING_TXDELAY_TCMP0
0x00000005UL
|
|
#define
|
_UART_TIMING_TXDELAY_TCMP1
0x00000006UL
|
|
#define
|
_UART_TIMING_TXDELAY_TCMP2
0x00000007UL
|
|
#define
|
_UART_TIMING_TXDELAY_THREE
0x00000003UL
|
|
#define
|
_UART_TIMING_TXDELAY_TWO
0x00000002UL
|
|
#define
|
_UART_TRIGCTRL_AUTOTXTEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TRIGCTRL_AUTOTXTEN_MASK
0x40UL
|
|
#define
|
_UART_TRIGCTRL_AUTOTXTEN_SHIFT
6
|
|
#define
|
_UART_TRIGCTRL_MASK
0x00071FF0UL
|
|
#define
|
_UART_TRIGCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_TRIGCTRL_RXATX0EN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TRIGCTRL_RXATX0EN_MASK
0x400UL
|
|
#define
|
_UART_TRIGCTRL_RXATX0EN_SHIFT
10
|
|
#define
|
_UART_TRIGCTRL_RXATX1EN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TRIGCTRL_RXATX1EN_MASK
0x800UL
|
|
#define
|
_UART_TRIGCTRL_RXATX1EN_SHIFT
11
|
|
#define
|
_UART_TRIGCTRL_RXATX2EN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TRIGCTRL_RXATX2EN_MASK
0x1000UL
|
|
#define
|
_UART_TRIGCTRL_RXATX2EN_SHIFT
12
|
|
#define
|
_UART_TRIGCTRL_RXTEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TRIGCTRL_RXTEN_MASK
0x10UL
|
|
#define
|
_UART_TRIGCTRL_RXTEN_SHIFT
4
|
|
#define
|
_UART_TRIGCTRL_TSEL_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TRIGCTRL_TSEL_MASK
0x70000UL
|
|
#define
|
_UART_TRIGCTRL_TSEL_PRSCH0
0x00000000UL
|
|
#define
|
_UART_TRIGCTRL_TSEL_PRSCH1
0x00000001UL
|
|
#define
|
_UART_TRIGCTRL_TSEL_PRSCH2
0x00000002UL
|
|
#define
|
_UART_TRIGCTRL_TSEL_PRSCH3
0x00000003UL
|
|
#define
|
_UART_TRIGCTRL_TSEL_PRSCH4
0x00000004UL
|
|
#define
|
_UART_TRIGCTRL_TSEL_PRSCH5
0x00000005UL
|
|
#define
|
_UART_TRIGCTRL_TSEL_PRSCH6
0x00000006UL
|
|
#define
|
_UART_TRIGCTRL_TSEL_PRSCH7
0x00000007UL
|
|
#define
|
_UART_TRIGCTRL_TSEL_SHIFT
16
|
|
#define
|
_UART_TRIGCTRL_TXARX0EN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TRIGCTRL_TXARX0EN_MASK
0x80UL
|
|
#define
|
_UART_TRIGCTRL_TXARX0EN_SHIFT
7
|
|
#define
|
_UART_TRIGCTRL_TXARX1EN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TRIGCTRL_TXARX1EN_MASK
0x100UL
|
|
#define
|
_UART_TRIGCTRL_TXARX1EN_SHIFT
8
|
|
#define
|
_UART_TRIGCTRL_TXARX2EN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TRIGCTRL_TXARX2EN_MASK
0x200UL
|
|
#define
|
_UART_TRIGCTRL_TXARX2EN_SHIFT
9
|
|
#define
|
_UART_TRIGCTRL_TXTEN_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TRIGCTRL_TXTEN_MASK
0x20UL
|
|
#define
|
_UART_TRIGCTRL_TXTEN_SHIFT
5
|
|
#define
|
_UART_TXDATA_MASK
0x000000FFUL
|
|
#define
|
_UART_TXDATA_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_TXDATA_TXDATA_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDATA_TXDATA_MASK
0xFFUL
|
|
#define
|
_UART_TXDATA_TXDATA_SHIFT
0
|
|
#define
|
_UART_TXDATAX_MASK
0x0000F9FFUL
|
|
#define
|
_UART_TXDATAX_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_TXDATAX_RXENAT_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDATAX_RXENAT_MASK
0x8000UL
|
|
#define
|
_UART_TXDATAX_RXENAT_SHIFT
15
|
|
#define
|
_UART_TXDATAX_TXBREAK_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDATAX_TXBREAK_MASK
0x2000UL
|
|
#define
|
_UART_TXDATAX_TXBREAK_SHIFT
13
|
|
#define
|
_UART_TXDATAX_TXDATAX_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDATAX_TXDATAX_MASK
0x1FFUL
|
|
#define
|
_UART_TXDATAX_TXDATAX_SHIFT
0
|
|
#define
|
_UART_TXDATAX_TXDISAT_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDATAX_TXDISAT_MASK
0x4000UL
|
|
#define
|
_UART_TXDATAX_TXDISAT_SHIFT
14
|
|
#define
|
_UART_TXDATAX_TXTRIAT_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDATAX_TXTRIAT_MASK
0x1000UL
|
|
#define
|
_UART_TXDATAX_TXTRIAT_SHIFT
12
|
|
#define
|
_UART_TXDATAX_UBRXAT_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDATAX_UBRXAT_MASK
0x800UL
|
|
#define
|
_UART_TXDATAX_UBRXAT_SHIFT
11
|
|
#define
|
_UART_TXDOUBLE_MASK
0x0000FFFFUL
|
|
#define
|
_UART_TXDOUBLE_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_TXDOUBLE_TXDATA0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLE_TXDATA0_MASK
0xFFUL
|
|
#define
|
_UART_TXDOUBLE_TXDATA0_SHIFT
0
|
|
#define
|
_UART_TXDOUBLE_TXDATA1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLE_TXDATA1_MASK
0xFF00UL
|
|
#define
|
_UART_TXDOUBLE_TXDATA1_SHIFT
8
|
|
#define
|
_UART_TXDOUBLEX_MASK
0xF9FFF9FFUL
|
|
#define
|
_UART_TXDOUBLEX_RESETVALUE
0x00000000UL
|
|
#define
|
_UART_TXDOUBLEX_RXENAT0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLEX_RXENAT0_MASK
0x8000UL
|
|
#define
|
_UART_TXDOUBLEX_RXENAT0_SHIFT
15
|
|
#define
|
_UART_TXDOUBLEX_RXENAT1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLEX_RXENAT1_MASK
0x80000000UL
|
|
#define
|
_UART_TXDOUBLEX_RXENAT1_SHIFT
31
|
|
#define
|
_UART_TXDOUBLEX_TXBREAK0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLEX_TXBREAK0_MASK
0x2000UL
|
|
#define
|
_UART_TXDOUBLEX_TXBREAK0_SHIFT
13
|
|
#define
|
_UART_TXDOUBLEX_TXBREAK1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLEX_TXBREAK1_MASK
0x20000000UL
|
|
#define
|
_UART_TXDOUBLEX_TXBREAK1_SHIFT
29
|
|
#define
|
_UART_TXDOUBLEX_TXDATA0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLEX_TXDATA0_MASK
0x1FFUL
|
|
#define
|
_UART_TXDOUBLEX_TXDATA0_SHIFT
0
|
|
#define
|
_UART_TXDOUBLEX_TXDATA1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLEX_TXDATA1_MASK
0x1FF0000UL
|
|
#define
|
_UART_TXDOUBLEX_TXDATA1_SHIFT
16
|
|
#define
|
_UART_TXDOUBLEX_TXDISAT0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLEX_TXDISAT0_MASK
0x4000UL
|
|
#define
|
_UART_TXDOUBLEX_TXDISAT0_SHIFT
14
|
|
#define
|
_UART_TXDOUBLEX_TXDISAT1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLEX_TXDISAT1_MASK
0x40000000UL
|
|
#define
|
_UART_TXDOUBLEX_TXDISAT1_SHIFT
30
|
|
#define
|
_UART_TXDOUBLEX_TXTRIAT0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLEX_TXTRIAT0_MASK
0x1000UL
|
|
#define
|
_UART_TXDOUBLEX_TXTRIAT0_SHIFT
12
|
|
#define
|
_UART_TXDOUBLEX_TXTRIAT1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLEX_TXTRIAT1_MASK
0x10000000UL
|
|
#define
|
_UART_TXDOUBLEX_TXTRIAT1_SHIFT
28
|
|
#define
|
_UART_TXDOUBLEX_UBRXAT0_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLEX_UBRXAT0_MASK
0x800UL
|
|
#define
|
_UART_TXDOUBLEX_UBRXAT0_SHIFT
11
|
|
#define
|
_UART_TXDOUBLEX_UBRXAT1_DEFAULT
0x00000000UL
|
|
#define
|
_UART_TXDOUBLEX_UBRXAT1_MASK
0x8000000UL
|
|
#define
|
_UART_TXDOUBLEX_UBRXAT1_SHIFT
27
|
|
#define
|
UART_CLKDIV_AUTOBAUDEN
(0x1UL << 31)
|
|
#define
|
UART_CLKDIV_AUTOBAUDEN_DEFAULT
(
_UART_CLKDIV_AUTOBAUDEN_DEFAULT
<< 31)
|
|
#define
|
UART_CLKDIV_DIV_DEFAULT
(
_UART_CLKDIV_DIV_DEFAULT
<< 3)
|
|
#define
|
UART_CMD_CLEARRX
(0x1UL << 11)
|
|
#define
|
UART_CMD_CLEARRX_DEFAULT
(
_UART_CMD_CLEARRX_DEFAULT
<< 11)
|
|
#define
|
UART_CMD_CLEARTX
(0x1UL << 10)
|
|
#define
|
UART_CMD_CLEARTX_DEFAULT
(
_UART_CMD_CLEARTX_DEFAULT
<< 10)
|
|
#define
|
UART_CMD_MASTERDIS
(0x1UL << 5)
|
|
#define
|
UART_CMD_MASTERDIS_DEFAULT
(
_UART_CMD_MASTERDIS_DEFAULT
<< 5)
|
|
#define
|
UART_CMD_MASTEREN
(0x1UL << 4)
|
|
#define
|
UART_CMD_MASTEREN_DEFAULT
(
_UART_CMD_MASTEREN_DEFAULT
<< 4)
|
|
#define
|
UART_CMD_RXBLOCKDIS
(0x1UL << 7)
|
|
#define
|
UART_CMD_RXBLOCKDIS_DEFAULT
(
_UART_CMD_RXBLOCKDIS_DEFAULT
<< 7)
|
|
#define
|
UART_CMD_RXBLOCKEN
(0x1UL << 6)
|
|
#define
|
UART_CMD_RXBLOCKEN_DEFAULT
(
_UART_CMD_RXBLOCKEN_DEFAULT
<< 6)
|
|
#define
|
UART_CMD_RXDIS
(0x1UL << 1)
|
|
#define
|
UART_CMD_RXDIS_DEFAULT
(
_UART_CMD_RXDIS_DEFAULT
<< 1)
|
|
#define
|
UART_CMD_RXEN
(0x1UL << 0)
|
|
#define
|
UART_CMD_RXEN_DEFAULT
(
_UART_CMD_RXEN_DEFAULT
<< 0)
|
|
#define
|
UART_CMD_TXDIS
(0x1UL << 3)
|
|
#define
|
UART_CMD_TXDIS_DEFAULT
(
_UART_CMD_TXDIS_DEFAULT
<< 3)
|
|
#define
|
UART_CMD_TXEN
(0x1UL << 2)
|
|
#define
|
UART_CMD_TXEN_DEFAULT
(
_UART_CMD_TXEN_DEFAULT
<< 2)
|
|
#define
|
UART_CMD_TXTRIDIS
(0x1UL << 9)
|
|
#define
|
UART_CMD_TXTRIDIS_DEFAULT
(
_UART_CMD_TXTRIDIS_DEFAULT
<< 9)
|
|
#define
|
UART_CMD_TXTRIEN
(0x1UL << 8)
|
|
#define
|
UART_CMD_TXTRIEN_DEFAULT
(
_UART_CMD_TXTRIEN_DEFAULT
<< 8)
|
|
#define
|
UART_CTRL_AUTOCS
(0x1UL << 16)
|
|
#define
|
UART_CTRL_AUTOCS_DEFAULT
(
_UART_CTRL_AUTOCS_DEFAULT
<< 16)
|
|
#define
|
UART_CTRL_AUTOTRI
(0x1UL << 17)
|
|
#define
|
UART_CTRL_AUTOTRI_DEFAULT
(
_UART_CTRL_AUTOTRI_DEFAULT
<< 17)
|
|
#define
|
UART_CTRL_AUTOTX
(0x1UL << 29)
|
|
#define
|
UART_CTRL_AUTOTX_DEFAULT
(
_UART_CTRL_AUTOTX_DEFAULT
<< 29)
|
|
#define
|
UART_CTRL_BIT8DV
(0x1UL << 21)
|
|
#define
|
UART_CTRL_BIT8DV_DEFAULT
(
_UART_CTRL_BIT8DV_DEFAULT
<< 21)
|
|
#define
|
UART_CTRL_BYTESWAP
(0x1UL << 28)
|
|
#define
|
UART_CTRL_BYTESWAP_DEFAULT
(
_UART_CTRL_BYTESWAP_DEFAULT
<< 28)
|
|
#define
|
UART_CTRL_CCEN
(0x1UL << 2)
|
|
#define
|
UART_CTRL_CCEN_DEFAULT
(
_UART_CTRL_CCEN_DEFAULT
<< 2)
|
|
#define
|
UART_CTRL_CLKPHA
(0x1UL << 9)
|
|
#define
|
UART_CTRL_CLKPHA_DEFAULT
(
_UART_CTRL_CLKPHA_DEFAULT
<< 9)
|
|
#define
|
UART_CTRL_CLKPHA_SAMPLELEADING
(
_UART_CTRL_CLKPHA_SAMPLELEADING
<< 9)
|
|
#define
|
UART_CTRL_CLKPHA_SAMPLETRAILING
(
_UART_CTRL_CLKPHA_SAMPLETRAILING
<< 9)
|
|
#define
|
UART_CTRL_CLKPOL
(0x1UL << 8)
|
|
#define
|
UART_CTRL_CLKPOL_DEFAULT
(
_UART_CTRL_CLKPOL_DEFAULT
<< 8)
|
|
#define
|
UART_CTRL_CLKPOL_IDLEHIGH
(
_UART_CTRL_CLKPOL_IDLEHIGH
<< 8)
|
|
#define
|
UART_CTRL_CLKPOL_IDLELOW
(
_UART_CTRL_CLKPOL_IDLELOW
<< 8)
|
|
#define
|
UART_CTRL_CSINV
(0x1UL << 15)
|
|
#define
|
UART_CTRL_CSINV_DEFAULT
(
_UART_CTRL_CSINV_DEFAULT
<< 15)
|
|
#define
|
UART_CTRL_CSMA
(0x1UL << 11)
|
|
#define
|
UART_CTRL_CSMA_DEFAULT
(
_UART_CTRL_CSMA_DEFAULT
<< 11)
|
|
#define
|
UART_CTRL_CSMA_GOTOSLAVEMODE
(
_UART_CTRL_CSMA_GOTOSLAVEMODE
<< 11)
|
|
#define
|
UART_CTRL_CSMA_NOACTION
(
_UART_CTRL_CSMA_NOACTION
<< 11)
|
|
#define
|
UART_CTRL_ERRSDMA
(0x1UL << 22)
|
|
#define
|
UART_CTRL_ERRSDMA_DEFAULT
(
_UART_CTRL_ERRSDMA_DEFAULT
<< 22)
|
|
#define
|
UART_CTRL_ERRSRX
(0x1UL << 23)
|
|
#define
|
UART_CTRL_ERRSRX_DEFAULT
(
_UART_CTRL_ERRSRX_DEFAULT
<< 23)
|
|
#define
|
UART_CTRL_ERRSTX
(0x1UL << 24)
|
|
#define
|
UART_CTRL_ERRSTX_DEFAULT
(
_UART_CTRL_ERRSTX_DEFAULT
<< 24)
|
|
#define
|
UART_CTRL_LOOPBK
(0x1UL << 1)
|
|
#define
|
UART_CTRL_LOOPBK_DEFAULT
(
_UART_CTRL_LOOPBK_DEFAULT
<< 1)
|
|
#define
|
UART_CTRL_MPAB
(0x1UL << 4)
|
|
#define
|
UART_CTRL_MPAB_DEFAULT
(
_UART_CTRL_MPAB_DEFAULT
<< 4)
|
|
#define
|
UART_CTRL_MPM
(0x1UL << 3)
|
|
#define
|
UART_CTRL_MPM_DEFAULT
(
_UART_CTRL_MPM_DEFAULT
<< 3)
|
|
#define
|
UART_CTRL_MSBF
(0x1UL << 10)
|
|
#define
|
UART_CTRL_MSBF_DEFAULT
(
_UART_CTRL_MSBF_DEFAULT
<< 10)
|
|
#define
|
UART_CTRL_MVDIS
(0x1UL << 30)
|
|
#define
|
UART_CTRL_MVDIS_DEFAULT
(
_UART_CTRL_MVDIS_DEFAULT
<< 30)
|
|
#define
|
UART_CTRL_OVS_DEFAULT
(
_UART_CTRL_OVS_DEFAULT
<< 5)
|
|
#define
|
UART_CTRL_OVS_X16
(
_UART_CTRL_OVS_X16
<< 5)
|
|
#define
|
UART_CTRL_OVS_X4
(
_UART_CTRL_OVS_X4
<< 5)
|
|
#define
|
UART_CTRL_OVS_X6
(
_UART_CTRL_OVS_X6
<< 5)
|
|
#define
|
UART_CTRL_OVS_X8
(
_UART_CTRL_OVS_X8
<< 5)
|
|
#define
|
UART_CTRL_RXINV
(0x1UL << 13)
|
|
#define
|
UART_CTRL_RXINV_DEFAULT
(
_UART_CTRL_RXINV_DEFAULT
<< 13)
|
|
#define
|
UART_CTRL_SCMODE
(0x1UL << 18)
|
|
#define
|
UART_CTRL_SCMODE_DEFAULT
(
_UART_CTRL_SCMODE_DEFAULT
<< 18)
|
|
#define
|
UART_CTRL_SCRETRANS
(0x1UL << 19)
|
|
#define
|
UART_CTRL_SCRETRANS_DEFAULT
(
_UART_CTRL_SCRETRANS_DEFAULT
<< 19)
|
|
#define
|
UART_CTRL_SKIPPERRF
(0x1UL << 20)
|
|
#define
|
|