COREEMLIB
Detailed Description
Core interrupt handling API.
- Introduction
- Compile time configuration
- The macro API
- API reimplementation
- Interrupt vector tables
- Examples
- Porting from em_int
Introduction
The purpose of the CORE interrupt API is to provide simple and safe means to disable and enable interrupts to protect sections of code.
This is often referred to as "critical sections" and this module provide support for three types of critical sections, each with different interrupt blocking capabilities.
- CRITICAL section: Inside a critical sections all interrupts are disabled (except for fault handlers). The PRIMASK register is always used for interrupt disable/enable.
- ATOMIC section: This type of section is configurable and the default method is to use PRIMASK. With BASEPRI configuration, interrupts with priority equal to or lower than a given configurable level are disabled. The interrupt disable priority level is defined at compile time. The BASEPRI register is not available for all architectures.
- NVIC mask section: Disable NVIC (external interrupts) on an individual manner.
em_core also has an API for manipulating RAM based interrupt vector tables.
Compile time configuration
The following #defines are used to configure em_core:
// The interrupt priority level used inside ATOMIC sections. #define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 // Method used for interrupt disable/enable within ATOMIC sections. #define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK
If the default values does not support your needs, they can be overridden by supplying -D compiler flags on the compiler command line or by collecting all macro redefinitions in a file named emlib_config.h and then supplying -DEMLIB_USER_CONFIG on compiler command line.
- Note
- The default emlib configuration for ATOMIC section interrupt disable method is using PRIMASK, i.e. ATOMIC sections are implemented as CRITICAL sections.
- Due to architectural limitations Cortex-M0+ devices does not support ATOMIC type critical sections using the BASEPRI register. On M0+ devices ATOMIC section helper macros are available but they are implemented as CRITICAL sections using PRIMASK register.
The macro API
The primary em_core API is the macro API. The macro API will map to correct CORE functions according to the selected CORE_ATOMIC_METHOD and similar configurations (the full CORE API is of course also available). The most useful macros are:
CORE_DECLARE_IRQ_STATE
CORE_ENTER_ATOMIC()
CORE_EXIT_ATOMIC()
Used together to implement an ATOMIC section.
{ CORE_DECLARE_IRQ_STATE; // Storage for saving IRQ state prior // atomic section entry. CORE_ENTER_ATOMIC(); // Enter atomic section ... ... your code goes here ... ... CORE_EXIT_ATOMIC(); // Exit atomic section, IRQ state is restored }
CORE_ATOMIC_SECTION(yourcode)
A concatenation of all three macros above.
{ CORE_ATOMIC_SECTION( ... ... your code goes here ... ... ) }
CORE_DECLARE_IRQ_STATE
CORE_ENTER_CRITICAL()
CORE_EXIT_CRITICAL()
CORE_CRITICAL_SECTION(yourcode)
These macros implement CRITICAL sections in a similar fashion as described above for ATOMIC sections.
CORE_DECLARE_NVIC_STATE
CORE_ENTER_NVIC()
CORE_EXIT_NVIC()
CORE_NVIC_SECTION(yourcode)
These macros implement NVIC mask sections in a similar fashion as described above for ATOMIC sections. See
Examples
for an example.
Refer to Macros or Macro Definition Documentation below for a full list of macros.
API reimplementation
Most of the functions in the API are implemented as weak functions. This means that it is easy to reimplement them when special needs arise. Shown below is a reimplementation of CRITICAL sections suitable if FreeRTOS is used:
CORE_irqState_t CORE_EnterCritical(void) { vPortEnterCritical(); return 0; } void CORE_ExitCritical(CORE_irqState_t irqState) { (void)irqState; vPortExitCritical(); }
Also note that CORE_Enter/ExitCritical() are not implemented as inline functions. As a result, reimplementations will be possible even when original implementations reside inside a linked library.
Some RTOS'es must be notified on interrupt handler entry and exit. Macros CORE_INTERRUPT_ENTRY() and CORE_INTERRUPT_EXIT() are suitable placeholders for inserting such code. Insert these macros in all your interrupt handlers and then override the default macro implementations. Here is an example suitable if uC/OS is used:
// In emlib_config.h: #define CORE_INTERRUPT_ENTRY() OSIntEnter() #define CORE_INTERRUPT_EXIT() OSIntExit()
Interrupt vector tables
When using RAM based interrupt vector tables it is the users responsibility to allocate the table space correctly. The tables must be aligned as specified in the cpu reference manual.
CORE_InitNvicVectorTable()
Initialize a RAM based vector table by copying table entries from a source vector table to a target table. VTOR is set to the address of the target vector table.
CORE_GetNvicRamTableHandler()
CORE_SetNvicRamTableHandler()
Use these functions to get or set the interrupt handler for a specific IRQn. They both use the interrupt vector table defined by current VTOR register value.
Examples
Implement a NVIC critical section:
{ CORE_DECLARE_NVIC_ZEROMASK(mask); // A zero initialized NVIC disable mask // Set mask bits for IRQ's we wish to block in the NVIC critical section // In many cases you can create the disable mask once upon application // startup and use the mask globally throughout application lifetime. CORE_NvicMaskSetIRQ(LEUART0_IRQn, &mask); CORE_NvicMaskSetIRQ(VCMP_IRQn, &mask); // Enter NVIC critical section with the disable mask CORE_NVIC_SECTION(&mask, ... ... your code goes here ... ... ) }
Porting from em_int
Existing code using INT_Enable() and INT_Disable() must be ported to the em_core API. While em_int used a global counter to store the interrupt state, em_core uses a local variable. Any usage of INT_Disable() therefore needs to be replaced with a declaration of the interrupt state variable before entering the critical section.
Since the state variable is in the local scope, the critical section exit needs to occur within the scope of the variable. If multiple nested critical sections are used, each needs to have its own state variable in its own scope.
In many cases, completely disabling all interrupts using CRITICAL sections might be more heavy-handed than needed. When porting, consider whether other types of sections, like ATOMIC or NVIC mask, can be used to only disable a subset of the interrupts.
Replacing em_int calls with em_core function calls:
void func(void) { // INT_Disable(); CORE_DECLARE_IRQ_STATE; CORE_ENTER_ATOMIC(); . . . // INT_Enable(); CORE_EXIT_ATOMIC(); }
Data Structures |
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struct | CORE_nvicMask_t |
Typedefs |
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typedef uint32_t | CORE_irqState_t |
Functions |
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void | CORE_AtomicDisableIrq (void) |
Disable interrupts.
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void | CORE_AtomicEnableIrq (void) |
Enable interrupts.
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void | CORE_CriticalDisableIrq (void) |
Disable interrupts.
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void | CORE_CriticalEnableIrq (void) |
Enable interrupts.
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CORE_irqState_t | CORE_EnterAtomic (void) |
Enter an ATOMIC section.
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CORE_irqState_t | CORE_EnterCritical (void) |
Enter a CRITICAL section.
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void | CORE_EnterNvicMask ( CORE_nvicMask_t *nvicState, const CORE_nvicMask_t *disable) |
Enter a NVIC mask section.
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void | CORE_ExitAtomic ( CORE_irqState_t irqState) |
Exit an ATOMIC section.
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void | CORE_ExitCritical ( CORE_irqState_t irqState) |
Exit a CRITICAL section.
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void | CORE_GetNvicEnabledMask ( CORE_nvicMask_t *mask) |
Get current NVIC enable mask state.
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bool | CORE_GetNvicMaskDisableState (const CORE_nvicMask_t *mask) |
Get NVIC disable state for a given mask.
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void * | CORE_GetNvicRamTableHandler ( IRQn_Type irqN) |
Utility function to get the handler for a specific interrupt.
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bool | CORE_InIrqContext (void) |
Check if current cpu operation mode is handler mode.
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void | CORE_InitNvicVectorTable (uint32_t *sourceTable, uint32_t sourceSize, uint32_t *targetTable, uint32_t targetSize, void *defaultHandler, bool overwriteActive) |
Initialize an interrupt vector table by copying table entries from a source to a target table.
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bool | CORE_IrqIsBlocked ( IRQn_Type irqN) |
Check if a specific interrupt is disabled or blocked.
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bool | CORE_IrqIsDisabled (void) |
Check if interrupts are disabled.
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void | CORE_NvicDisableMask (const CORE_nvicMask_t *disable) |
Disable NVIC interrupts.
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void | CORE_NvicEnableMask (const CORE_nvicMask_t *enable) |
Set current NVIC interrupt enable mask.
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bool | CORE_NvicIRQDisabled ( IRQn_Type irqN) |
Check if a NVIC interrupt is disabled.
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void | CORE_NvicMaskClearIRQ ( IRQn_Type irqN, CORE_nvicMask_t *mask) |
Utility function to clear an IRQn bit in a NVIC enable/disable mask.
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void | CORE_NvicMaskSetIRQ ( IRQn_Type irqN, CORE_nvicMask_t *mask) |
Utility function to set an IRQn bit in a NVIC enable/disable mask.
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void | CORE_SetNvicRamTableHandler ( IRQn_Type irqN, void *handler) |
Utility function to set the handler for a specific interrupt.
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void | CORE_YieldAtomic (void) |
Brief interrupt enable/disable sequence to allow handling of pending interrupts.
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void | CORE_YieldCritical (void) |
Brief interrupt enable/disable sequence to allow handling of pending interrupts.
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void | CORE_YieldNvicMask (const CORE_nvicMask_t *enable) |
Brief NVIC interrupt enable/disable sequence to allow handling of pending interrupts.
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Macro Definition Documentation
#define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 |
The interrupt priority level disabled within ATOMIC regions. Interrupts with priority level equal to or lower than this definition will be disabled within ATOMIC regions.
Definition at line
269
of file
em_core.c
.
Referenced by CORE_AtomicDisableIrq() , CORE_EnterAtomic() , CORE_IrqIsDisabled() , and CORE_YieldAtomic() .
#define CORE_ATOMIC_IRQ_DISABLE | ( |
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) | CORE_AtomicDisableIrq () |
ATOMIC style interrupt disable.
Definition at line
120
of file
em_core.h
.
#define CORE_ATOMIC_IRQ_ENABLE | ( |
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) | CORE_AtomicEnableIrq () |
ATOMIC style interrupt enable.
Definition at line
123
of file
em_core.h
.
#define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK |
Specify which method to use when implementing ATOMIC sections. You can select between BASEPRI or PRIMASK method.
- Note
- On Cortex-M0+ devices only PRIMASK can be used.
Definition at line
276
of file
em_core.c
.
#define CORE_ATOMIC_METHOD_BASEPRI 1 |
Use BASEPRI register to disable interrupts in ATOMIC sections.
Definition at line
58
of file
em_core.h
.
#define CORE_ATOMIC_METHOD_PRIMASK 0 |
Use PRIMASK register to disable interrupts in ATOMIC sections.
Definition at line
55
of file
em_core.h
.
#define CORE_ATOMIC_SECTION | ( |
yourcode
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) |
Convenience macro for implementing an ATOMIC section.
Definition at line
126
of file
em_core.h
.
Referenced by DMADRV_TransferDone() , DMADRV_TransferRemainingCount() , GPIOINT_CallbackRegister() , RTCDRV_FreeTimer() , SPIDRV_GetTransferStatus() , UARTDRV_Transmit() , USBD_AbortAllTransfers() , USBD_Connect() , USBD_Disconnect() , USBD_StallEp() , USBD_UnStallEp() , USBH_Init() , USBH_PortReset() , USBH_PortResume() , USBH_PortSuspend() , USBH_Stop() , and USBH_WaitForDeviceConnectionB() .
#define CORE_CRITICAL_IRQ_DISABLE | ( |
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) | CORE_CriticalDisableIrq () |
CRITICAL style interrupt disable.
Definition at line
88
of file
em_core.h
.
#define CORE_CRITICAL_IRQ_ENABLE | ( |
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) | CORE_CriticalEnableIrq () |
CRITICAL style interrupt enable.
Definition at line
91
of file
em_core.h
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#define CORE_CRITICAL_SECTION | ( |
yourcode
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) |
Convenience macro for implementing a CRITICAL section.
Definition at line
94
of file
em_core.h
.
Referenced by CORE_EnterNvicMask() , CORE_GetNvicEnabledMask() , CORE_GetNvicMaskDisableState() , CORE_NvicDisableMask() , CORE_NvicEnableMask() , CORE_YieldNvicMask() , EMU_EnterEM2() , and EMU_EnterEM3() .
#define CORE_DECLARE_IRQ_STATE CORE_irqState_t irqState |
Allocate storage for PRIMASK or BASEPRI value for use by CORE_ENTER/EXIT_ATOMIC() and CORE_ENTER/EXIT_CRITICAL() macros.
Definition at line
85
of file
em_core.h
.
Referenced by CAPLESENSE_Init() , DMADRV_AllocateChannel() , DMADRV_DeInit() , DMADRV_FreeChannel() , DMADRV_Init() , RETARGET_ReadChar() , RTCDRV_AllocateTimer() , RTCDRV_IsRunning() , RTCDRV_StartTimer() , RTCDRV_StopTimer() , RTCDRV_TimeRemaining() , SLEEP_Sleep() , SPIDRV_AbortTransfer() , SPIDRV_Init() , SPIDRV_MTransferSingleItemB() , SPIDRV_SetBitrate() , SPIDRV_SetFramelength() , UARTDRV_Abort() , UARTDRV_InitLeuart() , UARTDRV_InitUart() , UDELAY_Calibrate() , USBD_AbortTransfer() , USBD_Init() , USBD_Read() , USBD_RemoteWakeup() , USBD_Write() , USBH_ControlMsg() , USBH_Read() , USBH_Write() , USBTIMER_Start() , and USBTIMER_Stop() .
#define CORE_DECLARE_NVIC_MASK | ( |
x
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) | CORE_nvicMask_t x |
Allocate storage for NVIC interrupt masks.
- Parameters
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[in] x
The storage variable name to use.
Definition at line
158
of file
em_core.h
.
#define CORE_DECLARE_NVIC_STATE CORE_nvicMask_t nvicState |
Allocate storage for NVIC interrupt masks for use by CORE_ENTER/EXIT_NVIC() macros.
Definition at line
153
of file
em_core.h
.
#define CORE_DECLARE_NVIC_ZEROMASK | ( |
x
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) | CORE_nvicMask_t x = { { 0 } } |
Allocate storage for and zero initialize NVIC interrupt mask.
- Parameters
-
[in] x
The storage variable name to use.
Definition at line
163
of file
em_core.h
.
#define CORE_DEFAULT_VECTOR_TABLE_ENTRIES ( EXT_IRQ_COUNT + 16) |
Number of entries in a default interrupt vector table.
Definition at line
64
of file
em_core.h
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#define CORE_ENTER_ATOMIC | ( |
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) | irqState = CORE_EnterAtomic () |
Enter ATOMIC section. Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.
Definition at line
138
of file
em_core.h
.
Referenced by CAPLESENSE_Init() , DMADRV_AllocateChannel() , DMADRV_DeInit() , DMADRV_FreeChannel() , DMADRV_Init() , RETARGET_ReadChar() , RTCDRV_AllocateTimer() , RTCDRV_IsRunning() , RTCDRV_StartTimer() , RTCDRV_StopTimer() , RTCDRV_TimeRemaining() , SPIDRV_AbortTransfer() , SPIDRV_Init() , SPIDRV_MTransferSingleItemB() , SPIDRV_SetBitrate() , SPIDRV_SetFramelength() , UARTDRV_Abort() , UARTDRV_InitLeuart() , UARTDRV_InitUart() , UDELAY_Calibrate() , USBD_AbortTransfer() , USBD_Init() , USBD_Read() , USBD_RemoteWakeup() , USBD_Write() , USBH_ControlMsg() , USBH_Read() , USBH_Write() , USBTIMER_Start() , and USBTIMER_Stop() .
#define CORE_ENTER_CRITICAL | ( |
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) | irqState = CORE_EnterCritical () |
Enter CRITICAL section. Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.
Definition at line
106
of file
em_core.h
.
Referenced by nvm3_lockBegin() , and SLEEP_Sleep() .
#define CORE_ENTER_NVIC | ( |
disable
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) | CORE_EnterNvicMask (&nvicState, disable) |
Enter NVIC mask section. Assumes that a CORE_DECLARE_NVIC_STATE exist in scope.
- Parameters
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[in] disable
Mask specifying which NVIC interrupts to disable within the section.
Definition at line
194
of file
em_core.h
.
#define CORE_EXIT_ATOMIC | ( |
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) | CORE_ExitAtomic (irqState) |
Exit ATOMIC section. Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.
Definition at line
142
of file
em_core.h
.
Referenced by CAPLESENSE_Init() , DMADRV_AllocateChannel() , DMADRV_DeInit() , DMADRV_FreeChannel() , DMADRV_Init() , RETARGET_ReadChar() , RTCDRV_AllocateTimer() , RTCDRV_IsRunning() , RTCDRV_StartTimer() , RTCDRV_StopTimer() , RTCDRV_TimeRemaining() , SPIDRV_AbortTransfer() , SPIDRV_Init() , SPIDRV_MTransferSingleItemB() , SPIDRV_SetBitrate() , SPIDRV_SetFramelength() , UARTDRV_Abort() , UARTDRV_InitLeuart() , UARTDRV_InitUart() , UDELAY_Calibrate() , USBD_AbortTransfer() , USBD_Init() , USBD_Read() , USBD_RemoteWakeup() , USBD_Write() , USBH_ControlMsg() , USBH_Read() , USBH_Write() , USBTIMER_Start() , and USBTIMER_Stop() .
#define CORE_EXIT_CRITICAL | ( |
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) | CORE_ExitCritical (irqState) |
Exit CRITICAL section. Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.
Definition at line
110
of file
em_core.h
.
Referenced by nvm3_lockEnd() , and SLEEP_Sleep() .
#define CORE_EXIT_NVIC | ( |
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) | CORE_NvicEnableMask (&nvicState) |
Exit NVIC mask section. Assumes that a CORE_DECLARE_NVIC_STATE exist in scope.
Definition at line
198
of file
em_core.h
.
#define CORE_IN_IRQ_CONTEXT | ( |
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) | CORE_InIrqContext () |
Check if inside an IRQ handler.
Definition at line
213
of file
em_core.h
.
Referenced by USBH_ControlMsgB() , USBH_PortReset() , USBH_PortResume() , USBH_PortSuspend() , USBH_ReadB() , and USBH_WriteB() .
#define CORE_INTERRUPT_ENTRY | ( |
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Placeholder for optional interrupt handler entry code. This might be needed when working with an RTOS.
Definition at line
285
of file
em_core.c
.
#define CORE_INTERRUPT_EXIT | ( |
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Placeholder for optional interrupt handler exit code. This might be needed when working with an RTOS.
Definition at line
291
of file
em_core.c
.
#define CORE_IRQ_DISABLED | ( |
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) | CORE_IrqIsDisabled () |
Check if IRQ is disabled.
Definition at line
210
of file
em_core.h
.
Referenced by USBH_ControlMsgB() , USBH_PortReset() , USBH_PortResume() , USBH_PortSuspend() , USBH_ReadB() , and USBH_WriteB() .
#define CORE_NVIC_DISABLE | ( |
mask
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) | CORE_NvicDisableMask (mask) |
NVIC mask style interrupt disable.
- Parameters
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[in] mask
Mask specifying which NVIC interrupts to disable.
Definition at line
168
of file
em_core.h
.
#define CORE_NVIC_ENABLE | ( |
mask
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) | CORE_NvicEnableMask (mask) |
NVIC mask style interrupt enable.
- Parameters
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[in] mask
Mask specifying which NVIC interrupts to enable.
Definition at line
173
of file
em_core.h
.
#define CORE_NVIC_REG_WORDS (( EXT_IRQ_COUNT + 31) / 32) |
Number of words in a NVIC mask set.
Definition at line
61
of file
em_core.h
.
#define CORE_NVIC_SECTION | ( |
mask,
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yourcode
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Convenience macro for implementing a NVIC mask section.
- Parameters
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[in] mask
Mask specifying which NVIC interrupts to disable within the section. [in] yourcode
The code for the section.
Definition at line
180
of file
em_core.h
.
#define CORE_YIELD_ATOMIC | ( |
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) | CORE_YieldAtomic () |
ATOMIC style yield.
Definition at line
145
of file
em_core.h
.
#define CORE_YIELD_CRITICAL | ( |
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) | CORE_YieldCritical () |
CRITICAL style yield.
Definition at line
113
of file
em_core.h
.
#define CORE_YIELD_NVIC | ( |
enable
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) | CORE_YieldNvicMask (enable) |
NVIC maks style yield.
- Parameters
-
[in] enable
Mask specifying which NVIC interrupts to briefly enable.
Definition at line
203
of file
em_core.h
.
Typedef Documentation
typedef uint32_t CORE_irqState_t |
Storage for PRIMASK or BASEPRI value.
Definition at line
220
of file
em_core.h
.
Function Documentation
SL_WEAK void CORE_AtomicDisableIrq | ( | void |
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) |
Disable interrupts.
Disable interrupts with priority lower or equal to CORE_ATOMIC_BASE_PRIORITY_LEVEL . Sets core BASEPRI register to CORE_ATOMIC_BASE_PRIORITY_LEVEL.
- Note
- If CORE_ATOMIC_METHOD is CORE_ATOMIC_METHOD_PRIMASK , this function is identical to CORE_CriticalDisableIrq() .
Definition at line
388
of file
em_core.c
.
References __NVIC_PRIO_BITS , and CORE_ATOMIC_BASE_PRIORITY_LEVEL .
SL_WEAK void CORE_AtomicEnableIrq | ( | void |
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) |
Enable interrupts.
Enable interrupts by setting core BASEPRI register to 0.
- Note
- If CORE_ATOMIC_METHOD is CORE_ATOMIC_METHOD_BASEPRI and PRIMASK is set (cpu is inside a CRITICAL section), interrupts will still be disabled after calling this function.
- If CORE_ATOMIC_METHOD is CORE_ATOMIC_METHOD_PRIMASK , this function is identical to CORE_CriticalEnableIrq() .
Definition at line
412
of file
em_core.c
.
SL_WEAK void CORE_CriticalDisableIrq | ( | void |
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) |
Disable interrupts.
Disable all interrupts by setting PRIMASK. (Fault exception handlers will still be enabled).
Definition at line
311
of file
em_core.c
.
SL_WEAK void CORE_CriticalEnableIrq | ( | void |
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) |
Enable interrupts.
Enable interrupts by clearing PRIMASK.
Definition at line
322
of file
em_core.c
.
SL_WEAK CORE_irqState_t CORE_EnterAtomic | ( | void |
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) |
Enter an ATOMIC section.
When an ATOMIC section is entered, interrupts with priority lower or equal to CORE_ATOMIC_BASE_PRIORITY_LEVEL are disabled.
- Note
- If CORE_ATOMIC_METHOD is CORE_ATOMIC_METHOD_PRIMASK , this function is identical to CORE_EnterCritical() .
- Returns
- The value of BASEPRI register prior to ATOMIC section entry.
Definition at line
435
of file
em_core.c
.
References __NVIC_PRIO_BITS , and CORE_ATOMIC_BASE_PRIORITY_LEVEL .
SL_WEAK CORE_irqState_t CORE_EnterCritical | ( | void |
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) |
Enter a CRITICAL section.
When a CRITICAL section is entered, all interrupts (except fault handlers) are disabled.
- Returns
- The value of PRIMASK register prior to CRITICAL section entry.
Definition at line
337
of file
em_core.c
.
void CORE_EnterNvicMask | ( | CORE_nvicMask_t * |
nvicState,
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const CORE_nvicMask_t * |
disable
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) |
Enter a NVIC mask section.
When a NVIC mask section is entered, specified NVIC interrupts are disabled.
- Parameters
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[out] nvicState
Return NVIC interrupts enable mask prior to section entry. [in] disable
Mask specifying which NVIC interrupts to disable within the section.
Definition at line
513
of file
em_core.c
.
References CORE_CRITICAL_SECTION .
SL_WEAK void CORE_ExitAtomic | ( | CORE_irqState_t |
irqState
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) |
Exit an ATOMIC section.
- Parameters
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[in] irqState
The interrupt priority blocking level to restore to BASEPRI when exiting the ATOMIC section. This value is usually the one returned by a prior call to CORE_EnterAtomic() .
- Note
- If CORE_ATOMIC_METHOD is set to CORE_ATOMIC_METHOD_PRIMASK , this function is identical to CORE_ExitCritical() .
Definition at line
461
of file
em_core.c
.
SL_WEAK void CORE_ExitCritical | ( | CORE_irqState_t |
irqState
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) |
Exit a CRITICAL section.
- Parameters
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[in] irqState
The interrupt priority blocking level to restore to PRIMASK when exiting the CRITICAL section. This value is usually the one returned by a prior call to CORE_EnterCritical() .
Definition at line
353
of file
em_core.c
.
void CORE_GetNvicEnabledMask | ( | CORE_nvicMask_t * |
mask
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) |
Get current NVIC enable mask state.
- Parameters
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[out] mask
Current NVIC enable mask.
Definition at line
726
of file
em_core.c
.
References CORE_CRITICAL_SECTION .
bool CORE_GetNvicMaskDisableState | ( | const CORE_nvicMask_t * |
mask
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) |
Get NVIC disable state for a given mask.
- Parameters
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[in] mask
NVIC mask to check.
- Returns
- True if all NVIC interrupt mask bits are clear.
Definition at line
743
of file
em_core.c
.
References CORE_nvicMask_t::a , and CORE_CRITICAL_SECTION .
void * CORE_GetNvicRamTableHandler | ( | IRQn_Type |
irqN
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) |
Utility function to get the handler for a specific interrupt.
- Parameters
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[in] irqN
The IRQn_Type enumerator for the interrupt.
- Returns
- The handler address.
- Note
- Uses the interrupt vector table defined by current VTOR register value.
Definition at line
798
of file
em_core.c
.
References EXT_IRQ_COUNT .
SL_WEAK bool CORE_InIrqContext | ( | void |
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) |
Check if current cpu operation mode is handler mode.
- Returns
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True if cpu in handler mode (currently executing an interrupt handler).
False if cpu in thread mode.
Definition at line
643
of file
em_core.c
.
void CORE_InitNvicVectorTable | ( | uint32_t * |
sourceTable,
|
uint32_t |
sourceSize,
|
||
uint32_t * |
targetTable,
|
||
uint32_t |
targetSize,
|
||
void * |
defaultHandler,
|
||
bool |
overwriteActive
|
||
) |
Initialize an interrupt vector table by copying table entries from a source to a target table.
- Note
- This function will set a new VTOR register value.
- Parameters
-
[in] sourceTable
Address of source vector table. [in] sourceSize
Number of entries is source vector table. [in] targetTable
Address of target (new) vector table. [in] targetSize
Number of entries is target vector table. [in] defaultHandler
Address of interrupt handler used for target entries for which where there is no corresponding source entry (i.e. target table is larger than source table). [in] overwriteActive
When true, a target table entry is always overwritten with the corresponding source entry. If false, a target table entry is only overwritten if it is zero. This makes it possible for an application to partly initialize a target table before passing it to this function.
Definition at line
854
of file
em_core.c
.
Check if a specific interrupt is disabled or blocked.
- Parameters
-
[in] irqN
The IRQn_Type enumerator for the interrupt to check.
- Returns
- True if interrupt disabled or blocked.
Definition at line
658
of file
em_core.c
.
References __NVIC_PRIO_BITS , CORE_NvicIRQDisabled() , EXT_IRQ_COUNT , MemoryManagement_IRQn , and SVCall_IRQn .
Referenced by UARTDRV_ForceTransmit() .
SL_WEAK bool CORE_IrqIsDisabled | ( | void |
|
) |
Check if interrupts are disabled.
- Returns
- True if interrupts are disabled.
Definition at line
707
of file
em_core.c
.
References __NVIC_PRIO_BITS , and CORE_ATOMIC_BASE_PRIORITY_LEVEL .
void CORE_NvicDisableMask | ( | const CORE_nvicMask_t * |
disable
|
) |
Disable NVIC interrupts.
- Parameters
-
[in] disable
Mask specifying which NVIC interrupts to disable.
Definition at line
529
of file
em_core.c
.
References CORE_CRITICAL_SECTION .
void CORE_NvicEnableMask | ( | const CORE_nvicMask_t * |
enable
|
) |
Set current NVIC interrupt enable mask.
- Parameters
-
[out] enable
Mask specifying which NVIC interrupts are currently enabled.
Definition at line
543
of file
em_core.c
.
References CORE_CRITICAL_SECTION .
bool CORE_NvicIRQDisabled | ( | IRQn_Type |
irqN
|
) |
Check if a NVIC interrupt is disabled.
- Parameters
-
[in] irqN
The IRQn_Type enumerator for the interrupt to check.
- Returns
- True if interrupt disabled.
Definition at line
775
of file
em_core.c
.
References CORE_nvicMask_t::a , and EXT_IRQ_COUNT .
Referenced by CORE_IrqIsBlocked() .
void CORE_NvicMaskClearIRQ | ( | IRQn_Type |
irqN,
|
CORE_nvicMask_t * |
mask
|
||
) |
Utility function to clear an IRQn bit in a NVIC enable/disable mask.
- Parameters
-
[in] irqN
The IRQn_Type enumerator for the interrupt. [in,out] mask
The mask to clear interrupt bit in.
Definition at line
629
of file
em_core.c
.
References CORE_nvicMask_t::a , and EXT_IRQ_COUNT .
void CORE_NvicMaskSetIRQ | ( | IRQn_Type |
irqN,
|
CORE_nvicMask_t * |
mask
|
||
) |
Utility function to set an IRQn bit in a NVIC enable/disable mask.
- Parameters
-
[in] irqN
The IRQn_Type enumerator for the interrupt. [in,out] mask
The mask to set interrupt bit in.
Definition at line
613
of file
em_core.c
.
References CORE_nvicMask_t::a , and EXT_IRQ_COUNT .
void CORE_SetNvicRamTableHandler | ( | IRQn_Type |
irqN,
|
void * |
handler
|
||
) |
Utility function to set the handler for a specific interrupt.
- Parameters
-
[in] irqN
The IRQn_Type enumerator for the interrupt. [in] handler
The handler address.
- Note
- Uses the interrupt vector table defined by current VTOR register value.
Definition at line
817
of file
em_core.c
.
References EXT_IRQ_COUNT .
SL_WEAK void CORE_YieldAtomic | ( | void |
|
) |
Brief interrupt enable/disable sequence to allow handling of pending interrupts.
- Note
- Usully used within an ATOMIC section.
- If CORE_ATOMIC_METHOD is CORE_ATOMIC_METHOD_PRIMASK , this function is identical to CORE_YieldCritical() .
Definition at line
484
of file
em_core.c
.
References __NVIC_PRIO_BITS , and CORE_ATOMIC_BASE_PRIORITY_LEVEL .
SL_WEAK void CORE_YieldCritical | ( | void |
|
) |
Brief interrupt enable/disable sequence to allow handling of pending interrupts.
- Note
- Usully used within a CRITICAL section.
Definition at line
368
of file
em_core.c
.
void CORE_YieldNvicMask | ( | const CORE_nvicMask_t * |
enable
|
) |
Brief NVIC interrupt enable/disable sequence to allow handling of pending interrupts.
- Parameters
-
[in] enable
Mask specifying which NVIC interrupts to briefly enable.
- Note
- Usually used within a NVIC mask section.
Definition at line
561
of file
em_core.c
.
References CORE_nvicMask_t::a , and CORE_CRITICAL_SECTION .