SMU Bit FieldsDevices > EFR32MG13P932F512GM48 > Peripheral TypeDefsDevices > EFR32MG13P932F512GM48 > | Bit Fields > SMU
Macro Definition Documentation
#define _SMU_IEN_MASK 0x00000001UL |
Mask for SMU_IEN
Definition at line
5830
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IEN
Definition at line
5834
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IEN_PPUPRIV_MASK 0x1UL |
Bit mask for SMU_PPUPRIV
Definition at line
5833
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IEN_PPUPRIV_SHIFT 0 |
Shift value for SMU_PPUPRIV
Definition at line
5832
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IEN_RESETVALUE 0x00000000UL |
Default value for SMU_IEN
Definition at line
5829
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IF_MASK 0x00000001UL |
Mask for SMU_IF
Definition at line
5803
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IF
Definition at line
5807
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IF_PPUPRIV_MASK 0x1UL |
Bit mask for SMU_PPUPRIV
Definition at line
5806
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IF_PPUPRIV_SHIFT 0 |
Shift value for SMU_PPUPRIV
Definition at line
5805
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IF_RESETVALUE 0x00000000UL |
Default value for SMU_IF
Definition at line
5802
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IFC_MASK 0x00000001UL |
Mask for SMU_IFC
Definition at line
5821
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IFC
Definition at line
5825
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IFC_PPUPRIV_MASK 0x1UL |
Bit mask for SMU_PPUPRIV
Definition at line
5824
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IFC_PPUPRIV_SHIFT 0 |
Shift value for SMU_PPUPRIV
Definition at line
5823
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IFC_RESETVALUE 0x00000000UL |
Default value for SMU_IFC
Definition at line
5820
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IFS_MASK 0x00000001UL |
Mask for SMU_IFS
Definition at line
5812
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IFS
Definition at line
5816
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IFS_PPUPRIV_MASK 0x1UL |
Bit mask for SMU_PPUPRIV
Definition at line
5815
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IFS_PPUPRIV_SHIFT 0 |
Shift value for SMU_PPUPRIV
Definition at line
5814
of file
efr32mg13p932f512gm48.h
.
#define _SMU_IFS_RESETVALUE 0x00000000UL |
Default value for SMU_IFS
Definition at line
5811
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUCTRL
Definition at line
5843
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL |
Bit mask for SMU_ENABLE
Definition at line
5842
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUCTRL_ENABLE_SHIFT 0 |
Shift value for SMU_ENABLE
Definition at line
5841
of file
efr32mg13p932f512gm48.h
.
Referenced by SMU_EnablePPU() .
#define _SMU_PPUCTRL_MASK 0x00000001UL |
Mask for SMU_PPUCTRL
Definition at line
5839
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL |
Default value for SMU_PPUCTRL
Definition at line
5838
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_MASK 0x0000007FUL |
Mask for SMU_PPUFS
Definition at line
6016
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL |
Mode ACMP0 for SMU_PPUFS
Definition at line
6020
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL |
Mode ACMP1 for SMU_PPUFS
Definition at line
6021
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_ADC0 0x00000002UL |
Mode ADC0 for SMU_PPUFS
Definition at line
6022
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_CMU 0x00000005UL |
Mode CMU for SMU_PPUFS
Definition at line
6023
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000007UL |
Mode CRYOTIMER for SMU_PPUFS
Definition at line
6024
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x00000008UL |
Mode CRYPTO0 for SMU_PPUFS
Definition at line
6025
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_CRYPTO1 0x00000009UL |
Mode CRYPTO1 for SMU_PPUFS
Definition at line
6026
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUFS
Definition at line
6019
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_EMU 0x0000000DUL |
Mode EMU for SMU_PPUFS
Definition at line
6028
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_FPUEH 0x0000000EUL |
Mode FPUEH for SMU_PPUFS
Definition at line
6029
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000010UL |
Mode GPCRC for SMU_PPUFS
Definition at line
6030
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_GPIO 0x00000011UL |
Mode GPIO for SMU_PPUFS
Definition at line
6031
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_I2C0 0x00000012UL |
Mode I2C0 for SMU_PPUFS
Definition at line
6032
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_I2C1 0x00000013UL |
Mode I2C1 for SMU_PPUFS
Definition at line
6033
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_LDMA 0x00000016UL |
Mode LDMA for SMU_PPUFS
Definition at line
6035
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_LESENSE 0x00000017UL |
Mode LESENSE for SMU_PPUFS
Definition at line
6036
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_LETIMER0 0x00000018UL |
Mode LETIMER0 for SMU_PPUFS
Definition at line
6037
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_LEUART0 0x00000019UL |
Mode LEUART0 for SMU_PPUFS
Definition at line
6038
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL |
Bit mask for SMU_PERIPHID
Definition at line
6018
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_MSC 0x00000015UL |
Mode MSC for SMU_PPUFS
Definition at line
6034
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_PCNT0 0x0000001BUL |
Mode PCNT0 for SMU_PPUFS
Definition at line
6039
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_PRS 0x0000000CUL |
Mode PRS for SMU_PPUFS
Definition at line
6027
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_RMU 0x00000020UL |
Mode RMU for SMU_PPUFS
Definition at line
6040
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_RTCC 0x00000021UL |
Mode RTCC for SMU_PPUFS
Definition at line
6041
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_SHIFT 0 |
Shift value for SMU_PERIPHID
Definition at line
6017
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_SMU 0x00000022UL |
Mode SMU for SMU_PPUFS
Definition at line
6042
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000024UL |
Mode TIMER0 for SMU_PPUFS
Definition at line
6043
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_TIMER1 0x00000025UL |
Mode TIMER1 for SMU_PPUFS
Definition at line
6044
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000026UL |
Mode TRNG0 for SMU_PPUFS
Definition at line
6045
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_USART0 0x00000027UL |
Mode USART0 for SMU_PPUFS
Definition at line
6046
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_USART1 0x00000028UL |
Mode USART1 for SMU_PPUFS
Definition at line
6047
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_USART2 0x00000029UL |
Mode USART2 for SMU_PPUFS
Definition at line
6048
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000002AUL |
Mode WDOG0 for SMU_PPUFS
Definition at line
6049
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000002BUL |
Mode WDOG1 for SMU_PPUFS
Definition at line
6050
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000002CUL |
Mode WTIMER0 for SMU_PPUFS
Definition at line
6051
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUFS_RESETVALUE 0x00000000UL |
Default value for SMU_PPUFS
Definition at line
6015
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5852
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL |
Bit mask for SMU_ACMP0
Definition at line
5851
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_ACMP0_SHIFT 0 |
Shift value for SMU_ACMP0
Definition at line
5850
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5857
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL |
Bit mask for SMU_ACMP1
Definition at line
5856
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_ACMP1_SHIFT 1 |
Shift value for SMU_ACMP1
Definition at line
5855
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5862
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_ADC0_MASK 0x4UL |
Bit mask for SMU_ADC0
Definition at line
5861
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_ADC0_SHIFT 2 |
Shift value for SMU_ADC0
Definition at line
5860
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5867
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_CMU_MASK 0x20UL |
Bit mask for SMU_CMU
Definition at line
5866
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_CMU_SHIFT 5 |
Shift value for SMU_CMU
Definition at line
5865
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5872
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL |
Bit mask for SMU_CRYOTIMER
Definition at line
5871
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7 |
Shift value for SMU_CRYOTIMER
Definition at line
5870
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5877
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_CRYPTO0_MASK 0x100UL |
Bit mask for SMU_CRYPTO0
Definition at line
5876
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_CRYPTO0_SHIFT 8 |
Shift value for SMU_CRYPTO0
Definition at line
5875
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_CRYPTO1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5882
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_CRYPTO1_MASK 0x200UL |
Bit mask for SMU_CRYPTO1
Definition at line
5881
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_CRYPTO1_SHIFT 9 |
Shift value for SMU_CRYPTO1
Definition at line
5880
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5892
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_EMU_MASK 0x2000UL |
Bit mask for SMU_EMU
Definition at line
5891
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_EMU_SHIFT 13 |
Shift value for SMU_EMU
Definition at line
5890
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5897
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_FPUEH_MASK 0x4000UL |
Bit mask for SMU_FPUEH
Definition at line
5896
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_FPUEH_SHIFT 14 |
Shift value for SMU_FPUEH
Definition at line
5895
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5902
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_GPCRC_MASK 0x10000UL |
Bit mask for SMU_GPCRC
Definition at line
5901
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_GPCRC_SHIFT 16 |
Shift value for SMU_GPCRC
Definition at line
5900
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5907
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_GPIO_MASK 0x20000UL |
Bit mask for SMU_GPIO
Definition at line
5906
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_GPIO_SHIFT 17 |
Shift value for SMU_GPIO
Definition at line
5905
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5912
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_I2C0_MASK 0x40000UL |
Bit mask for SMU_I2C0
Definition at line
5911
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_I2C0_SHIFT 18 |
Shift value for SMU_I2C0
Definition at line
5910
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5917
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_I2C1_MASK 0x80000UL |
Bit mask for SMU_I2C1
Definition at line
5916
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_I2C1_SHIFT 19 |
Shift value for SMU_I2C1
Definition at line
5915
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5927
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_LDMA_MASK 0x400000UL |
Bit mask for SMU_LDMA
Definition at line
5926
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_LDMA_SHIFT 22 |
Shift value for SMU_LDMA
Definition at line
5925
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5932
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_LESENSE_MASK 0x800000UL |
Bit mask for SMU_LESENSE
Definition at line
5931
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_LESENSE_SHIFT 23 |
Shift value for SMU_LESENSE
Definition at line
5930
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5937
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_LETIMER0_MASK 0x1000000UL |
Bit mask for SMU_LETIMER0
Definition at line
5936
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_LETIMER0_SHIFT 24 |
Shift value for SMU_LETIMER0
Definition at line
5935
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5942
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_LEUART0_MASK 0x2000000UL |
Bit mask for SMU_LEUART0
Definition at line
5941
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_LEUART0_SHIFT 25 |
Shift value for SMU_LEUART0
Definition at line
5940
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_MASK 0x0BEF73A7UL |
Mask for SMU_PPUPATD0
Definition at line
5848
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5922
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_MSC_MASK 0x200000UL |
Bit mask for SMU_MSC
Definition at line
5921
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_MSC_SHIFT 21 |
Shift value for SMU_MSC
Definition at line
5920
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_PCNT0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5947
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_PCNT0_MASK 0x8000000UL |
Bit mask for SMU_PCNT0
Definition at line
5946
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_PCNT0_SHIFT 27 |
Shift value for SMU_PCNT0
Definition at line
5945
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
5887
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_PRS_MASK 0x1000UL |
Bit mask for SMU_PRS
Definition at line
5886
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_PRS_SHIFT 12 |
Shift value for SMU_PRS
Definition at line
5885
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL |
Default value for SMU_PPUPATD0
Definition at line
5847
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_MASK 0x00001FF7UL |
Mask for SMU_PPUPATD1
Definition at line
5952
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL |
Default value for SMU_PPUPATD1
Definition at line
5951
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
5956
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_RMU_MASK 0x1UL |
Bit mask for SMU_RMU
Definition at line
5955
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_RMU_SHIFT 0 |
Shift value for SMU_RMU
Definition at line
5954
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
5961
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_RTCC_MASK 0x2UL |
Bit mask for SMU_RTCC
Definition at line
5960
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_RTCC_SHIFT 1 |
Shift value for SMU_RTCC
Definition at line
5959
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
5966
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_SMU_MASK 0x4UL |
Bit mask for SMU_SMU
Definition at line
5965
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_SMU_SHIFT 2 |
Shift value for SMU_SMU
Definition at line
5964
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
5971
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_TIMER0_MASK 0x10UL |
Bit mask for SMU_TIMER0
Definition at line
5970
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_TIMER0_SHIFT 4 |
Shift value for SMU_TIMER0
Definition at line
5969
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
5976
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_TIMER1_MASK 0x20UL |
Bit mask for SMU_TIMER1
Definition at line
5975
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_TIMER1_SHIFT 5 |
Shift value for SMU_TIMER1
Definition at line
5974
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
5981
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_TRNG0_MASK 0x40UL |
Bit mask for SMU_TRNG0
Definition at line
5980
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_TRNG0_SHIFT 6 |
Shift value for SMU_TRNG0
Definition at line
5979
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
5986
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_USART0_MASK 0x80UL |
Bit mask for SMU_USART0
Definition at line
5985
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_USART0_SHIFT 7 |
Shift value for SMU_USART0
Definition at line
5984
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
5991
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_USART1_MASK 0x100UL |
Bit mask for SMU_USART1
Definition at line
5990
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_USART1_SHIFT 8 |
Shift value for SMU_USART1
Definition at line
5989
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
5996
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_USART2_MASK 0x200UL |
Bit mask for SMU_USART2
Definition at line
5995
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_USART2_SHIFT 9 |
Shift value for SMU_USART2
Definition at line
5994
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
6001
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_WDOG0_MASK 0x400UL |
Bit mask for SMU_WDOG0
Definition at line
6000
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_WDOG0_SHIFT 10 |
Shift value for SMU_WDOG0
Definition at line
5999
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
6006
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_WDOG1_MASK 0x800UL |
Bit mask for SMU_WDOG1
Definition at line
6005
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_WDOG1_SHIFT 11 |
Shift value for SMU_WDOG1
Definition at line
6004
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
6011
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_WTIMER0_MASK 0x1000UL |
Bit mask for SMU_WTIMER0
Definition at line
6010
of file
efr32mg13p932f512gm48.h
.
#define _SMU_PPUPATD1_WTIMER0_SHIFT 12 |
Shift value for SMU_WTIMER0
Definition at line
6009
of file
efr32mg13p932f512gm48.h
.
#define SMU_IEN_PPUPRIV (0x1UL << 0) |
PPUPRIV Interrupt Enable
Definition at line
5831
of file
efr32mg13p932f512gm48.h
.
#define SMU_IEN_PPUPRIV_DEFAULT ( _SMU_IEN_PPUPRIV_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_IEN
Definition at line
5835
of file
efr32mg13p932f512gm48.h
.
#define SMU_IF_PPUPRIV (0x1UL << 0) |
PPU Privilege Interrupt Flag
Definition at line
5804
of file
efr32mg13p932f512gm48.h
.
#define SMU_IF_PPUPRIV_DEFAULT ( _SMU_IF_PPUPRIV_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_IF
Definition at line
5808
of file
efr32mg13p932f512gm48.h
.
#define SMU_IFC_PPUPRIV (0x1UL << 0) |
Clear PPUPRIV Interrupt Flag
Definition at line
5822
of file
efr32mg13p932f512gm48.h
.
#define SMU_IFC_PPUPRIV_DEFAULT ( _SMU_IFC_PPUPRIV_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_IFC
Definition at line
5826
of file
efr32mg13p932f512gm48.h
.
#define SMU_IFS_PPUPRIV (0x1UL << 0) |
Set PPUPRIV Interrupt Flag
Definition at line
5813
of file
efr32mg13p932f512gm48.h
.
#define SMU_IFS_PPUPRIV_DEFAULT ( _SMU_IFS_PPUPRIV_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_IFS
Definition at line
5817
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUCTRL_ENABLE_DEFAULT ( _SMU_PPUCTRL_ENABLE_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_PPUCTRL
Definition at line
5844
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_ACMP0 ( _SMU_PPUFS_PERIPHID_ACMP0 << 0) |
Shifted mode ACMP0 for SMU_PPUFS
Definition at line
6053
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_ACMP1 ( _SMU_PPUFS_PERIPHID_ACMP1 << 0) |
Shifted mode ACMP1 for SMU_PPUFS
Definition at line
6054
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_ADC0 ( _SMU_PPUFS_PERIPHID_ADC0 << 0) |
Shifted mode ADC0 for SMU_PPUFS
Definition at line
6055
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_CMU ( _SMU_PPUFS_PERIPHID_CMU << 0) |
Shifted mode CMU for SMU_PPUFS
Definition at line
6056
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_CRYOTIMER ( _SMU_PPUFS_PERIPHID_CRYOTIMER << 0) |
Shifted mode CRYOTIMER for SMU_PPUFS
Definition at line
6057
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_CRYPTO0 ( _SMU_PPUFS_PERIPHID_CRYPTO0 << 0) |
Shifted mode CRYPTO0 for SMU_PPUFS
Definition at line
6058
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_CRYPTO1 ( _SMU_PPUFS_PERIPHID_CRYPTO1 << 0) |
Shifted mode CRYPTO1 for SMU_PPUFS
Definition at line
6059
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_DEFAULT ( _SMU_PPUFS_PERIPHID_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_PPUFS
Definition at line
6052
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_EMU ( _SMU_PPUFS_PERIPHID_EMU << 0) |
Shifted mode EMU for SMU_PPUFS
Definition at line
6061
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_FPUEH ( _SMU_PPUFS_PERIPHID_FPUEH << 0) |
Shifted mode FPUEH for SMU_PPUFS
Definition at line
6062
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_GPCRC ( _SMU_PPUFS_PERIPHID_GPCRC << 0) |
Shifted mode GPCRC for SMU_PPUFS
Definition at line
6063
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_GPIO ( _SMU_PPUFS_PERIPHID_GPIO << 0) |
Shifted mode GPIO for SMU_PPUFS
Definition at line
6064
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_I2C0 ( _SMU_PPUFS_PERIPHID_I2C0 << 0) |
Shifted mode I2C0 for SMU_PPUFS
Definition at line
6065
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_I2C1 ( _SMU_PPUFS_PERIPHID_I2C1 << 0) |
Shifted mode I2C1 for SMU_PPUFS
Definition at line
6066
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_LDMA ( _SMU_PPUFS_PERIPHID_LDMA << 0) |
Shifted mode LDMA for SMU_PPUFS
Definition at line
6068
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_LESENSE ( _SMU_PPUFS_PERIPHID_LESENSE << 0) |
Shifted mode LESENSE for SMU_PPUFS
Definition at line
6069
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_LETIMER0 ( _SMU_PPUFS_PERIPHID_LETIMER0 << 0) |
Shifted mode LETIMER0 for SMU_PPUFS
Definition at line
6070
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_LEUART0 ( _SMU_PPUFS_PERIPHID_LEUART0 << 0) |
Shifted mode LEUART0 for SMU_PPUFS
Definition at line
6071
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_MSC ( _SMU_PPUFS_PERIPHID_MSC << 0) |
Shifted mode MSC for SMU_PPUFS
Definition at line
6067
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_PCNT0 ( _SMU_PPUFS_PERIPHID_PCNT0 << 0) |
Shifted mode PCNT0 for SMU_PPUFS
Definition at line
6072
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_PRS ( _SMU_PPUFS_PERIPHID_PRS << 0) |
Shifted mode PRS for SMU_PPUFS
Definition at line
6060
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_RMU ( _SMU_PPUFS_PERIPHID_RMU << 0) |
Shifted mode RMU for SMU_PPUFS
Definition at line
6073
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_RTCC ( _SMU_PPUFS_PERIPHID_RTCC << 0) |
Shifted mode RTCC for SMU_PPUFS
Definition at line
6074
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_SMU ( _SMU_PPUFS_PERIPHID_SMU << 0) |
Shifted mode SMU for SMU_PPUFS
Definition at line
6075
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_TIMER0 ( _SMU_PPUFS_PERIPHID_TIMER0 << 0) |
Shifted mode TIMER0 for SMU_PPUFS
Definition at line
6076
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_TIMER1 ( _SMU_PPUFS_PERIPHID_TIMER1 << 0) |
Shifted mode TIMER1 for SMU_PPUFS
Definition at line
6077
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_TRNG0 ( _SMU_PPUFS_PERIPHID_TRNG0 << 0) |
Shifted mode TRNG0 for SMU_PPUFS
Definition at line
6078
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_USART0 ( _SMU_PPUFS_PERIPHID_USART0 << 0) |
Shifted mode USART0 for SMU_PPUFS
Definition at line
6079
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_USART1 ( _SMU_PPUFS_PERIPHID_USART1 << 0) |
Shifted mode USART1 for SMU_PPUFS
Definition at line
6080
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_USART2 ( _SMU_PPUFS_PERIPHID_USART2 << 0) |
Shifted mode USART2 for SMU_PPUFS
Definition at line
6081
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_WDOG0 ( _SMU_PPUFS_PERIPHID_WDOG0 << 0) |
Shifted mode WDOG0 for SMU_PPUFS
Definition at line
6082
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_WDOG1 ( _SMU_PPUFS_PERIPHID_WDOG1 << 0) |
Shifted mode WDOG1 for SMU_PPUFS
Definition at line
6083
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUFS_PERIPHID_WTIMER0 ( _SMU_PPUFS_PERIPHID_WTIMER0 << 0) |
Shifted mode WTIMER0 for SMU_PPUFS
Definition at line
6084
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) |
Analog Comparator 0 access control bit
Definition at line
5849
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_ACMP0_DEFAULT ( _SMU_PPUPATD0_ACMP0_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5853
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) |
Analog Comparator 1 access control bit
Definition at line
5854
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_ACMP1_DEFAULT ( _SMU_PPUPATD0_ACMP1_DEFAULT << 1) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5858
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_ADC0 (0x1UL << 2) |
Analog to Digital Converter 0 access control bit
Definition at line
5859
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_ADC0_DEFAULT ( _SMU_PPUPATD0_ADC0_DEFAULT << 2) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5863
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_CMU (0x1UL << 5) |
Clock Management Unit access control bit
Definition at line
5864
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_CMU_DEFAULT ( _SMU_PPUPATD0_CMU_DEFAULT << 5) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5868
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) |
CryoTimer access control bit
Definition at line
5869
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_CRYOTIMER_DEFAULT ( _SMU_PPUPATD0_CRYOTIMER_DEFAULT << 7) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5873
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 8) |
Advanced Encryption Standard Accelerator 0 access control bit
Definition at line
5874
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_CRYPTO0_DEFAULT ( _SMU_PPUPATD0_CRYPTO0_DEFAULT << 8) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5878
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_CRYPTO1 (0x1UL << 9) |
Advanced Encryption Standard Accelerator 1 access control bit
Definition at line
5879
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_CRYPTO1_DEFAULT ( _SMU_PPUPATD0_CRYPTO1_DEFAULT << 9) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5883
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_EMU (0x1UL << 13) |
Energy Management Unit access control bit
Definition at line
5889
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_EMU_DEFAULT ( _SMU_PPUPATD0_EMU_DEFAULT << 13) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5893
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_FPUEH (0x1UL << 14) |
FPU Exception Handler access control bit
Definition at line
5894
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_FPUEH_DEFAULT ( _SMU_PPUPATD0_FPUEH_DEFAULT << 14) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5898
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_GPCRC (0x1UL << 16) |
General Purpose CRC access control bit
Definition at line
5899
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_GPCRC_DEFAULT ( _SMU_PPUPATD0_GPCRC_DEFAULT << 16) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5903
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_GPIO (0x1UL << 17) |
General purpose Input/Output access control bit
Definition at line
5904
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_GPIO_DEFAULT ( _SMU_PPUPATD0_GPIO_DEFAULT << 17) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5908
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_I2C0 (0x1UL << 18) |
I2C 0 access control bit
Definition at line
5909
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_I2C0_DEFAULT ( _SMU_PPUPATD0_I2C0_DEFAULT << 18) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5913
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_I2C1 (0x1UL << 19) |
I2C 1 access control bit
Definition at line
5914
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_I2C1_DEFAULT ( _SMU_PPUPATD0_I2C1_DEFAULT << 19) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5918
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_LDMA (0x1UL << 22) |
Linked Direct Memory Access Controller access control bit
Definition at line
5924
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_LDMA_DEFAULT ( _SMU_PPUPATD0_LDMA_DEFAULT << 22) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5928
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_LESENSE (0x1UL << 23) |
Low Energy Sensor Interface access control bit
Definition at line
5929
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_LESENSE_DEFAULT ( _SMU_PPUPATD0_LESENSE_DEFAULT << 23) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5933
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_LETIMER0 (0x1UL << 24) |
Low Energy Timer 0 access control bit
Definition at line
5934
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_LETIMER0_DEFAULT ( _SMU_PPUPATD0_LETIMER0_DEFAULT << 24) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5938
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_LEUART0 (0x1UL << 25) |
Low Energy UART 0 access control bit
Definition at line
5939
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_LEUART0_DEFAULT ( _SMU_PPUPATD0_LEUART0_DEFAULT << 25) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5943
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_MSC (0x1UL << 21) |
Memory System Controller access control bit
Definition at line
5919
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_MSC_DEFAULT ( _SMU_PPUPATD0_MSC_DEFAULT << 21) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5923
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_PCNT0 (0x1UL << 27) |
Pulse Counter 0 access control bit
Definition at line
5944
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_PCNT0_DEFAULT ( _SMU_PPUPATD0_PCNT0_DEFAULT << 27) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5948
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_PRS (0x1UL << 12) |
Peripheral Reflex System access control bit
Definition at line
5884
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD0_PRS_DEFAULT ( _SMU_PPUPATD0_PRS_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
5888
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_RMU (0x1UL << 0) |
Reset Management Unit access control bit
Definition at line
5953
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_RMU_DEFAULT ( _SMU_PPUPATD1_RMU_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
5957
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_RTCC (0x1UL << 1) |
Real-Time Counter and Calendar access control bit
Definition at line
5958
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_RTCC_DEFAULT ( _SMU_PPUPATD1_RTCC_DEFAULT << 1) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
5962
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_SMU (0x1UL << 2) |
Security Management Unit access control bit
Definition at line
5963
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_SMU_DEFAULT ( _SMU_PPUPATD1_SMU_DEFAULT << 2) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
5967
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_TIMER0 (0x1UL << 4) |
Timer 0 access control bit
Definition at line
5968
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_TIMER0_DEFAULT ( _SMU_PPUPATD1_TIMER0_DEFAULT << 4) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
5972
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_TIMER1 (0x1UL << 5) |
Timer 1 access control bit
Definition at line
5973
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_TIMER1_DEFAULT ( _SMU_PPUPATD1_TIMER1_DEFAULT << 5) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
5977
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_TRNG0 (0x1UL << 6) |
True Random Number Generator 0 access control bit
Definition at line
5978
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_TRNG0_DEFAULT ( _SMU_PPUPATD1_TRNG0_DEFAULT << 6) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
5982
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_USART0 (0x1UL << 7) |
Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit
Definition at line
5983
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_USART0_DEFAULT ( _SMU_PPUPATD1_USART0_DEFAULT << 7) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
5987
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_USART1 (0x1UL << 8) |
Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit
Definition at line
5988
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_USART1_DEFAULT ( _SMU_PPUPATD1_USART1_DEFAULT << 8) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
5992
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_USART2 (0x1UL << 9) |
Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit
Definition at line
5993
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_USART2_DEFAULT ( _SMU_PPUPATD1_USART2_DEFAULT << 9) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
5997
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_WDOG0 (0x1UL << 10) |
Watchdog 0 access control bit
Definition at line
5998
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_WDOG0_DEFAULT ( _SMU_PPUPATD1_WDOG0_DEFAULT << 10) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
6002
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_WDOG1 (0x1UL << 11) |
Watchdog 1 access control bit
Definition at line
6003
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_WDOG1_DEFAULT ( _SMU_PPUPATD1_WDOG1_DEFAULT << 11) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
6007
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_WTIMER0 (0x1UL << 12) |
Wide Timer 0 access control bit
Definition at line
6008
of file
efr32mg13p932f512gm48.h
.
#define SMU_PPUPATD1_WTIMER0_DEFAULT ( _SMU_PPUPATD1_WTIMER0_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
6012
of file
efr32mg13p932f512gm48.h
.