LDMA_TypeDef Struct ReferenceDevices > EFR32MG13P932F512GM48 > Peripheral TypeDefsDevices > EFR32MG13P932F512GM48 > | Bit Fields > LDMADevices > | LDMA
LDMA Register Declaration
Definition at line
473
of file
efr32mg13p932f512gm48.h
.
#include <
efr32mg13p932f512gm48.h
>
Data Fields |
|
| LDMA_CH_TypeDef | CH [8U] |
| __IM uint32_t | CHBUSY |
| __IOM uint32_t | CHDONE |
| __IOM uint32_t | CHEN |
| __IOM uint32_t | CTRL |
| __IOM uint32_t | DBGHALT |
| __IOM uint32_t | IEN |
| __IM uint32_t | IF |
| __IOM uint32_t | IFC |
| __IOM uint32_t | IFS |
| __IOM uint32_t | LINKLOAD |
| __IOM uint32_t | REQCLEAR |
| __IOM uint32_t | REQDIS |
| __IM uint32_t | REQPEND |
| uint32_t | RESERVED0 [5U] |
| uint32_t | RESERVED1 [7U] |
| uint32_t | RESERVED2 [4U] |
| __IM uint32_t | STATUS |
| __IOM uint32_t | SWREQ |
| __IOM uint32_t | SYNC |
Field Documentation
| LDMA_CH_TypeDef LDMA_TypeDef::CH |
DMA Channel Registers
Definition at line
494
of file
efr32mg13p932f512gm48.h
.
| __IM uint32_t LDMA_TypeDef::CHBUSY |
DMA Channel Busy Register
Definition at line
479
of file
efr32mg13p932f512gm48.h
.
| __IOM uint32_t LDMA_TypeDef::CHDONE |
DMA Channel Linking Done Register (Single-Cycle RMW)
Definition at line
480
of file
efr32mg13p932f512gm48.h
.
| __IOM uint32_t LDMA_TypeDef::CHEN |
DMA Channel Enable Register (Single-Cycle RMW)
Definition at line
478
of file
efr32mg13p932f512gm48.h
.
| __IOM uint32_t LDMA_TypeDef::CTRL |
DMA Control Register
Definition at line
474
of file
efr32mg13p932f512gm48.h
.
| __IOM uint32_t LDMA_TypeDef::DBGHALT |
DMA Channel Debug Halt Register
Definition at line
481
of file
efr32mg13p932f512gm48.h
.
| __IOM uint32_t LDMA_TypeDef::IEN |
Interrupt Enable Register
Definition at line
491
of file
efr32mg13p932f512gm48.h
.
| __IM uint32_t LDMA_TypeDef::IF |
Interrupt Flag Register
Definition at line
488
of file
efr32mg13p932f512gm48.h
.
| __IOM uint32_t LDMA_TypeDef::IFC |
Interrupt Flag Clear Register
Definition at line
490
of file
efr32mg13p932f512gm48.h
.
| __IOM uint32_t LDMA_TypeDef::IFS |
Interrupt Flag Set Register
Definition at line
489
of file
efr32mg13p932f512gm48.h
.
| __IOM uint32_t LDMA_TypeDef::LINKLOAD |
DMA Channel Link Load Register
Definition at line
485
of file
efr32mg13p932f512gm48.h
.
| __IOM uint32_t LDMA_TypeDef::REQCLEAR |
DMA Channel Request Clear Register
Definition at line
486
of file
efr32mg13p932f512gm48.h
.
| __IOM uint32_t LDMA_TypeDef::REQDIS |
DMA Channel Request Disable Register
Definition at line
483
of file
efr32mg13p932f512gm48.h
.
| __IM uint32_t LDMA_TypeDef::REQPEND |
DMA Channel Requests Pending Register
Definition at line
484
of file
efr32mg13p932f512gm48.h
.
| uint32_t LDMA_TypeDef::RESERVED0 |
Reserved for future use
Definition at line
477
of file
efr32mg13p932f512gm48.h
.
| uint32_t LDMA_TypeDef::RESERVED1 |
Reserved for future use
Definition at line
487
of file
efr32mg13p932f512gm48.h
.
| uint32_t LDMA_TypeDef::RESERVED2 |
Reserved registers
Definition at line
493
of file
efr32mg13p932f512gm48.h
.
| __IM uint32_t LDMA_TypeDef::STATUS |
DMA Status Register
Definition at line
475
of file
efr32mg13p932f512gm48.h
.
| __IOM uint32_t LDMA_TypeDef::SWREQ |
DMA Channel Software Transfer Request Register
Definition at line
482
of file
efr32mg13p932f512gm48.h
.
| __IOM uint32_t LDMA_TypeDef::SYNC |
DMA Synchronization Trigger Register (Single-Cycle RMW)
Definition at line
476
of file
efr32mg13p932f512gm48.h
.
The documentation for this struct was generated from the following files:
-
C:/repos/super_h1/platform/Device/SiliconLabs/EFR32MG13P/Include/
efr32mg13p932f512gm48.h -
C:/repos/super_h1/platform/Device/SiliconLabs/EFR32MG13P/Include/
efr32mg13p_ldma.h