EFM32GG995F1024 Peripheral Memory MapDevices > EFM32GG995F1024
| Macros | |
| #define | ACMP0_BASE (0x40001000UL) | 
| #define | ACMP1_BASE (0x40001400UL) | 
| #define | ADC0_BASE (0x40002000UL) | 
| #define | AES_BASE (0x400E0000UL) | 
| #define | BURTC_BASE (0x40081000UL) | 
| #define | CALIBRATE_BASE (0x0FE08000UL) | 
| #define | CMU_BASE (0x400C8000UL) | 
| #define | DAC0_BASE (0x40004000UL) | 
| #define | DEVINFO_BASE (0x0FE081B0UL) | 
| #define | DMA_BASE (0x400C2000UL) | 
| #define | EBI_BASE (0x40008000UL) | 
| #define | EMU_BASE (0x400C6000UL) | 
| #define | ETM_BASE (0xE0041000UL) | 
| #define | GPIO_BASE (0x40006000UL) | 
| #define | I2C0_BASE (0x4000A000UL) | 
| #define | I2C1_BASE (0x4000A400UL) | 
| #define | LCD_BASE (0x4008A000UL) | 
| #define | LESENSE_BASE (0x4008C000UL) | 
| #define | LETIMER0_BASE (0x40082000UL) | 
| #define | LEUART0_BASE (0x40084000UL) | 
| #define | LEUART1_BASE (0x40084400UL) | 
| #define | LOCKBITS_BASE (0x0FE04000UL) | 
| #define | MSC_BASE (0x400C0000UL) | 
| #define | PCNT0_BASE (0x40086000UL) | 
| #define | PCNT1_BASE (0x40086400UL) | 
| #define | PCNT2_BASE (0x40086800UL) | 
| #define | PRS_BASE (0x400CC000UL) | 
| #define | RMU_BASE (0x400CA000UL) | 
| #define | ROMTABLE_BASE (0xE00FFFD0UL) | 
| #define | RTC_BASE (0x40080000UL) | 
| #define | TIMER0_BASE (0x40010000UL) | 
| #define | TIMER1_BASE (0x40010400UL) | 
| #define | TIMER2_BASE (0x40010800UL) | 
| #define | TIMER3_BASE (0x40010C00UL) | 
| #define | UART0_BASE (0x4000E000UL) | 
| #define | UART1_BASE (0x4000E400UL) | 
| #define | USART0_BASE (0x4000C000UL) | 
| #define | USART1_BASE (0x4000C400UL) | 
| #define | USART2_BASE (0x4000C800UL) | 
| #define | USB_BASE (0x400C4000UL) | 
| #define | USERDATA_BASE (0x0FE00000UL) | 
| #define | VCMP_BASE (0x40000000UL) | 
| #define | WDOG_BASE (0x40088000UL) | 
Macro Definition Documentation
| #define ACMP0_BASE (0x40001000UL) | 
ACMP0 base address
        Definition at line
        
         357
        
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         efm32gg995f1024.h
        
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| #define ACMP1_BASE (0x40001400UL) | 
ACMP1 base address
        Definition at line
        
         358
        
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| #define ADC0_BASE (0x40002000UL) | 
ADC0 base address
        Definition at line
        
         369
        
        of file
        
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| #define AES_BASE (0x400E0000UL) | 
AES base address
        Definition at line
        
         338
        
        of file
        
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| #define BURTC_BASE (0x40081000UL) | 
BURTC base address
        Definition at line
        
         372
        
        of file
        
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| #define CALIBRATE_BASE (0x0FE08000UL) | 
CALIBRATE base address
        Definition at line
        
         375
        
        of file
        
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| #define CMU_BASE (0x400C8000UL) | 
CMU base address
        Definition at line
        
         343
        
        of file
        
         efm32gg995f1024.h
        
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| #define DAC0_BASE (0x40004000UL) | 
DAC0 base address
        Definition at line
        
         370
        
        of file
        
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| #define DEVINFO_BASE (0x0FE081B0UL) | 
DEVINFO base address
        Definition at line
        
         376
        
        of file
        
         efm32gg995f1024.h
        
        .
       
Referenced by SYSTEM_GetCalibrationValue() .
| #define DMA_BASE (0x400C2000UL) | 
DMA base address
        Definition at line
        
         337
        
        of file
        
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| #define EBI_BASE (0x40008000UL) | 
EBI base address
        Definition at line
        
         347
        
        of file
        
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| #define EMU_BASE (0x400C6000UL) | 
EMU base address
        Definition at line
        
         341
        
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Referenced by CHIP_Init() , EMU_EnterEM4() , and RMU_ResetCauseGet() .
| #define ETM_BASE (0xE0041000UL) | 
ETM base address
        Definition at line
        
         374
        
        of file
        
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| #define GPIO_BASE (0x40006000UL) | 
GPIO base address
        Definition at line
        
         361
        
        of file
        
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| #define I2C0_BASE (0x4000A000UL) | 
I2C0 base address
        Definition at line
        
         359
        
        of file
        
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| #define I2C1_BASE (0x4000A400UL) | 
I2C1 base address
        Definition at line
        
         360
        
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| #define LCD_BASE (0x4008A000UL) | 
| #define LESENSE_BASE (0x4008C000UL) | 
LESENSE base address
        Definition at line
        
         344
        
        of file
        
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| #define LETIMER0_BASE (0x40082000UL) | 
LETIMER0 base address
        Definition at line
        
         346
        
        of file
        
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| #define LEUART0_BASE (0x40084000UL) | 
LEUART0 base address
        Definition at line
        
         364
        
        of file
        
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| #define LEUART1_BASE (0x40084400UL) | 
LEUART1 base address
        Definition at line
        
         365
        
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| #define LOCKBITS_BASE (0x0FE04000UL) | 
Lock-bits page base address
        Definition at line
        
         378
        
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| #define MSC_BASE (0x400C0000UL) | 
MSC base address
        Definition at line
        
         340
        
        of file
        
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| #define PCNT0_BASE (0x40086000UL) | 
PCNT0 base address
        Definition at line
        
         366
        
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| #define PCNT1_BASE (0x40086400UL) | 
PCNT1 base address
        Definition at line
        
         367
        
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| #define PCNT2_BASE (0x40086800UL) | 
PCNT2 base address
        Definition at line
        
         368
        
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| #define PRS_BASE (0x400CC000UL) | 
PRS base address
        Definition at line
        
         363
        
        of file
        
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| #define RMU_BASE (0x400CA000UL) | 
RMU base address
        Definition at line
        
         342
        
        of file
        
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| #define ROMTABLE_BASE (0xE00FFFD0UL) | 
ROMTABLE base address
        Definition at line
        
         377
        
        of file
        
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| #define RTC_BASE (0x40080000UL) | 
RTC base address
        Definition at line
        
         345
        
        of file
        
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| #define TIMER0_BASE (0x40010000UL) | 
TIMER0 base address
        Definition at line
        
         353
        
        of file
        
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| #define TIMER1_BASE (0x40010400UL) | 
TIMER1 base address
        Definition at line
        
         354
        
        of file
        
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| #define TIMER2_BASE (0x40010800UL) | 
TIMER2 base address
        Definition at line
        
         355
        
        of file
        
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| #define TIMER3_BASE (0x40010C00UL) | 
TIMER3 base address
        Definition at line
        
         356
        
        of file
        
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| #define UART0_BASE (0x4000E000UL) | 
UART0 base address
        Definition at line
        
         351
        
        of file
        
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| #define UART1_BASE (0x4000E400UL) | 
UART1 base address
        Definition at line
        
         352
        
        of file
        
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| #define USART0_BASE (0x4000C000UL) | 
USART0 base address
        Definition at line
        
         348
        
        of file
        
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        .
       
| #define USART1_BASE (0x4000C400UL) | 
USART1 base address
        Definition at line
        
         349
        
        of file
        
         efm32gg995f1024.h
        
        .
       
| #define USART2_BASE (0x4000C800UL) | 
USART2 base address
        Definition at line
        
         350
        
        of file
        
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| #define USB_BASE (0x400C4000UL) | 
USB base address
        Definition at line
        
         339
        
        of file
        
         efm32gg995f1024.h
        
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| #define USERDATA_BASE (0x0FE00000UL) | 
User data page base address
        Definition at line
        
         379
        
        of file
        
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| #define VCMP_BASE (0x40000000UL) | 
VCMP base address
        Definition at line
        
         362
        
        of file
        
         efm32gg995f1024.h
        
        .
       
| #define WDOG_BASE (0x40088000UL) | 
WDOG base address
        Definition at line
        
         373
        
        of file
        
         efm32gg995f1024.h
        
        .