Modules
EFM32TG842F32 Alternate Function

EFM32TG842F32 Bit Fields

EFM32TG842F32 Core
Processor and Core Peripheral Section.

EFM32TG842F32 Part

EFM32TG842F32 Peripheral Declarations

EFM32TG842F32 Peripheral Memory Map

EFM32TG842F32 Peripheral TypeDefs
Device Specific Peripheral Register Structures.

Macros
#define	SET_BIT_FIELD (REG, MASK, VALUE, OFFSET) REG = ((REG) &~(MASK)) \| (((VALUE) << (OFFSET)) & (MASK));
	Set the value of a bit field within a register.

Enumerations
enum	IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, DMA_IRQn = 0, GPIO_EVEN_IRQn = 1, TIMER0_IRQn = 2, USART0_RX_IRQn = 3, USART0_TX_IRQn = 4, ACMP0_IRQn = 5, ADC0_IRQn = 6, DAC0_IRQn = 7, I2C0_IRQn = 8, GPIO_ODD_IRQn = 9, TIMER1_IRQn = 10, USART1_RX_IRQn = 11, USART1_TX_IRQn = 12, LESENSE_IRQn = 13, LEUART0_IRQn = 14, LETIMER0_IRQn = 15, PCNT0_IRQn = 16, RTC_IRQn = 17, CMU_IRQn = 18, VCMP_IRQn = 19, LCD_IRQn = 20, MSC_IRQn = 21, AES_IRQn = 22 }

Macro Definition Documentation

#define SET_BIT_FIELD	(	`REG,`
		`MASK,`
		`VALUE,`
		`OFFSET`
	)	REG = ((REG) &~(MASK)) \| (((VALUE) << (OFFSET)) & (MASK));

Set the value of a bit field within a register.

Parameters

`REG`	The register to update
`MASK`	The mask for the bit field to update
`VALUE`	The value to write to the bit field
`OFFSET`	The number of bits that the field is offset within the register. 0 (zero) means LSB.

Definition at line 401 of file efm32tg842f32.h .

Typedef Documentation

Interrupt Number Definition

enum IRQn

Interrupt Number Definition

Enumerator
NonMaskableInt_IRQn	-14 Cortex-M3 Non Maskable Interrupt
HardFault_IRQn	-13 Cortex-M3 Hard Fault Interrupt
MemoryManagement_IRQn	-12 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	-11 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	-10 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	-5 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	-4 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	-2 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	-1 Cortex-M3 System Tick Interrupt
DMA_IRQn	0 EFM32 DMA Interrupt
GPIO_EVEN_IRQn	1 EFM32 GPIO_EVEN Interrupt
TIMER0_IRQn	2 EFM32 TIMER0 Interrupt
USART0_RX_IRQn	3 EFM32 USART0_RX Interrupt
USART0_TX_IRQn	4 EFM32 USART0_TX Interrupt
ACMP0_IRQn	5 EFM32 ACMP0 Interrupt
ADC0_IRQn	6 EFM32 ADC0 Interrupt
DAC0_IRQn	7 EFM32 DAC0 Interrupt
I2C0_IRQn	8 EFM32 I2C0 Interrupt
GPIO_ODD_IRQn	9 EFM32 GPIO_ODD Interrupt
TIMER1_IRQn	10 EFM32 TIMER1 Interrupt
USART1_RX_IRQn	11 EFM32 USART1_RX Interrupt
USART1_TX_IRQn	12 EFM32 USART1_TX Interrupt
LESENSE_IRQn	13 EFM32 LESENSE Interrupt
LEUART0_IRQn	14 EFM32 LEUART0 Interrupt
LETIMER0_IRQn	15 EFM32 LETIMER0 Interrupt
PCNT0_IRQn	16 EFM32 PCNT0 Interrupt
RTC_IRQn	17 EFM32 RTC Interrupt
CMU_IRQn	18 EFM32 CMU Interrupt
VCMP_IRQn	19 EFM32 VCMP Interrupt
LCD_IRQn	20 EFM32 LCD Interrupt
MSC_IRQn	21 EFM32 MSC Interrupt
AES_IRQn	22 EFM32 AES Interrupt

Definition at line 57 of file efm32tg842f32.h .