EFM32ZG222F32Devices
Modules |
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EFM32ZG222F32 Alternate Function | |
EFM32ZG222F32 Bit Fields | |
EFM32ZG222F32 Core | |
Processor and Core Peripheral Section.
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EFM32ZG222F32 Part | |
EFM32ZG222F32 Peripheral Declarations | |
EFM32ZG222F32 Peripheral Memory Map | |
EFM32ZG222F32 Peripheral TypeDefs | |
Device Specific Peripheral Register Structures.
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Macros |
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#define | ARM_MATH_CM0PLUS |
#define | SET_BIT_FIELD (REG, MASK, VALUE, OFFSET) REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); |
Set the value of a bit field within a register.
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Typedefs |
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typedef enum IRQn | IRQn_Type |
Enumerations |
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enum |
IRQn
{
NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2, SysTick_IRQn = -1, DMA_IRQn = 0, GPIO_EVEN_IRQn = 1, TIMER0_IRQn = 2, ACMP0_IRQn = 3, ADC0_IRQn = 4, I2C0_IRQn = 5, GPIO_ODD_IRQn = 6, TIMER1_IRQn = 7, USART1_RX_IRQn = 8, USART1_TX_IRQn = 9, LEUART0_IRQn = 10, PCNT0_IRQn = 11, RTC_IRQn = 12, CMU_IRQn = 13, VCMP_IRQn = 14, MSC_IRQn = 15, AES_IRQn = 16 } |
Macro Definition Documentation
#define SET_BIT_FIELD | ( |
REG,
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MASK,
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VALUE,
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OFFSET
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) | REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); |
Set the value of a bit field within a register.
- Parameters
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REG
The register to update MASK
The mask for the bit field to update VALUE
The value to write to the bit field OFFSET
The number of bits that the field is offset within the register. 0 (zero) means LSB.
Definition at line
366
of file
efm32zg222f32.h
.
Typedef Documentation
Enumeration Type Documentation
enum IRQn |
Interrupt Number Definition
Definition at line
58
of file
efm32zg222f32.h
.