icm20648.h File Reference

Driver for the Invensense ICM20648 6-axis motion sensor.

Version
5.5.0

License

Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com

This file is licensed under the Silicon Labs License Agreement. See the file "Silabs_License_Agreement.txt" for details. Before using this software for any purpose, you must agree to the terms of that agreement.

Definition in file icm20648.h .

#include <stdint.h>
#include "icm20648_config.h"

Macros

Error Codes
#define ICM20648_OK 0x0000
#define ICM20648_ERROR_INVALID_DEVICE_ID 0x0001
ICM20648 register banks
#define ICM20648_BANK_0 (0 << 7)
#define ICM20648_BANK_1 (1 << 7)
#define ICM20648_BANK_2 (2 << 7)
#define ICM20648_BANK_3 (3 << 7)
Register and associated bit definitions
#define ICM20648_REG_WHO_AM_I ( ICM20648_BANK_0 | 0x00)
#define ICM20648_REG_USER_CTRL ( ICM20648_BANK_0 | 0x03)
#define ICM20648_BIT_DMP_EN 0x80
#define ICM20648_BIT_FIFO_EN 0x40
#define ICM20648_BIT_I2C_MST_EN 0x20
#define ICM20648_BIT_I2C_IF_DIS 0x10
#define ICM20648_BIT_DMP_RST 0x08
#define ICM20648_BIT_DIAMOND_DMP_RST 0x04
#define ICM20648_REG_LP_CONFIG ( ICM20648_BANK_0 | 0x05)
#define ICM20648_BIT_I2C_MST_CYCLE 0x40
#define ICM20648_BIT_ACCEL_CYCLE 0x20
#define ICM20648_BIT_GYRO_CYCLE 0x10
#define ICM20648_REG_PWR_MGMT_1 ( ICM20648_BANK_0 | 0x06)
#define ICM20648_BIT_H_RESET 0x80
#define ICM20648_BIT_SLEEP 0x40
#define ICM20648_BIT_LP_EN 0x20
#define ICM20648_BIT_TEMP_DIS 0x08
#define ICM20648_BIT_CLK_PLL 0x01
#define ICM20648_REG_PWR_MGMT_2 ( ICM20648_BANK_0 | 0x07)
#define ICM20648_BIT_PWR_ACCEL_STBY 0x38
#define ICM20648_BIT_PWR_GYRO_STBY 0x07
#define ICM20648_BIT_PWR_ALL_OFF 0x7F
#define ICM20648_REG_INT_PIN_CFG ( ICM20648_BANK_0 | 0x0F)
#define ICM20648_BIT_INT_ACTL 0x80
#define ICM20648_BIT_INT_OPEN 0x40
#define ICM20648_BIT_INT_LATCH_EN 0x20
#define ICM20648_REG_INT_ENABLE ( ICM20648_BANK_0 | 0x10)
#define ICM20648_BIT_WOM_INT_EN 0x08
#define ICM20648_REG_INT_ENABLE_1 ( ICM20648_BANK_0 | 0x11)
#define ICM20648_BIT_RAW_DATA_0_RDY_EN 0x01
#define ICM20648_REG_INT_ENABLE_2 ( ICM20648_BANK_0 | 0x12)
#define ICM20648_BIT_FIFO_OVERFLOW_EN_0 0x01
#define ICM20648_REG_INT_ENABLE_3 ( ICM20648_BANK_0 | 0x13)
#define ICM20648_REG_INT_STATUS ( ICM20648_BANK_0 | 0x19)
#define ICM20648_BIT_WOM_INT 0x08
#define ICM20648_BIT_PLL_RDY 0x04
#define ICM20648_REG_INT_STATUS_1 ( ICM20648_BANK_0 | 0x1A)
#define ICM20648_BIT_RAW_DATA_0_RDY_INT 0x01
#define ICM20648_REG_INT_STATUS_2 ( ICM20648_BANK_0 | 0x1B)
#define ICM20648_REG_ACCEL_XOUT_H_SH ( ICM20648_BANK_0 | 0x2D)
#define ICM20648_REG_ACCEL_XOUT_L_SH ( ICM20648_BANK_0 | 0x2E)
#define ICM20648_REG_ACCEL_YOUT_H_SH ( ICM20648_BANK_0 | 0x2F)
#define ICM20648_REG_ACCEL_YOUT_L_SH ( ICM20648_BANK_0 | 0x30)
#define ICM20648_REG_ACCEL_ZOUT_H_SH ( ICM20648_BANK_0 | 0x31)
#define ICM20648_REG_ACCEL_ZOUT_L_SH ( ICM20648_BANK_0 | 0x32)
#define ICM20648_REG_GYRO_XOUT_H_SH ( ICM20648_BANK_0 | 0x33)
#define ICM20648_REG_GYRO_XOUT_L_SH ( ICM20648_BANK_0 | 0x34)
#define ICM20648_REG_GYRO_YOUT_H_SH ( ICM20648_BANK_0 | 0x35)
#define ICM20648_REG_GYRO_YOUT_L_SH ( ICM20648_BANK_0 | 0x36)
#define ICM20648_REG_GYRO_ZOUT_H_SH ( ICM20648_BANK_0 | 0x37)
#define ICM20648_REG_GYRO_ZOUT_L_SH ( ICM20648_BANK_0 | 0x38)
#define ICM20648_REG_TEMPERATURE_H ( ICM20648_BANK_0 | 0x39)
#define ICM20648_REG_TEMPERATURE_L ( ICM20648_BANK_0 | 0x3A)
#define ICM20648_REG_TEMP_CONFIG ( ICM20648_BANK_0 | 0x53)
#define ICM20648_REG_FIFO_EN_1 ( ICM20648_BANK_0 | 0x66)
#define ICM20648_REG_FIFO_EN_2 ( ICM20648_BANK_0 | 0x67)
#define ICM20648_BIT_ACCEL_FIFO_EN 0x10
#define ICM20648_BITS_GYRO_FIFO_EN 0x0E
#define ICM20648_REG_FIFO_RST ( ICM20648_BANK_0 | 0x68)
#define ICM20648_REG_FIFO_MODE ( ICM20648_BANK_0 | 0x69)
#define ICM20648_REG_FIFO_COUNT_H ( ICM20648_BANK_0 | 0x70)
#define ICM20648_REG_FIFO_COUNT_L ( ICM20648_BANK_0 | 0x71)
#define ICM20648_REG_FIFO_R_W ( ICM20648_BANK_0 | 0x72)
#define ICM20648_REG_DATA_RDY_STATUS ( ICM20648_BANK_0 | 0x74)
#define ICM20648_BIT_RAW_DATA_0_RDY 0x01
#define ICM20648_REG_FIFO_CFG ( ICM20648_BANK_0 | 0x76)
#define ICM20648_BIT_MULTI_FIFO_CFG 0x01
#define ICM20648_BIT_SINGLE_FIFO_CFG 0x00
#define ICM20648_REG_XA_OFFSET_H ( ICM20648_BANK_1 | 0x14)
#define ICM20648_REG_XA_OFFSET_L ( ICM20648_BANK_1 | 0x15)
#define ICM20648_REG_YA_OFFSET_H ( ICM20648_BANK_1 | 0x17)
#define ICM20648_REG_YA_OFFSET_L ( ICM20648_BANK_1 | 0x18)
#define ICM20648_REG_ZA_OFFSET_H ( ICM20648_BANK_1 | 0x1A)
#define ICM20648_REG_ZA_OFFSET_L ( ICM20648_BANK_1 | 0x1B)
#define ICM20648_REG_TIMEBASE_CORR_PLL ( ICM20648_BANK_1 | 0x28)
#define ICM20648_REG_GYRO_SMPLRT_DIV ( ICM20648_BANK_2 | 0x00)
#define ICM20648_REG_GYRO_CONFIG_1 ( ICM20648_BANK_2 | 0x01)
#define ICM20648_BIT_GYRO_FCHOICE 0x01
#define ICM20648_SHIFT_GYRO_FS_SEL 1
#define ICM20648_SHIFT_GYRO_DLPCFG 3
#define ICM20648_MASK_GYRO_FULLSCALE 0x06
#define ICM20648_MASK_GYRO_BW 0x39
#define ICM20648_GYRO_FULLSCALE_250DPS (0x00 << ICM20648_SHIFT_GYRO_FS_SEL)
#define ICM20648_GYRO_FULLSCALE_500DPS (0x01 << ICM20648_SHIFT_GYRO_FS_SEL)
#define ICM20648_GYRO_FULLSCALE_1000DPS (0x02 << ICM20648_SHIFT_GYRO_FS_SEL)
#define ICM20648_GYRO_FULLSCALE_2000DPS (0x03 << ICM20648_SHIFT_GYRO_FS_SEL)
#define ICM20648_GYRO_BW_12100HZ (0x00 << ICM20648_SHIFT_GYRO_DLPCFG)
#define ICM20648_GYRO_BW_360HZ ( (0x07 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)
#define ICM20648_GYRO_BW_200HZ ( (0x00 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)
#define ICM20648_GYRO_BW_150HZ ( (0x01 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)
#define ICM20648_GYRO_BW_120HZ ( (0x02 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)
#define ICM20648_GYRO_BW_51HZ ( (0x03 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)
#define ICM20648_GYRO_BW_24HZ ( (0x04 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)
#define ICM20648_GYRO_BW_12HZ ( (0x05 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)
#define ICM20648_GYRO_BW_6HZ ( (0x06 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)
#define ICM20648_REG_GYRO_CONFIG_2 ( ICM20648_BANK_2 | 0x02)
#define ICM20648_BIT_GYRO_CTEN 0x38
#define ICM20648_REG_XG_OFFS_USRH ( ICM20648_BANK_2 | 0x03)
#define ICM20648_REG_XG_OFFS_USRL ( ICM20648_BANK_2 | 0x04)
#define ICM20648_REG_YG_OFFS_USRH ( ICM20648_BANK_2 | 0x05)
#define ICM20648_REG_YG_OFFS_USRL ( ICM20648_BANK_2 | 0x06)
#define ICM20648_REG_ZG_OFFS_USRH ( ICM20648_BANK_2 | 0x07)
#define ICM20648_REG_ZG_OFFS_USRL ( ICM20648_BANK_2 | 0x08)
#define ICM20648_REG_ODR_ALIGN_EN ( ICM20648_BANK_2 | 0x09)
#define ICM20648_REG_ACCEL_SMPLRT_DIV_1 ( ICM20648_BANK_2 | 0x10)
#define ICM20648_REG_ACCEL_SMPLRT_DIV_2 ( ICM20648_BANK_2 | 0x11)
#define ICM20648_REG_ACCEL_INTEL_CTRL ( ICM20648_BANK_2 | 0x12)
#define ICM20648_BIT_ACCEL_INTEL_EN 0x02
#define ICM20648_BIT_ACCEL_INTEL_MODE 0x01
#define ICM20648_REG_ACCEL_WOM_THR ( ICM20648_BANK_2 | 0x13)
#define ICM20648_REG_ACCEL_CONFIG ( ICM20648_BANK_2 | 0x14)
#define ICM20648_BIT_ACCEL_FCHOICE 0x01
#define ICM20648_SHIFT_ACCEL_FS 1
#define ICM20648_SHIFT_ACCEL_DLPCFG 3
#define ICM20648_MASK_ACCEL_FULLSCALE 0x06
#define ICM20648_MASK_ACCEL_BW 0x39
#define ICM20648_ACCEL_FULLSCALE_2G (0x00 << ICM20648_SHIFT_ACCEL_FS)
#define ICM20648_ACCEL_FULLSCALE_4G (0x01 << ICM20648_SHIFT_ACCEL_FS)
#define ICM20648_ACCEL_FULLSCALE_8G (0x02 << ICM20648_SHIFT_ACCEL_FS)
#define ICM20648_ACCEL_FULLSCALE_16G (0x03 << ICM20648_SHIFT_ACCEL_FS)
#define ICM20648_ACCEL_BW_1210HZ (0x00 << ICM20648_SHIFT_ACCEL_DLPCFG)
#define ICM20648_ACCEL_BW_470HZ ( (0x07 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)
#define ICM20648_ACCEL_BW_246HZ ( (0x00 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)
#define ICM20648_ACCEL_BW_111HZ ( (0x02 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)
#define ICM20648_ACCEL_BW_50HZ ( (0x03 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)
#define ICM20648_ACCEL_BW_24HZ ( (0x04 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)
#define ICM20648_ACCEL_BW_12HZ ( (0x05 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)
#define ICM20648_ACCEL_BW_6HZ ( (0x06 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)
#define ICM20648_REG_ACCEL_CONFIG_2 ( ICM20648_BANK_2 | 0x15)
#define ICM20648_BIT_ACCEL_CTEN 0x1C
#define ICM20648_REG_I2C_MST_ODR_CONFIG ( ICM20648_BANK_3 | 0x00)
#define ICM20648_REG_I2C_MST_CTRL ( ICM20648_BANK_3 | 0x01)
#define ICM20648_BIT_I2C_MST_P_NSR 0x10
#define ICM20648_REG_I2C_MST_DELAY_CTRL ( ICM20648_BANK_3 | 0x02)
#define ICM20648_BIT_SLV0_DLY_EN 0x01
#define ICM20648_BIT_SLV1_DLY_EN 0x02
#define ICM20648_BIT_SLV2_DLY_EN 0x04
#define ICM20648_BIT_SLV3_DLY_EN 0x08
#define ICM20648_REG_I2C_SLV0_ADDR ( ICM20648_BANK_3 | 0x03)
#define ICM20648_REG_I2C_SLV0_REG ( ICM20648_BANK_3 | 0x04)
#define ICM20648_REG_I2C_SLV0_CTRL ( ICM20648_BANK_3 | 0x05)
#define ICM20648_REG_I2C_SLV0_DO ( ICM20648_BANK_3 | 0x06)
#define ICM20648_REG_I2C_SLV1_ADDR ( ICM20648_BANK_3 | 0x07)
#define ICM20648_REG_I2C_SLV1_REG ( ICM20648_BANK_3 | 0x08)
#define ICM20648_REG_I2C_SLV1_CTRL ( ICM20648_BANK_3 | 0x09)
#define ICM20648_REG_I2C_SLV1_DO ( ICM20648_BANK_3 | 0x0A)
#define ICM20648_REG_I2C_SLV2_ADDR ( ICM20648_BANK_3 | 0x0B)
#define ICM20648_REG_I2C_SLV2_REG ( ICM20648_BANK_3 | 0x0C)
#define ICM20648_REG_I2C_SLV2_CTRL ( ICM20648_BANK_3 | 0x0D)
#define ICM20648_REG_I2C_SLV2_DO ( ICM20648_BANK_3 | 0x0E)
#define ICM20648_REG_I2C_SLV3_ADDR ( ICM20648_BANK_3 | 0x0F)
#define ICM20648_REG_I2C_SLV3_REG ( ICM20648_BANK_3 | 0x10)
#define ICM20648_REG_I2C_SLV3_CTRL ( ICM20648_BANK_3 | 0x11)
#define ICM20648_REG_I2C_SLV3_DO ( ICM20648_BANK_3 | 0x12)
#define ICM20648_REG_I2C_SLV4_ADDR ( ICM20648_BANK_3 | 0x13)
#define ICM20648_REG_I2C_SLV4_REG ( ICM20648_BANK_3 | 0x14)
#define ICM20648_REG_I2C_SLV4_CTRL ( ICM20648_BANK_3 | 0x15)
#define ICM20648_REG_I2C_SLV4_DO ( ICM20648_BANK_3 | 0x16)
#define ICM20648_REG_I2C_SLV4_DI ( ICM20648_BANK_3 | 0x17)
#define ICM20648_BIT_I2C_SLV_EN 0x80
#define ICM20648_BIT_I2C_BYTE_SW 0x40
#define ICM20648_BIT_I2C_REG_DIS 0x20
#define ICM20648_BIT_I2C_GRP 0x10
#define ICM20648_BIT_I2C_READ 0x80
#define ICM20648_REG_BANK_SEL 0x7F
#define ICM20648_DEVICE_ID 0xE0
#define ICM20948_DEVICE_ID 0xEA

Functions

uint32_t ICM20648_accelBandwidthSet (uint8_t accelBw)
Sets the bandwidth of the accelerometer.
uint32_t ICM20648_accelDataRead (float *accel)
Reads the raw acceleration value and converts to g value based on the actual resolution.
uint32_t ICM20648_accelFullscaleSet (uint8_t accelFs)
Sets the full scale value of the accelerometer.
uint32_t ICM20648_accelGyroCalibrate (float *accelBiasScaled, float *gyroBiasScaled)
Accelerometer and gyroscope calibration function. Reads the gyroscope and accelerometer values while the device is at rest and in level. The resulting values are loaded to the accel and gyro bias registers to cancel the static offset error.
uint32_t ICM20648_accelResolutionGet (float *accelRes)
Gets the actual resolution of the accelerometer.
float ICM20648_accelSampleRateSet (float sampleRate)
Sets the sample rate of the gyroscope.
void ICM20648_bankSelect (uint8_t bank)
Select the desired register bank.
uint32_t ICM20648_cycleModeEnable (bool enable)
Enables or disables the cycle mode operation of the accel and gyro.
uint32_t ICM20648_deInit (void)
De-initializes the ICM20648 sensor by disconnecting the supply and SPI lines.
uint32_t ICM20648_getDeviceID (uint8_t *devID)
Reads the device ID of the ICM20648.
uint32_t ICM20648_gyroBandwidthSet (uint8_t gyroBw)
Sets the bandwidth of the gyroscope.
uint32_t ICM20648_gyroCalibrate (float *gyroBiasScaled)
Gyroscope calibration function. Reads the gyroscope values while the device is at rest and in level. The resulting values are loaded to the gyro bias registers to cancel the static offset error.
uint32_t ICM20648_gyroDataRead (float *gyro)
Reads the raw gyroscope value and converts to deg/sec value based on the actual resolution.
uint32_t ICM20648_gyroFullscaleSet (uint8_t gyroFs)
Sets the full scale value of the gyroscope.
uint32_t ICM20648_gyroResolutionGet (float *gyroRes)
Gets the actual resolution of the gyroscope.
float ICM20648_gyroSampleRateSet (float sampleRate)
Sets the sample rate of the accelerometer.
uint32_t ICM20648_init (void)
Initializes the ICM20648 sensor. Enables the power supply and SPI lines, sets up the host SPI controller, configures the chip control interface, clock generator and interrupt line.
uint32_t ICM20648_interruptEnable (bool dataReadyEnable, bool womEnable)
Enables or disables the interrupts in the ICM20648 chip.
uint32_t ICM20648_interruptStatusRead (uint32_t *intStatus)
Reads the interrupt status registers of the ICM20648 chip.
bool ICM20648_isDataReady (void)
Checks if new data is available for read.
uint32_t ICM20648_lowPowerModeEnter (bool enAccel, bool enGyro, bool enTemp)
Enables or disables the sensors in low power mode in the ICM20648 chip.
void ICM20648_registerRead (uint16_t addr, int numBytes, uint8_t *data)
Reads register from the ICM20648 device.
void ICM20648_registerWrite (uint16_t addr, uint8_t data)
Writes a register in the ICM20648 device.
uint32_t ICM20648_reset (void)
Performs soft reset on the ICM20648 chip.
uint32_t ICM20648_sampleRateSet (float sampleRate)
Sets the sample rate both of the accelerometer and the gyroscope.
uint32_t ICM20648_sensorEnable (bool accel, bool gyro, bool temp)
Enables or disables the sensors in the ICM20648 chip.
uint32_t ICM20648_sleepModeEnable (bool enable)
Enables or disables the sleep mode of the device.
uint32_t ICM20648_spiInit (void)
Initializes the SPI bus in order to communicate with the ICM20648.
uint32_t ICM20648_temperatureRead (float *temperature)
Reads the temperature sensor raw value and converts to Celsius.
uint32_t ICM20648_wakeOnMotionITEnable (bool enable, uint8_t womThreshold, float sampleRate)
Sets up and enables the Wake-up On Motion feature.