Macros
#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL

#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL

#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0

#define	_DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL

#define	_DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL

#define	_DMA_CH_CTRL_MASK 0x003F000FUL

#define	_DMA_CH_CTRL_RESETVALUE 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL

#define	_DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_MASK 0xFUL

#define	_DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_SHIFT 0

#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_UART0TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL

#define	_DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL

#define	_DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL

#define	_DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL

#define	_DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL

#define	_DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL

#define	_DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL

#define	_DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL

#define	_DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL

#define	_DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL

#define	_DMA_CH_CTRL_SOURCESEL_SHIFT 16

#define	_DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL

#define	_DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL

#define	_DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL

#define	_DMA_CH_CTRL_SOURCESEL_UART0 0x0000002CUL

#define	_DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL

#define	_DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL

#define	_DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL

#define	_DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH0ALTC_MASK 0x1UL

#define	_DMA_CHALTC_CH0ALTC_SHIFT 0

#define	_DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH1ALTC_MASK 0x2UL

#define	_DMA_CHALTC_CH1ALTC_SHIFT 1

#define	_DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH2ALTC_MASK 0x4UL

#define	_DMA_CHALTC_CH2ALTC_SHIFT 2

#define	_DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH3ALTC_MASK 0x8UL

#define	_DMA_CHALTC_CH3ALTC_SHIFT 3

#define	_DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH4ALTC_MASK 0x10UL

#define	_DMA_CHALTC_CH4ALTC_SHIFT 4

#define	_DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH5ALTC_MASK 0x20UL

#define	_DMA_CHALTC_CH5ALTC_SHIFT 5

#define	_DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH6ALTC_MASK 0x40UL

#define	_DMA_CHALTC_CH6ALTC_SHIFT 6

#define	_DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH7ALTC_MASK 0x80UL

#define	_DMA_CHALTC_CH7ALTC_SHIFT 7

#define	_DMA_CHALTC_MASK 0x000000FFUL

#define	_DMA_CHALTC_RESETVALUE 0x00000000UL

#define	_DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH0ALTS_MASK 0x1UL

#define	_DMA_CHALTS_CH0ALTS_SHIFT 0

#define	_DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH1ALTS_MASK 0x2UL

#define	_DMA_CHALTS_CH1ALTS_SHIFT 1

#define	_DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH2ALTS_MASK 0x4UL

#define	_DMA_CHALTS_CH2ALTS_SHIFT 2

#define	_DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH3ALTS_MASK 0x8UL

#define	_DMA_CHALTS_CH3ALTS_SHIFT 3

#define	_DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH4ALTS_MASK 0x10UL

#define	_DMA_CHALTS_CH4ALTS_SHIFT 4

#define	_DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH5ALTS_MASK 0x20UL

#define	_DMA_CHALTS_CH5ALTS_SHIFT 5

#define	_DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH6ALTS_MASK 0x40UL

#define	_DMA_CHALTS_CH6ALTS_SHIFT 6

#define	_DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH7ALTS_MASK 0x80UL

#define	_DMA_CHALTS_CH7ALTS_SHIFT 7

#define	_DMA_CHALTS_MASK 0x000000FFUL

#define	_DMA_CHALTS_RESETVALUE 0x00000000UL

#define	_DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH0ENC_MASK 0x1UL

#define	_DMA_CHENC_CH0ENC_SHIFT 0

#define	_DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH1ENC_MASK 0x2UL

#define	_DMA_CHENC_CH1ENC_SHIFT 1

#define	_DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH2ENC_MASK 0x4UL

#define	_DMA_CHENC_CH2ENC_SHIFT 2

#define	_DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH3ENC_MASK 0x8UL

#define	_DMA_CHENC_CH3ENC_SHIFT 3

#define	_DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH4ENC_MASK 0x10UL

#define	_DMA_CHENC_CH4ENC_SHIFT 4

#define	_DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH5ENC_MASK 0x20UL

#define	_DMA_CHENC_CH5ENC_SHIFT 5

#define	_DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH6ENC_MASK 0x40UL

#define	_DMA_CHENC_CH6ENC_SHIFT 6

#define	_DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH7ENC_MASK 0x80UL

#define	_DMA_CHENC_CH7ENC_SHIFT 7

#define	_DMA_CHENC_MASK 0x000000FFUL

#define	_DMA_CHENC_RESETVALUE 0x00000000UL

#define	_DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH0ENS_MASK 0x1UL

#define	_DMA_CHENS_CH0ENS_SHIFT 0

#define	_DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH1ENS_MASK 0x2UL

#define	_DMA_CHENS_CH1ENS_SHIFT 1

#define	_DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH2ENS_MASK 0x4UL

#define	_DMA_CHENS_CH2ENS_SHIFT 2

#define	_DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH3ENS_MASK 0x8UL

#define	_DMA_CHENS_CH3ENS_SHIFT 3

#define	_DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH4ENS_MASK 0x10UL

#define	_DMA_CHENS_CH4ENS_SHIFT 4

#define	_DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH5ENS_MASK 0x20UL

#define	_DMA_CHENS_CH5ENS_SHIFT 5

#define	_DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH6ENS_MASK 0x40UL

#define	_DMA_CHENS_CH6ENS_SHIFT 6

#define	_DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH7ENS_MASK 0x80UL

#define	_DMA_CHENS_CH7ENS_SHIFT 7

#define	_DMA_CHENS_MASK 0x000000FFUL

#define	_DMA_CHENS_RESETVALUE 0x00000000UL

#define	_DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH0PRIC_MASK 0x1UL

#define	_DMA_CHPRIC_CH0PRIC_SHIFT 0

#define	_DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH1PRIC_MASK 0x2UL

#define	_DMA_CHPRIC_CH1PRIC_SHIFT 1

#define	_DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH2PRIC_MASK 0x4UL

#define	_DMA_CHPRIC_CH2PRIC_SHIFT 2

#define	_DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH3PRIC_MASK 0x8UL

#define	_DMA_CHPRIC_CH3PRIC_SHIFT 3

#define	_DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH4PRIC_MASK 0x10UL

#define	_DMA_CHPRIC_CH4PRIC_SHIFT 4

#define	_DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH5PRIC_MASK 0x20UL

#define	_DMA_CHPRIC_CH5PRIC_SHIFT 5

#define	_DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH6PRIC_MASK 0x40UL

#define	_DMA_CHPRIC_CH6PRIC_SHIFT 6

#define	_DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH7PRIC_MASK 0x80UL

#define	_DMA_CHPRIC_CH7PRIC_SHIFT 7

#define	_DMA_CHPRIC_MASK 0x000000FFUL

#define	_DMA_CHPRIC_RESETVALUE 0x00000000UL

#define	_DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH0PRIS_MASK 0x1UL

#define	_DMA_CHPRIS_CH0PRIS_SHIFT 0

#define	_DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH1PRIS_MASK 0x2UL

#define	_DMA_CHPRIS_CH1PRIS_SHIFT 1

#define	_DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH2PRIS_MASK 0x4UL

#define	_DMA_CHPRIS_CH2PRIS_SHIFT 2

#define	_DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH3PRIS_MASK 0x8UL

#define	_DMA_CHPRIS_CH3PRIS_SHIFT 3

#define	_DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH4PRIS_MASK 0x10UL

#define	_DMA_CHPRIS_CH4PRIS_SHIFT 4

#define	_DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH5PRIS_MASK 0x20UL

#define	_DMA_CHPRIS_CH5PRIS_SHIFT 5

#define	_DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH6PRIS_MASK 0x40UL

#define	_DMA_CHPRIS_CH6PRIS_SHIFT 6

#define	_DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH7PRIS_MASK 0x80UL

#define	_DMA_CHPRIS_CH7PRIS_SHIFT 7

#define	_DMA_CHPRIS_MASK 0x000000FFUL

#define	_DMA_CHPRIS_RESETVALUE 0x00000000UL

#define	_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL

#define	_DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0

#define	_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL

#define	_DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1

#define	_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL

#define	_DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2

#define	_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL

#define	_DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3

#define	_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL

#define	_DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4

#define	_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL

#define	_DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5

#define	_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL

#define	_DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6

#define	_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL

#define	_DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7

#define	_DMA_CHREQMASKC_MASK 0x000000FFUL

#define	_DMA_CHREQMASKC_RESETVALUE 0x00000000UL

#define	_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL

#define	_DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0

#define	_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL

#define	_DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1

#define	_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL

#define	_DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2

#define	_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL

#define	_DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3

#define	_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL

#define	_DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4

#define	_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL

#define	_DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5

#define	_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL

#define	_DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6

#define	_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL

#define	_DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7

#define	_DMA_CHREQMASKS_MASK 0x000000FFUL

#define	_DMA_CHREQMASKS_RESETVALUE 0x00000000UL

#define	_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL

#define	_DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0

#define	_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL

#define	_DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1

#define	_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL

#define	_DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2

#define	_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL

#define	_DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3

#define	_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL

#define	_DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4

#define	_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL

#define	_DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5

#define	_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL

#define	_DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6

#define	_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL

#define	_DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7

#define	_DMA_CHREQSTATUS_MASK 0x000000FFUL

#define	_DMA_CHREQSTATUS_RESETVALUE 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL

#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0

#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL

#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1

#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL

#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2

#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL

#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3

#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL

#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4

#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL

#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5

#define	_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL

#define	_DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6

#define	_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL

#define	_DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7

#define	_DMA_CHSREQSTATUS_MASK 0x000000FFUL

#define	_DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL

#define	_DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL

#define	_DMA_CHSWREQ_CH0SWREQ_SHIFT 0

#define	_DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL

#define	_DMA_CHSWREQ_CH1SWREQ_SHIFT 1

#define	_DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL

#define	_DMA_CHSWREQ_CH2SWREQ_SHIFT 2

#define	_DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL

#define	_DMA_CHSWREQ_CH3SWREQ_SHIFT 3

#define	_DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL

#define	_DMA_CHSWREQ_CH4SWREQ_SHIFT 4

#define	_DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL

#define	_DMA_CHSWREQ_CH5SWREQ_SHIFT 5

#define	_DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL

#define	_DMA_CHSWREQ_CH6SWREQ_SHIFT 6

#define	_DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL

#define	_DMA_CHSWREQ_CH7SWREQ_SHIFT 7

#define	_DMA_CHSWREQ_MASK 0x000000FFUL

#define	_DMA_CHSWREQ_RESETVALUE 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL

#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0

#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL

#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1

#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL

#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2

#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL

#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3

#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL

#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4

#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL

#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5

#define	_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL

#define	_DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6

#define	_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL

#define	_DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7

#define	_DMA_CHUSEBURSTC_MASK 0x000000FFUL

#define	_DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL

#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1

#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL

#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2

#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL

#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3

#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL

#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4

#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL

#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5

#define	_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL

#define	_DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6

#define	_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL

#define	_DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7

#define	_DMA_CHUSEBURSTS_MASK 0x000000FFUL

#define	_DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL

#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL

#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0

#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL

#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1

#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL

#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2

#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL

#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3

#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL

#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4

#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL

#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5

#define	_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL

#define	_DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6

#define	_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL

#define	_DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7

#define	_DMA_CHWAITSTATUS_MASK 0x000000FFUL

#define	_DMA_CHWAITSTATUS_RESETVALUE 0x000000FFUL

#define	_DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL

#define	_DMA_CONFIG_CHPROT_MASK 0x20UL

#define	_DMA_CONFIG_CHPROT_SHIFT 5

#define	_DMA_CONFIG_EN_DEFAULT 0x00000000UL

#define	_DMA_CONFIG_EN_MASK 0x1UL

#define	_DMA_CONFIG_EN_SHIFT 0

#define	_DMA_CONFIG_MASK 0x00000021UL

#define	_DMA_CONFIG_RESETVALUE 0x00000000UL

#define	_DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL

#define	_DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL

#define	_DMA_CTRLBASE_CTRLBASE_SHIFT 0

#define	_DMA_CTRLBASE_MASK 0xFFFFFFFFUL

#define	_DMA_CTRLBASE_RESETVALUE 0x00000000UL

#define	_DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL

#define	_DMA_ERRORC_ERRORC_MASK 0x1UL

#define	_DMA_ERRORC_ERRORC_SHIFT 0

#define	_DMA_ERRORC_MASK 0x00000001UL

#define	_DMA_ERRORC_RESETVALUE 0x00000000UL

#define	_DMA_IEN_CH0DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH0DONE_MASK 0x1UL

#define	_DMA_IEN_CH0DONE_SHIFT 0

#define	_DMA_IEN_CH1DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH1DONE_MASK 0x2UL

#define	_DMA_IEN_CH1DONE_SHIFT 1

#define	_DMA_IEN_CH2DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH2DONE_MASK 0x4UL

#define	_DMA_IEN_CH2DONE_SHIFT 2

#define	_DMA_IEN_CH3DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH3DONE_MASK 0x8UL

#define	_DMA_IEN_CH3DONE_SHIFT 3

#define	_DMA_IEN_CH4DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH4DONE_MASK 0x10UL

#define	_DMA_IEN_CH4DONE_SHIFT 4

#define	_DMA_IEN_CH5DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH5DONE_MASK 0x20UL

#define	_DMA_IEN_CH5DONE_SHIFT 5

#define	_DMA_IEN_CH6DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH6DONE_MASK 0x40UL

#define	_DMA_IEN_CH6DONE_SHIFT 6

#define	_DMA_IEN_CH7DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH7DONE_MASK 0x80UL

#define	_DMA_IEN_CH7DONE_SHIFT 7

#define	_DMA_IEN_ERR_DEFAULT 0x00000000UL

#define	_DMA_IEN_ERR_MASK 0x80000000UL

#define	_DMA_IEN_ERR_SHIFT 31

#define	_DMA_IEN_MASK 0x800000FFUL

#define	_DMA_IEN_RESETVALUE 0x00000000UL

#define	_DMA_IF_CH0DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH0DONE_MASK 0x1UL

#define	_DMA_IF_CH0DONE_SHIFT 0

#define	_DMA_IF_CH1DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH1DONE_MASK 0x2UL

#define	_DMA_IF_CH1DONE_SHIFT 1

#define	_DMA_IF_CH2DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH2DONE_MASK 0x4UL

#define	_DMA_IF_CH2DONE_SHIFT 2

#define	_DMA_IF_CH3DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH3DONE_MASK 0x8UL

#define	_DMA_IF_CH3DONE_SHIFT 3

#define	_DMA_IF_CH4DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH4DONE_MASK 0x10UL

#define	_DMA_IF_CH4DONE_SHIFT 4

#define	_DMA_IF_CH5DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH5DONE_MASK 0x20UL

#define	_DMA_IF_CH5DONE_SHIFT 5

#define	_DMA_IF_CH6DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH6DONE_MASK 0x40UL

#define	_DMA_IF_CH6DONE_SHIFT 6

#define	_DMA_IF_CH7DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH7DONE_MASK 0x80UL

#define	_DMA_IF_CH7DONE_SHIFT 7

#define	_DMA_IF_ERR_DEFAULT 0x00000000UL

#define	_DMA_IF_ERR_MASK 0x80000000UL

#define	_DMA_IF_ERR_SHIFT 31

#define	_DMA_IF_MASK 0x800000FFUL

#define	_DMA_IF_RESETVALUE 0x00000000UL

#define	_DMA_IFC_CH0DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH0DONE_MASK 0x1UL

#define	_DMA_IFC_CH0DONE_SHIFT 0

#define	_DMA_IFC_CH1DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH1DONE_MASK 0x2UL

#define	_DMA_IFC_CH1DONE_SHIFT 1

#define	_DMA_IFC_CH2DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH2DONE_MASK 0x4UL

#define	_DMA_IFC_CH2DONE_SHIFT 2

#define	_DMA_IFC_CH3DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH3DONE_MASK 0x8UL

#define	_DMA_IFC_CH3DONE_SHIFT 3

#define	_DMA_IFC_CH4DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH4DONE_MASK 0x10UL

#define	_DMA_IFC_CH4DONE_SHIFT 4

#define	_DMA_IFC_CH5DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH5DONE_MASK 0x20UL

#define	_DMA_IFC_CH5DONE_SHIFT 5

#define	_DMA_IFC_CH6DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH6DONE_MASK 0x40UL

#define	_DMA_IFC_CH6DONE_SHIFT 6

#define	_DMA_IFC_CH7DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH7DONE_MASK 0x80UL

#define	_DMA_IFC_CH7DONE_SHIFT 7

#define	_DMA_IFC_ERR_DEFAULT 0x00000000UL

#define	_DMA_IFC_ERR_MASK 0x80000000UL

#define	_DMA_IFC_ERR_SHIFT 31

#define	_DMA_IFC_MASK 0x800000FFUL

#define	_DMA_IFC_RESETVALUE 0x00000000UL

#define	_DMA_IFS_CH0DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH0DONE_MASK 0x1UL

#define	_DMA_IFS_CH0DONE_SHIFT 0

#define	_DMA_IFS_CH1DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH1DONE_MASK 0x2UL

#define	_DMA_IFS_CH1DONE_SHIFT 1

#define	_DMA_IFS_CH2DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH2DONE_MASK 0x4UL

#define	_DMA_IFS_CH2DONE_SHIFT 2

#define	_DMA_IFS_CH3DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH3DONE_MASK 0x8UL

#define	_DMA_IFS_CH3DONE_SHIFT 3

#define	_DMA_IFS_CH4DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH4DONE_MASK 0x10UL

#define	_DMA_IFS_CH4DONE_SHIFT 4

#define	_DMA_IFS_CH5DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH5DONE_MASK 0x20UL

#define	_DMA_IFS_CH5DONE_SHIFT 5

#define	_DMA_IFS_CH6DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH6DONE_MASK 0x40UL

#define	_DMA_IFS_CH6DONE_SHIFT 6

#define	_DMA_IFS_CH7DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH7DONE_MASK 0x80UL

#define	_DMA_IFS_CH7DONE_SHIFT 7

#define	_DMA_IFS_ERR_DEFAULT 0x00000000UL

#define	_DMA_IFS_ERR_MASK 0x80000000UL

#define	_DMA_IFS_ERR_SHIFT 31

#define	_DMA_IFS_MASK 0x800000FFUL

#define	_DMA_IFS_RESETVALUE 0x00000000UL

#define	_DMA_STATUS_CHNUM_DEFAULT 0x00000007UL

#define	_DMA_STATUS_CHNUM_MASK 0x1F0000UL

#define	_DMA_STATUS_CHNUM_SHIFT 16

#define	_DMA_STATUS_EN_DEFAULT 0x00000000UL

#define	_DMA_STATUS_EN_MASK 0x1UL

#define	_DMA_STATUS_EN_SHIFT 0

#define	_DMA_STATUS_MASK 0x001F00F1UL

#define	_DMA_STATUS_RESETVALUE 0x10070000UL

#define	_DMA_STATUS_STATE_DEFAULT 0x00000000UL

#define	_DMA_STATUS_STATE_DONE 0x00000009UL

#define	_DMA_STATUS_STATE_IDLE 0x00000000UL

#define	_DMA_STATUS_STATE_MASK 0xF0UL

#define	_DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL

#define	_DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL

#define	_DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL

#define	_DMA_STATUS_STATE_RDSRCDATA 0x00000004UL

#define	_DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL

#define	_DMA_STATUS_STATE_SHIFT 4

#define	_DMA_STATUS_STATE_STALLED 0x00000008UL

#define	_DMA_STATUS_STATE_WAITREQCLR 0x00000006UL

#define	_DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL

#define	_DMA_STATUS_STATE_WRDSTDATA 0x00000005UL

#define	DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT ( _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)

#define	DMA_CH_CTRL_SIGSEL_ADC0SCAN ( _DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)

#define	DMA_CH_CTRL_SIGSEL_ADC0SINGLE ( _DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)

#define	DMA_CH_CTRL_SIGSEL_AESDATARD ( _DMA_CH_CTRL_SIGSEL_AESDATARD << 0)

#define	DMA_CH_CTRL_SIGSEL_AESDATAWR ( _DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)

#define	DMA_CH_CTRL_SIGSEL_AESKEYWR ( _DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)

#define	DMA_CH_CTRL_SIGSEL_AESXORDATAWR ( _DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)

#define	DMA_CH_CTRL_SIGSEL_DAC0CH0 ( _DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0)

#define	DMA_CH_CTRL_SIGSEL_DAC0CH1 ( _DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0)

#define	DMA_CH_CTRL_SIGSEL_I2C0RXDATAV ( _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_I2C0TXBL ( _DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV ( _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_LEUART0TXBL ( _DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY ( _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)

#define	DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV ( _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_LEUART1TXBL ( _DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY ( _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0)

#define	DMA_CH_CTRL_SIGSEL_MSCWDATA ( _DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER0CC0 ( _DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER0CC1 ( _DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER0CC2 ( _DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER0UFOF ( _DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER1CC0 ( _DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER1CC1 ( _DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER1CC2 ( _DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER1UFOF ( _DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER2CC0 ( _DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER2CC1 ( _DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER2CC2 ( _DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER2UFOF ( _DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)

#define	DMA_CH_CTRL_SIGSEL_UART0RXDATAV ( _DMA_CH_CTRL_SIGSEL_UART0RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_UART0TXBL ( _DMA_CH_CTRL_SIGSEL_UART0TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_UART0TXEMPTY ( _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY << 0)

#define	DMA_CH_CTRL_SIGSEL_USART0RXDATAV ( _DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_USART0TXBL ( _DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_USART0TXEMPTY ( _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)

#define	DMA_CH_CTRL_SIGSEL_USART1RXDATAV ( _DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_USART1TXBL ( _DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_USART1TXEMPTY ( _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)

#define	DMA_CH_CTRL_SIGSEL_USART2RXDATAV ( _DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_USART2TXBL ( _DMA_CH_CTRL_SIGSEL_USART2TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_USART2TXEMPTY ( _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0)

#define	DMA_CH_CTRL_SOURCESEL_ADC0 ( _DMA_CH_CTRL_SOURCESEL_ADC0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_AES ( _DMA_CH_CTRL_SOURCESEL_AES << 16)

#define	DMA_CH_CTRL_SOURCESEL_DAC0 ( _DMA_CH_CTRL_SOURCESEL_DAC0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_I2C0 ( _DMA_CH_CTRL_SOURCESEL_I2C0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_LEUART0 ( _DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_LEUART1 ( _DMA_CH_CTRL_SOURCESEL_LEUART1 << 16)

#define	DMA_CH_CTRL_SOURCESEL_MSC ( _DMA_CH_CTRL_SOURCESEL_MSC << 16)

#define	DMA_CH_CTRL_SOURCESEL_NONE ( _DMA_CH_CTRL_SOURCESEL_NONE << 16)

#define	DMA_CH_CTRL_SOURCESEL_TIMER0 ( _DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_TIMER1 ( _DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)

#define	DMA_CH_CTRL_SOURCESEL_TIMER2 ( _DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)

#define	DMA_CH_CTRL_SOURCESEL_UART0 ( _DMA_CH_CTRL_SOURCESEL_UART0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_USART0 ( _DMA_CH_CTRL_SOURCESEL_USART0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_USART1 ( _DMA_CH_CTRL_SOURCESEL_USART1 << 16)

#define	DMA_CH_CTRL_SOURCESEL_USART2 ( _DMA_CH_CTRL_SOURCESEL_USART2 << 16)

#define	DMA_CHALTC_CH0ALTC (0x1UL << 0)

#define	DMA_CHALTC_CH0ALTC_DEFAULT ( _DMA_CHALTC_CH0ALTC_DEFAULT << 0)

#define	DMA_CHALTC_CH1ALTC (0x1UL << 1)

#define	DMA_CHALTC_CH1ALTC_DEFAULT ( _DMA_CHALTC_CH1ALTC_DEFAULT << 1)

#define	DMA_CHALTC_CH2ALTC (0x1UL << 2)

#define	DMA_CHALTC_CH2ALTC_DEFAULT ( _DMA_CHALTC_CH2ALTC_DEFAULT << 2)

#define	DMA_CHALTC_CH3ALTC (0x1UL << 3)

#define	DMA_CHALTC_CH3ALTC_DEFAULT ( _DMA_CHALTC_CH3ALTC_DEFAULT << 3)

#define	DMA_CHALTC_CH4ALTC (0x1UL << 4)

#define	DMA_CHALTC_CH4ALTC_DEFAULT ( _DMA_CHALTC_CH4ALTC_DEFAULT << 4)

#define	DMA_CHALTC_CH5ALTC (0x1UL << 5)

#define	DMA_CHALTC_CH5ALTC_DEFAULT ( _DMA_CHALTC_CH5ALTC_DEFAULT << 5)

#define	DMA_CHALTC_CH6ALTC (0x1UL << 6)

#define	DMA_CHALTC_CH6ALTC_DEFAULT ( _DMA_CHALTC_CH6ALTC_DEFAULT << 6)

#define	DMA_CHALTC_CH7ALTC (0x1UL << 7)

#define	DMA_CHALTC_CH7ALTC_DEFAULT ( _DMA_CHALTC_CH7ALTC_DEFAULT << 7)

#define	DMA_CHALTS_CH0ALTS (0x1UL << 0)

#define	DMA_CHALTS_CH0ALTS_DEFAULT ( _DMA_CHALTS_CH0ALTS_DEFAULT << 0)

#define	DMA_CHALTS_CH1ALTS (0x1UL << 1)

#define	DMA_CHALTS_CH1ALTS_DEFAULT ( _DMA_CHALTS_CH1ALTS_DEFAULT << 1)

#define	DMA_CHALTS_CH2ALTS (0x1UL << 2)

#define	DMA_CHALTS_CH2ALTS_DEFAULT ( _DMA_CHALTS_CH2ALTS_DEFAULT << 2)

#define	DMA_CHALTS_CH3ALTS (0x1UL << 3)

#define	DMA_CHALTS_CH3ALTS_DEFAULT ( _DMA_CHALTS_CH3ALTS_DEFAULT << 3)

#define	DMA_CHALTS_CH4ALTS (0x1UL << 4)

#define	DMA_CHALTS_CH4ALTS_DEFAULT ( _DMA_CHALTS_CH4ALTS_DEFAULT << 4)

#define	DMA_CHALTS_CH5ALTS (0x1UL << 5)

#define	DMA_CHALTS_CH5ALTS_DEFAULT ( _DMA_CHALTS_CH5ALTS_DEFAULT << 5)

#define	DMA_CHALTS_CH6ALTS (0x1UL << 6)

#define	DMA_CHALTS_CH6ALTS_DEFAULT ( _DMA_CHALTS_CH6ALTS_DEFAULT << 6)

#define	DMA_CHALTS_CH7ALTS (0x1UL << 7)

#define	DMA_CHALTS_CH7ALTS_DEFAULT ( _DMA_CHALTS_CH7ALTS_DEFAULT << 7)

#define	DMA_CHENC_CH0ENC (0x1UL << 0)

#define	DMA_CHENC_CH0ENC_DEFAULT ( _DMA_CHENC_CH0ENC_DEFAULT << 0)

#define	DMA_CHENC_CH1ENC (0x1UL << 1)

#define	DMA_CHENC_CH1ENC_DEFAULT ( _DMA_CHENC_CH1ENC_DEFAULT << 1)

#define	DMA_CHENC_CH2ENC (0x1UL << 2)

#define	DMA_CHENC_CH2ENC_DEFAULT ( _DMA_CHENC_CH2ENC_DEFAULT << 2)

#define	DMA_CHENC_CH3ENC (0x1UL << 3)

#define	DMA_CHENC_CH3ENC_DEFAULT ( _DMA_CHENC_CH3ENC_DEFAULT << 3)

#define	DMA_CHENC_CH4ENC (0x1UL << 4)

#define	DMA_CHENC_CH4ENC_DEFAULT ( _DMA_CHENC_CH4ENC_DEFAULT << 4)

#define	DMA_CHENC_CH5ENC (0x1UL << 5)

#define	DMA_CHENC_CH5ENC_DEFAULT ( _DMA_CHENC_CH5ENC_DEFAULT << 5)

#define	DMA_CHENC_CH6ENC (0x1UL << 6)

#define	DMA_CHENC_CH6ENC_DEFAULT ( _DMA_CHENC_CH6ENC_DEFAULT << 6)

#define	DMA_CHENC_CH7ENC (0x1UL << 7)

#define	DMA_CHENC_CH7ENC_DEFAULT ( _DMA_CHENC_CH7ENC_DEFAULT << 7)

#define	DMA_CHENS_CH0ENS (0x1UL << 0)

#define	DMA_CHENS_CH0ENS_DEFAULT ( _DMA_CHENS_CH0ENS_DEFAULT << 0)

#define	DMA_CHENS_CH1ENS (0x1UL << 1)

#define	DMA_CHENS_CH1ENS_DEFAULT ( _DMA_CHENS_CH1ENS_DEFAULT << 1)

#define	DMA_CHENS_CH2ENS (0x1UL << 2)

#define	DMA_CHENS_CH2ENS_DEFAULT ( _DMA_CHENS_CH2ENS_DEFAULT << 2)

#define	DMA_CHENS_CH3ENS (0x1UL << 3)

#define	DMA_CHENS_CH3ENS_DEFAULT ( _DMA_CHENS_CH3ENS_DEFAULT << 3)

#define	DMA_CHENS_CH4ENS (0x1UL << 4)

#define	DMA_CHENS_CH4ENS_DEFAULT ( _DMA_CHENS_CH4ENS_DEFAULT << 4)

#define	DMA_CHENS_CH5ENS (0x1UL << 5)

#define	DMA_CHENS_CH5ENS_DEFAULT ( _DMA_CHENS_CH5ENS_DEFAULT << 5)

#define	DMA_CHENS_CH6ENS (0x1UL << 6)

#define	DMA_CHENS_CH6ENS_DEFAULT ( _DMA_CHENS_CH6ENS_DEFAULT << 6)

#define	DMA_CHENS_CH7ENS (0x1UL << 7)

#define	DMA_CHENS_CH7ENS_DEFAULT ( _DMA_CHENS_CH7ENS_DEFAULT << 7)

#define	DMA_CHPRIC_CH0PRIC (0x1UL << 0)

#define	DMA_CHPRIC_CH0PRIC_DEFAULT ( _DMA_CHPRIC_CH0PRIC_DEFAULT << 0)

#define	DMA_CHPRIC_CH1PRIC (0x1UL << 1)

#define	DMA_CHPRIC_CH1PRIC_DEFAULT ( _DMA_CHPRIC_CH1PRIC_DEFAULT << 1)

#define	DMA_CHPRIC_CH2PRIC (0x1UL << 2)

#define	DMA_CHPRIC_CH2PRIC_DEFAULT ( _DMA_CHPRIC_CH2PRIC_DEFAULT << 2)

#define	DMA_CHPRIC_CH3PRIC (0x1UL << 3)

#define	DMA_CHPRIC_CH3PRIC_DEFAULT ( _DMA_CHPRIC_CH3PRIC_DEFAULT << 3)

#define	DMA_CHPRIC_CH4PRIC (0x1UL << 4)

#define	DMA_CHPRIC_CH4PRIC_DEFAULT ( _DMA_CHPRIC_CH4PRIC_DEFAULT << 4)

#define	DMA_CHPRIC_CH5PRIC (0x1UL << 5)

#define	DMA_CHPRIC_CH5PRIC_DEFAULT ( _DMA_CHPRIC_CH5PRIC_DEFAULT << 5)

#define	DMA_CHPRIC_CH6PRIC (0x1UL << 6)

#define	DMA_CHPRIC_CH6PRIC_DEFAULT ( _DMA_CHPRIC_CH6PRIC_DEFAULT << 6)

#define	DMA_CHPRIC_CH7PRIC (0x1UL << 7)

#define	DMA_CHPRIC_CH7PRIC_DEFAULT ( _DMA_CHPRIC_CH7PRIC_DEFAULT << 7)

#define	DMA_CHPRIS_CH0PRIS (0x1UL << 0)

#define	DMA_CHPRIS_CH0PRIS_DEFAULT ( _DMA_CHPRIS_CH0PRIS_DEFAULT << 0)

#define	DMA_CHPRIS_CH1PRIS (0x1UL << 1)

#define	DMA_CHPRIS_CH1PRIS_DEFAULT ( _DMA_CHPRIS_CH1PRIS_DEFAULT << 1)

#define	DMA_CHPRIS_CH2PRIS (0x1UL << 2)

#define	DMA_CHPRIS_CH2PRIS_DEFAULT ( _DMA_CHPRIS_CH2PRIS_DEFAULT << 2)

#define	DMA_CHPRIS_CH3PRIS (0x1UL << 3)

#define	DMA_CHPRIS_CH3PRIS_DEFAULT ( _DMA_CHPRIS_CH3PRIS_DEFAULT << 3)

#define	DMA_CHPRIS_CH4PRIS (0x1UL << 4)

#define	DMA_CHPRIS_CH4PRIS_DEFAULT ( _DMA_CHPRIS_CH4PRIS_DEFAULT << 4)

#define	DMA_CHPRIS_CH5PRIS (0x1UL << 5)

#define	DMA_CHPRIS_CH5PRIS_DEFAULT ( _DMA_CHPRIS_CH5PRIS_DEFAULT << 5)

#define	DMA_CHPRIS_CH6PRIS (0x1UL << 6)

#define	DMA_CHPRIS_CH6PRIS_DEFAULT ( _DMA_CHPRIS_CH6PRIS_DEFAULT << 6)

#define	DMA_CHPRIS_CH7PRIS (0x1UL << 7)

#define	DMA_CHPRIS_CH7PRIS_DEFAULT ( _DMA_CHPRIS_CH7PRIS_DEFAULT << 7)

#define	DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0)

#define	DMA_CHREQMASKC_CH0REQMASKC_DEFAULT ( _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)

#define	DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1)

#define	DMA_CHREQMASKC_CH1REQMASKC_DEFAULT ( _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)

#define	DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2)

#define	DMA_CHREQMASKC_CH2REQMASKC_DEFAULT ( _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)

#define	DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3)

#define	DMA_CHREQMASKC_CH3REQMASKC_DEFAULT ( _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)

#define	DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4)

#define	DMA_CHREQMASKC_CH4REQMASKC_DEFAULT ( _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)

#define	DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5)

#define	DMA_CHREQMASKC_CH5REQMASKC_DEFAULT ( _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)

#define	DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6)

#define	DMA_CHREQMASKC_CH6REQMASKC_DEFAULT ( _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6)

#define	DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7)

#define	DMA_CHREQMASKC_CH7REQMASKC_DEFAULT ( _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7)

#define	DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0)

#define	DMA_CHREQMASKS_CH0REQMASKS_DEFAULT ( _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)

#define	DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1)

#define	DMA_CHREQMASKS_CH1REQMASKS_DEFAULT ( _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)

#define	DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2)

#define	DMA_CHREQMASKS_CH2REQMASKS_DEFAULT ( _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)

#define	DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3)

#define	DMA_CHREQMASKS_CH3REQMASKS_DEFAULT ( _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)

#define	DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4)

#define	DMA_CHREQMASKS_CH4REQMASKS_DEFAULT ( _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)

#define	DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5)

#define	DMA_CHREQMASKS_CH5REQMASKS_DEFAULT ( _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)

#define	DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6)

#define	DMA_CHREQMASKS_CH6REQMASKS_DEFAULT ( _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6)

#define	DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7)

#define	DMA_CHREQMASKS_CH7REQMASKS_DEFAULT ( _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7)

#define	DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0)

#define	DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT ( _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)

#define	DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1)

#define	DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT ( _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)

#define	DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2)

#define	DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT ( _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)

#define	DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3)

#define	DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT ( _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)

#define	DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4)

#define	DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT ( _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)

#define	DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5)

#define	DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT ( _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)

#define	DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6)

#define	DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT ( _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6)

#define	DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7)

#define	DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT ( _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7)

#define	DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0)

#define	DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT ( _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)

#define	DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1)

#define	DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT ( _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)

#define	DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2)

#define	DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT ( _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)

#define	DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3)

#define	DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT ( _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)

#define	DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4)

#define	DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT ( _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)

#define	DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5)

#define	DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT ( _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)

#define	DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6)

#define	DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT ( _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6)

#define	DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7)

#define	DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT ( _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7)

#define	DMA_CHSWREQ_CH0SWREQ (0x1UL << 0)

#define	DMA_CHSWREQ_CH0SWREQ_DEFAULT ( _DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)

#define	DMA_CHSWREQ_CH1SWREQ (0x1UL << 1)

#define	DMA_CHSWREQ_CH1SWREQ_DEFAULT ( _DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)

#define	DMA_CHSWREQ_CH2SWREQ (0x1UL << 2)

#define	DMA_CHSWREQ_CH2SWREQ_DEFAULT ( _DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)

#define	DMA_CHSWREQ_CH3SWREQ (0x1UL << 3)

#define	DMA_CHSWREQ_CH3SWREQ_DEFAULT ( _DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)

#define	DMA_CHSWREQ_CH4SWREQ (0x1UL << 4)

#define	DMA_CHSWREQ_CH4SWREQ_DEFAULT ( _DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)

#define	DMA_CHSWREQ_CH5SWREQ (0x1UL << 5)

#define	DMA_CHSWREQ_CH5SWREQ_DEFAULT ( _DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)

#define	DMA_CHSWREQ_CH6SWREQ (0x1UL << 6)

#define	DMA_CHSWREQ_CH6SWREQ_DEFAULT ( _DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6)

#define	DMA_CHSWREQ_CH7SWREQ (0x1UL << 7)

#define	DMA_CHSWREQ_CH7SWREQ_DEFAULT ( _DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7)

#define	DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0)

#define	DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT ( _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)

#define	DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1)

#define	DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT ( _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)

#define	DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2)

#define	DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT ( _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)

#define	DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3)

#define	DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT ( _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)

#define	DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4)

#define	DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT ( _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)

#define	DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5)

#define	DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT ( _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)

#define	DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6)

#define	DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT ( _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6)

#define	DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7)

#define	DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT ( _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7)

#define	DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0)

#define	DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY ( _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)

#define	DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT ( _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)

#define	DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST ( _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)

#define	DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1)

#define	DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT ( _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)

#define	DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2)

#define	DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT ( _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)

#define	DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3)

#define	DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT ( _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)

#define	DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4)

#define	DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT ( _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)

#define	DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5)

#define	DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT ( _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)

#define	DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6)

#define	DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT ( _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6)

#define	DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7)

#define	DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT ( _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7)

#define	DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0)

#define	DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT ( _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)

#define	DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1)

#define	DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT ( _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)

#define	DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2)

#define	DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT ( _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)

#define	DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3)

#define	DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT ( _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)

#define	DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4)

#define	DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT ( _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)

#define	DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5)

#define	DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT ( _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)

#define	DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6)

#define	DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT ( _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6)

#define	DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7)

#define	DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT ( _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7)

#define	DMA_CONFIG_CHPROT (0x1UL << 5)

#define	DMA_CONFIG_CHPROT_DEFAULT ( _DMA_CONFIG_CHPROT_DEFAULT << 5)

#define	DMA_CONFIG_EN (0x1UL << 0)

#define	DMA_CONFIG_EN_DEFAULT ( _DMA_CONFIG_EN_DEFAULT << 0)

#define	DMA_CTRLBASE_CTRLBASE_DEFAULT ( _DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)

#define	DMA_ERRORC_ERRORC (0x1UL << 0)

#define	DMA_ERRORC_ERRORC_DEFAULT ( _DMA_ERRORC_ERRORC_DEFAULT << 0)

#define	DMA_IEN_CH0DONE (0x1UL << 0)

#define	DMA_IEN_CH0DONE_DEFAULT ( _DMA_IEN_CH0DONE_DEFAULT << 0)

#define	DMA_IEN_CH1DONE (0x1UL << 1)

#define	DMA_IEN_CH1DONE_DEFAULT ( _DMA_IEN_CH1DONE_DEFAULT << 1)

#define	DMA_IEN_CH2DONE (0x1UL << 2)

#define	DMA_IEN_CH2DONE_DEFAULT ( _DMA_IEN_CH2DONE_DEFAULT << 2)

#define	DMA_IEN_CH3DONE (0x1UL << 3)

#define	DMA_IEN_CH3DONE_DEFAULT ( _DMA_IEN_CH3DONE_DEFAULT << 3)

#define	DMA_IEN_CH4DONE (0x1UL << 4)

#define	DMA_IEN_CH4DONE_DEFAULT ( _DMA_IEN_CH4DONE_DEFAULT << 4)

#define	DMA_IEN_CH5DONE (0x1UL << 5)

#define	DMA_IEN_CH5DONE_DEFAULT ( _DMA_IEN_CH5DONE_DEFAULT << 5)

#define	DMA_IEN_CH6DONE (0x1UL << 6)

#define	DMA_IEN_CH6DONE_DEFAULT ( _DMA_IEN_CH6DONE_DEFAULT << 6)

#define	DMA_IEN_CH7DONE (0x1UL << 7)

#define	DMA_IEN_CH7DONE_DEFAULT ( _DMA_IEN_CH7DONE_DEFAULT << 7)

#define	DMA_IEN_ERR (0x1UL << 31)

#define	DMA_IEN_ERR_DEFAULT ( _DMA_IEN_ERR_DEFAULT << 31)

#define	DMA_IF_CH0DONE (0x1UL << 0)

#define	DMA_IF_CH0DONE_DEFAULT ( _DMA_IF_CH0DONE_DEFAULT << 0)

#define	DMA_IF_CH1DONE (0x1UL << 1)

#define	DMA_IF_CH1DONE_DEFAULT ( _DMA_IF_CH1DONE_DEFAULT << 1)

#define	DMA_IF_CH2DONE (0x1UL << 2)

#define	DMA_IF_CH2DONE_DEFAULT ( _DMA_IF_CH2DONE_DEFAULT << 2)

#define	DMA_IF_CH3DONE (0x1UL << 3)

#define	DMA_IF_CH3DONE_DEFAULT ( _DMA_IF_CH3DONE_DEFAULT << 3)

#define	DMA_IF_CH4DONE (0x1UL << 4)

#define	DMA_IF_CH4DONE_DEFAULT ( _DMA_IF_CH4DONE_DEFAULT << 4)

#define	DMA_IF_CH5DONE (0x1UL << 5)

#define	DMA_IF_CH5DONE_DEFAULT ( _DMA_IF_CH5DONE_DEFAULT << 5)

#define	DMA_IF_CH6DONE (0x1UL << 6)

#define	DMA_IF_CH6DONE_DEFAULT ( _DMA_IF_CH6DONE_DEFAULT << 6)

#define	DMA_IF_CH7DONE (0x1UL << 7)

#define	DMA_IF_CH7DONE_DEFAULT ( _DMA_IF_CH7DONE_DEFAULT << 7)

#define	DMA_IF_ERR (0x1UL << 31)

#define	DMA_IF_ERR_DEFAULT ( _DMA_IF_ERR_DEFAULT << 31)

#define	DMA_IFC_CH0DONE (0x1UL << 0)

#define	DMA_IFC_CH0DONE_DEFAULT ( _DMA_IFC_CH0DONE_DEFAULT << 0)

#define	DMA_IFC_CH1DONE (0x1UL << 1)

#define	DMA_IFC_CH1DONE_DEFAULT ( _DMA_IFC_CH1DONE_DEFAULT << 1)

#define	DMA_IFC_CH2DONE (0x1UL << 2)

#define	DMA_IFC_CH2DONE_DEFAULT ( _DMA_IFC_CH2DONE_DEFAULT << 2)

#define	DMA_IFC_CH3DONE (0x1UL << 3)

#define	DMA_IFC_CH3DONE_DEFAULT ( _DMA_IFC_CH3DONE_DEFAULT << 3)

#define	DMA_IFC_CH4DONE (0x1UL << 4)

#define	DMA_IFC_CH4DONE_DEFAULT ( _DMA_IFC_CH4DONE_DEFAULT << 4)

#define	DMA_IFC_CH5DONE (0x1UL << 5)

#define	DMA_IFC_CH5DONE_DEFAULT ( _DMA_IFC_CH5DONE_DEFAULT << 5)

#define	DMA_IFC_CH6DONE (0x1UL << 6)

#define	DMA_IFC_CH6DONE_DEFAULT ( _DMA_IFC_CH6DONE_DEFAULT << 6)

#define	DMA_IFC_CH7DONE (0x1UL << 7)

#define	DMA_IFC_CH7DONE_DEFAULT ( _DMA_IFC_CH7DONE_DEFAULT << 7)

#define	DMA_IFC_ERR (0x1UL << 31)

#define	DMA_IFC_ERR_DEFAULT ( _DMA_IFC_ERR_DEFAULT << 31)

#define	DMA_IFS_CH0DONE (0x1UL << 0)

#define	DMA_IFS_CH0DONE_DEFAULT ( _DMA_IFS_CH0DONE_DEFAULT << 0)

#define	DMA_IFS_CH1DONE (0x1UL << 1)

#define	DMA_IFS_CH1DONE_DEFAULT ( _DMA_IFS_CH1DONE_DEFAULT << 1)

#define	DMA_IFS_CH2DONE (0x1UL << 2)

#define	DMA_IFS_CH2DONE_DEFAULT ( _DMA_IFS_CH2DONE_DEFAULT << 2)

#define	DMA_IFS_CH3DONE (0x1UL << 3)

#define	DMA_IFS_CH3DONE_DEFAULT ( _DMA_IFS_CH3DONE_DEFAULT << 3)

#define	DMA_IFS_CH4DONE (0x1UL << 4)

#define	DMA_IFS_CH4DONE_DEFAULT ( _DMA_IFS_CH4DONE_DEFAULT << 4)

#define	DMA_IFS_CH5DONE (0x1UL << 5)

#define	DMA_IFS_CH5DONE_DEFAULT ( _DMA_IFS_CH5DONE_DEFAULT << 5)

#define	DMA_IFS_CH6DONE (0x1UL << 6)

#define	DMA_IFS_CH6DONE_DEFAULT ( _DMA_IFS_CH6DONE_DEFAULT << 6)

#define	DMA_IFS_CH7DONE (0x1UL << 7)

#define	DMA_IFS_CH7DONE_DEFAULT ( _DMA_IFS_CH7DONE_DEFAULT << 7)

#define	DMA_IFS_ERR (0x1UL << 31)

#define	DMA_IFS_ERR_DEFAULT ( _DMA_IFS_ERR_DEFAULT << 31)

#define	DMA_STATUS_CHNUM_DEFAULT ( _DMA_STATUS_CHNUM_DEFAULT << 16)

#define	DMA_STATUS_EN (0x1UL << 0)

#define	DMA_STATUS_EN_DEFAULT ( _DMA_STATUS_EN_DEFAULT << 0)

#define	DMA_STATUS_STATE_DEFAULT ( _DMA_STATUS_STATE_DEFAULT << 4)

#define	DMA_STATUS_STATE_DONE ( _DMA_STATUS_STATE_DONE << 4)

#define	DMA_STATUS_STATE_IDLE ( _DMA_STATUS_STATE_IDLE << 4)

#define	DMA_STATUS_STATE_PERSCATTRANS ( _DMA_STATUS_STATE_PERSCATTRANS << 4)

#define	DMA_STATUS_STATE_RDCHCTRLDATA ( _DMA_STATUS_STATE_RDCHCTRLDATA << 4)

#define	DMA_STATUS_STATE_RDDSTENDPTR ( _DMA_STATUS_STATE_RDDSTENDPTR << 4)

EFM32G_DMA_BitFieldsDevices

Macros