Macros
#define	_VDAC_CAL_GAINERRTRIM_DEFAULT 0x00000020UL

#define	_VDAC_CAL_GAINERRTRIM_MASK 0x3F00UL

#define	_VDAC_CAL_GAINERRTRIM_SHIFT 8

#define	_VDAC_CAL_GAINERRTRIMCH1_DEFAULT 0x00000008UL

#define	_VDAC_CAL_GAINERRTRIMCH1_MASK 0xF0000UL

#define	_VDAC_CAL_GAINERRTRIMCH1_SHIFT 16

#define	_VDAC_CAL_MASK 0x000F3F07UL

#define	_VDAC_CAL_OFFSETTRIM_DEFAULT 0x00000004UL

#define	_VDAC_CAL_OFFSETTRIM_MASK 0x7UL

#define	_VDAC_CAL_OFFSETTRIM_SHIFT 0

#define	_VDAC_CAL_RESETVALUE 0x00082004UL

#define	_VDAC_CH0CTRL_CONVMODE_CONTINUOUS 0x00000000UL

#define	_VDAC_CH0CTRL_CONVMODE_DEFAULT 0x00000000UL

#define	_VDAC_CH0CTRL_CONVMODE_MASK 0x1UL

#define	_VDAC_CH0CTRL_CONVMODE_SAMPLEOFF 0x00000001UL

#define	_VDAC_CH0CTRL_CONVMODE_SHIFT 0

#define	_VDAC_CH0CTRL_MASK 0x00007171UL

#define	_VDAC_CH0CTRL_PRSASYNC_DEFAULT 0x00000000UL

#define	_VDAC_CH0CTRL_PRSASYNC_MASK 0x100UL

#define	_VDAC_CH0CTRL_PRSASYNC_SHIFT 8

#define	_VDAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL

#define	_VDAC_CH0CTRL_PRSSEL_MASK 0x7000UL

#define	_VDAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL

#define	_VDAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL

#define	_VDAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL

#define	_VDAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL

#define	_VDAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL

#define	_VDAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL

#define	_VDAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL

#define	_VDAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL

#define	_VDAC_CH0CTRL_PRSSEL_SHIFT 12

#define	_VDAC_CH0CTRL_RESETVALUE 0x00000000UL

#define	_VDAC_CH0CTRL_TRIGMODE_DEFAULT 0x00000000UL

#define	_VDAC_CH0CTRL_TRIGMODE_LESENSE 0x00000005UL

#define	_VDAC_CH0CTRL_TRIGMODE_MASK 0x70UL

#define	_VDAC_CH0CTRL_TRIGMODE_PRS 0x00000001UL

#define	_VDAC_CH0CTRL_TRIGMODE_REFRESH 0x00000002UL

#define	_VDAC_CH0CTRL_TRIGMODE_SHIFT 4

#define	_VDAC_CH0CTRL_TRIGMODE_SW 0x00000000UL

#define	_VDAC_CH0CTRL_TRIGMODE_SWPRS 0x00000003UL

#define	_VDAC_CH0CTRL_TRIGMODE_SWREFRESH 0x00000004UL

#define	_VDAC_CH0DATA_DATA_DEFAULT 0x00000800UL

#define	_VDAC_CH0DATA_DATA_MASK 0xFFFUL

#define	_VDAC_CH0DATA_DATA_SHIFT 0

#define	_VDAC_CH0DATA_MASK 0x00000FFFUL

#define	_VDAC_CH0DATA_RESETVALUE 0x00000800UL

#define	_VDAC_CH1CTRL_CONVMODE_CONTINUOUS 0x00000000UL

#define	_VDAC_CH1CTRL_CONVMODE_DEFAULT 0x00000000UL

#define	_VDAC_CH1CTRL_CONVMODE_MASK 0x1UL

#define	_VDAC_CH1CTRL_CONVMODE_SAMPLEOFF 0x00000001UL

#define	_VDAC_CH1CTRL_CONVMODE_SHIFT 0

#define	_VDAC_CH1CTRL_MASK 0x00007171UL

#define	_VDAC_CH1CTRL_PRSASYNC_DEFAULT 0x00000000UL

#define	_VDAC_CH1CTRL_PRSASYNC_MASK 0x100UL

#define	_VDAC_CH1CTRL_PRSASYNC_SHIFT 8

#define	_VDAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL

#define	_VDAC_CH1CTRL_PRSSEL_MASK 0x7000UL

#define	_VDAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL

#define	_VDAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL

#define	_VDAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL

#define	_VDAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL

#define	_VDAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL

#define	_VDAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL

#define	_VDAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL

#define	_VDAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL

#define	_VDAC_CH1CTRL_PRSSEL_SHIFT 12

#define	_VDAC_CH1CTRL_RESETVALUE 0x00000000UL

#define	_VDAC_CH1CTRL_TRIGMODE_DEFAULT 0x00000000UL

#define	_VDAC_CH1CTRL_TRIGMODE_LESENSE 0x00000005UL

#define	_VDAC_CH1CTRL_TRIGMODE_MASK 0x70UL

#define	_VDAC_CH1CTRL_TRIGMODE_PRS 0x00000001UL

#define	_VDAC_CH1CTRL_TRIGMODE_REFRESH 0x00000002UL

#define	_VDAC_CH1CTRL_TRIGMODE_SHIFT 4

#define	_VDAC_CH1CTRL_TRIGMODE_SW 0x00000000UL

#define	_VDAC_CH1CTRL_TRIGMODE_SWPRS 0x00000003UL

#define	_VDAC_CH1CTRL_TRIGMODE_SWREFRESH 0x00000004UL

#define	_VDAC_CH1DATA_DATA_DEFAULT 0x00000800UL

#define	_VDAC_CH1DATA_DATA_MASK 0xFFFUL

#define	_VDAC_CH1DATA_DATA_SHIFT 0

#define	_VDAC_CH1DATA_MASK 0x00000FFFUL

#define	_VDAC_CH1DATA_RESETVALUE 0x00000800UL

#define	_VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL

#define	_VDAC_CMD_CH0DIS_MASK 0x2UL

#define	_VDAC_CMD_CH0DIS_SHIFT 1

#define	_VDAC_CMD_CH0EN_DEFAULT 0x00000000UL

#define	_VDAC_CMD_CH0EN_MASK 0x1UL

#define	_VDAC_CMD_CH0EN_SHIFT 0

#define	_VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL

#define	_VDAC_CMD_CH1DIS_MASK 0x8UL

#define	_VDAC_CMD_CH1DIS_SHIFT 3

#define	_VDAC_CMD_CH1EN_DEFAULT 0x00000000UL

#define	_VDAC_CMD_CH1EN_MASK 0x4UL

#define	_VDAC_CMD_CH1EN_SHIFT 2

#define	_VDAC_CMD_MASK 0x00FF000FUL

#define	_VDAC_CMD_OPA0DIS_DEFAULT 0x00000000UL

#define	_VDAC_CMD_OPA0DIS_MASK 0x20000UL

#define	_VDAC_CMD_OPA0DIS_SHIFT 17

#define	_VDAC_CMD_OPA0EN_DEFAULT 0x00000000UL

#define	_VDAC_CMD_OPA0EN_MASK 0x10000UL

#define	_VDAC_CMD_OPA0EN_SHIFT 16

#define	_VDAC_CMD_OPA1DIS_DEFAULT 0x00000000UL

#define	_VDAC_CMD_OPA1DIS_MASK 0x80000UL

#define	_VDAC_CMD_OPA1DIS_SHIFT 19

#define	_VDAC_CMD_OPA1EN_DEFAULT 0x00000000UL

#define	_VDAC_CMD_OPA1EN_MASK 0x40000UL

#define	_VDAC_CMD_OPA1EN_SHIFT 18

#define	_VDAC_CMD_OPA2DIS_DEFAULT 0x00000000UL

#define	_VDAC_CMD_OPA2DIS_MASK 0x200000UL

#define	_VDAC_CMD_OPA2DIS_SHIFT 21

#define	_VDAC_CMD_OPA2EN_DEFAULT 0x00000000UL

#define	_VDAC_CMD_OPA2EN_MASK 0x100000UL

#define	_VDAC_CMD_OPA2EN_SHIFT 20

#define	_VDAC_CMD_OPA3DIS_DEFAULT 0x00000000UL

#define	_VDAC_CMD_OPA3DIS_MASK 0x800000UL

#define	_VDAC_CMD_OPA3DIS_SHIFT 23

#define	_VDAC_CMD_OPA3EN_DEFAULT 0x00000000UL

#define	_VDAC_CMD_OPA3EN_MASK 0x400000UL

#define	_VDAC_CMD_OPA3EN_SHIFT 22

#define	_VDAC_CMD_RESETVALUE 0x00000000UL

#define	_VDAC_COMBDATA_CH0DATA_DEFAULT 0x00000800UL

#define	_VDAC_COMBDATA_CH0DATA_MASK 0xFFFUL

#define	_VDAC_COMBDATA_CH0DATA_SHIFT 0

#define	_VDAC_COMBDATA_CH1DATA_DEFAULT 0x00000800UL

#define	_VDAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL

#define	_VDAC_COMBDATA_CH1DATA_SHIFT 16

#define	_VDAC_COMBDATA_MASK 0x0FFF0FFFUL

#define	_VDAC_COMBDATA_RESETVALUE 0x08000800UL

#define	_VDAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL

#define	_VDAC_CTRL_CH0PRESCRST_MASK 0x40UL

#define	_VDAC_CTRL_CH0PRESCRST_SHIFT 6

#define	_VDAC_CTRL_DACCLKMODE_ASYNC 0x00000001UL

#define	_VDAC_CTRL_DACCLKMODE_DEFAULT 0x00000000UL

#define	_VDAC_CTRL_DACCLKMODE_MASK 0x80000000UL

#define	_VDAC_CTRL_DACCLKMODE_SHIFT 31

#define	_VDAC_CTRL_DACCLKMODE_SYNC 0x00000000UL

#define	_VDAC_CTRL_DIFF_DEFAULT 0x00000000UL

#define	_VDAC_CTRL_DIFF_MASK 0x1UL

#define	_VDAC_CTRL_DIFF_SHIFT 0

#define	_VDAC_CTRL_MASK 0x937F0771UL

#define	_VDAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL

#define	_VDAC_CTRL_OUTENPRS_MASK 0x20UL

#define	_VDAC_CTRL_OUTENPRS_SHIFT 5

#define	_VDAC_CTRL_PRESC_DEFAULT 0x00000000UL

#define	_VDAC_CTRL_PRESC_MASK 0x7F0000UL

#define	_VDAC_CTRL_PRESC_NODIVISION 0x00000000UL

#define	_VDAC_CTRL_PRESC_SHIFT 16

#define	_VDAC_CTRL_REFRESHPERIOD_16CYCLES 0x00000001UL

#define	_VDAC_CTRL_REFRESHPERIOD_32CYCLES 0x00000002UL

#define	_VDAC_CTRL_REFRESHPERIOD_64CYCLES 0x00000003UL

#define	_VDAC_CTRL_REFRESHPERIOD_8CYCLES 0x00000000UL

#define	_VDAC_CTRL_REFRESHPERIOD_DEFAULT 0x00000000UL

#define	_VDAC_CTRL_REFRESHPERIOD_MASK 0x3000000UL

#define	_VDAC_CTRL_REFRESHPERIOD_SHIFT 24

#define	_VDAC_CTRL_REFSEL_1V25 0x00000002UL

#define	_VDAC_CTRL_REFSEL_1V25LN 0x00000000UL

#define	_VDAC_CTRL_REFSEL_2V5 0x00000003UL

#define	_VDAC_CTRL_REFSEL_2V5LN 0x00000001UL

#define	_VDAC_CTRL_REFSEL_DEFAULT 0x00000000UL

#define	_VDAC_CTRL_REFSEL_EXT 0x00000006UL

#define	_VDAC_CTRL_REFSEL_MASK 0x700UL

#define	_VDAC_CTRL_REFSEL_SHIFT 8

#define	_VDAC_CTRL_REFSEL_VDD 0x00000004UL

#define	_VDAC_CTRL_RESETVALUE 0x00000000UL

#define	_VDAC_CTRL_SINEMODE_DEFAULT 0x00000000UL

#define	_VDAC_CTRL_SINEMODE_MASK 0x10UL

#define	_VDAC_CTRL_SINEMODE_SHIFT 4

#define	_VDAC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL

#define	_VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL

#define	_VDAC_CTRL_WARMUPMODE_MASK 0x10000000UL

#define	_VDAC_CTRL_WARMUPMODE_NORMAL 0x00000000UL

#define	_VDAC_CTRL_WARMUPMODE_SHIFT 28

#define	_VDAC_IEN_CH0BL_DEFAULT 0x00000000UL

#define	_VDAC_IEN_CH0BL_MASK 0x40UL

#define	_VDAC_IEN_CH0BL_SHIFT 6

#define	_VDAC_IEN_CH0CD_DEFAULT 0x00000000UL

#define	_VDAC_IEN_CH0CD_MASK 0x1UL

#define	_VDAC_IEN_CH0CD_SHIFT 0

#define	_VDAC_IEN_CH0OF_DEFAULT 0x00000000UL

#define	_VDAC_IEN_CH0OF_MASK 0x4UL

#define	_VDAC_IEN_CH0OF_SHIFT 2

#define	_VDAC_IEN_CH0UF_DEFAULT 0x00000000UL

#define	_VDAC_IEN_CH0UF_MASK 0x10UL

#define	_VDAC_IEN_CH0UF_SHIFT 4

#define	_VDAC_IEN_CH1BL_DEFAULT 0x00000000UL

#define	_VDAC_IEN_CH1BL_MASK 0x80UL

#define	_VDAC_IEN_CH1BL_SHIFT 7

#define	_VDAC_IEN_CH1CD_DEFAULT 0x00000000UL

#define	_VDAC_IEN_CH1CD_MASK 0x2UL

#define	_VDAC_IEN_CH1CD_SHIFT 1

#define	_VDAC_IEN_CH1OF_DEFAULT 0x00000000UL

#define	_VDAC_IEN_CH1OF_MASK 0x8UL

#define	_VDAC_IEN_CH1OF_SHIFT 3

#define	_VDAC_IEN_CH1UF_DEFAULT 0x00000000UL

#define	_VDAC_IEN_CH1UF_MASK 0x20UL

#define	_VDAC_IEN_CH1UF_SHIFT 5

#define	_VDAC_IEN_EM23ERR_DEFAULT 0x00000000UL

#define	_VDAC_IEN_EM23ERR_MASK 0x8000UL

#define	_VDAC_IEN_EM23ERR_SHIFT 15

#define	_VDAC_IEN_MASK 0xF0FF80FFUL

#define	_VDAC_IEN_OPA0APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IEN_OPA0APORTCONFLICT_MASK 0x10000UL

#define	_VDAC_IEN_OPA0APORTCONFLICT_SHIFT 16

#define	_VDAC_IEN_OPA0OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IEN_OPA0OUTVALID_MASK 0x10000000UL

#define	_VDAC_IEN_OPA0OUTVALID_SHIFT 28

#define	_VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IEN_OPA0PRSTIMEDERR_MASK 0x100000UL

#define	_VDAC_IEN_OPA0PRSTIMEDERR_SHIFT 20

#define	_VDAC_IEN_OPA1APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IEN_OPA1APORTCONFLICT_MASK 0x20000UL

#define	_VDAC_IEN_OPA1APORTCONFLICT_SHIFT 17

#define	_VDAC_IEN_OPA1OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IEN_OPA1OUTVALID_MASK 0x20000000UL

#define	_VDAC_IEN_OPA1OUTVALID_SHIFT 29

#define	_VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IEN_OPA1PRSTIMEDERR_MASK 0x200000UL

#define	_VDAC_IEN_OPA1PRSTIMEDERR_SHIFT 21

#define	_VDAC_IEN_OPA2APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IEN_OPA2APORTCONFLICT_MASK 0x40000UL

#define	_VDAC_IEN_OPA2APORTCONFLICT_SHIFT 18

#define	_VDAC_IEN_OPA2OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IEN_OPA2OUTVALID_MASK 0x40000000UL

#define	_VDAC_IEN_OPA2OUTVALID_SHIFT 30

#define	_VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IEN_OPA2PRSTIMEDERR_MASK 0x400000UL

#define	_VDAC_IEN_OPA2PRSTIMEDERR_SHIFT 22

#define	_VDAC_IEN_OPA3APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IEN_OPA3APORTCONFLICT_MASK 0x80000UL

#define	_VDAC_IEN_OPA3APORTCONFLICT_SHIFT 19

#define	_VDAC_IEN_OPA3OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IEN_OPA3OUTVALID_MASK 0x80000000UL

#define	_VDAC_IEN_OPA3OUTVALID_SHIFT 31

#define	_VDAC_IEN_OPA3PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IEN_OPA3PRSTIMEDERR_MASK 0x800000UL

#define	_VDAC_IEN_OPA3PRSTIMEDERR_SHIFT 23

#define	_VDAC_IEN_RESETVALUE 0x00000000UL

#define	_VDAC_IF_CH0BL_DEFAULT 0x00000001UL

#define	_VDAC_IF_CH0BL_MASK 0x40UL

#define	_VDAC_IF_CH0BL_SHIFT 6

#define	_VDAC_IF_CH0CD_DEFAULT 0x00000000UL

#define	_VDAC_IF_CH0CD_MASK 0x1UL

#define	_VDAC_IF_CH0CD_SHIFT 0

#define	_VDAC_IF_CH0OF_DEFAULT 0x00000000UL

#define	_VDAC_IF_CH0OF_MASK 0x4UL

#define	_VDAC_IF_CH0OF_SHIFT 2

#define	_VDAC_IF_CH0UF_DEFAULT 0x00000000UL

#define	_VDAC_IF_CH0UF_MASK 0x10UL

#define	_VDAC_IF_CH0UF_SHIFT 4

#define	_VDAC_IF_CH1BL_DEFAULT 0x00000001UL

#define	_VDAC_IF_CH1BL_MASK 0x80UL

#define	_VDAC_IF_CH1BL_SHIFT 7

#define	_VDAC_IF_CH1CD_DEFAULT 0x00000000UL

#define	_VDAC_IF_CH1CD_MASK 0x2UL

#define	_VDAC_IF_CH1CD_SHIFT 1

#define	_VDAC_IF_CH1OF_DEFAULT 0x00000000UL

#define	_VDAC_IF_CH1OF_MASK 0x8UL

#define	_VDAC_IF_CH1OF_SHIFT 3

#define	_VDAC_IF_CH1UF_DEFAULT 0x00000000UL

#define	_VDAC_IF_CH1UF_MASK 0x20UL

#define	_VDAC_IF_CH1UF_SHIFT 5

#define	_VDAC_IF_EM23ERR_DEFAULT 0x00000000UL

#define	_VDAC_IF_EM23ERR_MASK 0x8000UL

#define	_VDAC_IF_EM23ERR_SHIFT 15

#define	_VDAC_IF_MASK 0xF0FF80FFUL

#define	_VDAC_IF_OPA0APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IF_OPA0APORTCONFLICT_MASK 0x10000UL

#define	_VDAC_IF_OPA0APORTCONFLICT_SHIFT 16

#define	_VDAC_IF_OPA0OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IF_OPA0OUTVALID_MASK 0x10000000UL

#define	_VDAC_IF_OPA0OUTVALID_SHIFT 28

#define	_VDAC_IF_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IF_OPA0PRSTIMEDERR_MASK 0x100000UL

#define	_VDAC_IF_OPA0PRSTIMEDERR_SHIFT 20

#define	_VDAC_IF_OPA1APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IF_OPA1APORTCONFLICT_MASK 0x20000UL

#define	_VDAC_IF_OPA1APORTCONFLICT_SHIFT 17

#define	_VDAC_IF_OPA1OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IF_OPA1OUTVALID_MASK 0x20000000UL

#define	_VDAC_IF_OPA1OUTVALID_SHIFT 29

#define	_VDAC_IF_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IF_OPA1PRSTIMEDERR_MASK 0x200000UL

#define	_VDAC_IF_OPA1PRSTIMEDERR_SHIFT 21

#define	_VDAC_IF_OPA2APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IF_OPA2APORTCONFLICT_MASK 0x40000UL

#define	_VDAC_IF_OPA2APORTCONFLICT_SHIFT 18

#define	_VDAC_IF_OPA2OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IF_OPA2OUTVALID_MASK 0x40000000UL

#define	_VDAC_IF_OPA2OUTVALID_SHIFT 30

#define	_VDAC_IF_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IF_OPA2PRSTIMEDERR_MASK 0x400000UL

#define	_VDAC_IF_OPA2PRSTIMEDERR_SHIFT 22

#define	_VDAC_IF_OPA3APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IF_OPA3APORTCONFLICT_MASK 0x80000UL

#define	_VDAC_IF_OPA3APORTCONFLICT_SHIFT 19

#define	_VDAC_IF_OPA3OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IF_OPA3OUTVALID_MASK 0x80000000UL

#define	_VDAC_IF_OPA3OUTVALID_SHIFT 31

#define	_VDAC_IF_OPA3PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IF_OPA3PRSTIMEDERR_MASK 0x800000UL

#define	_VDAC_IF_OPA3PRSTIMEDERR_SHIFT 23

#define	_VDAC_IF_RESETVALUE 0x000000C0UL

#define	_VDAC_IFC_CH0CD_DEFAULT 0x00000000UL

#define	_VDAC_IFC_CH0CD_MASK 0x1UL

#define	_VDAC_IFC_CH0CD_SHIFT 0

#define	_VDAC_IFC_CH0OF_DEFAULT 0x00000000UL

#define	_VDAC_IFC_CH0OF_MASK 0x4UL

#define	_VDAC_IFC_CH0OF_SHIFT 2

#define	_VDAC_IFC_CH0UF_DEFAULT 0x00000000UL

#define	_VDAC_IFC_CH0UF_MASK 0x10UL

#define	_VDAC_IFC_CH0UF_SHIFT 4

#define	_VDAC_IFC_CH1CD_DEFAULT 0x00000000UL

#define	_VDAC_IFC_CH1CD_MASK 0x2UL

#define	_VDAC_IFC_CH1CD_SHIFT 1

#define	_VDAC_IFC_CH1OF_DEFAULT 0x00000000UL

#define	_VDAC_IFC_CH1OF_MASK 0x8UL

#define	_VDAC_IFC_CH1OF_SHIFT 3

#define	_VDAC_IFC_CH1UF_DEFAULT 0x00000000UL

#define	_VDAC_IFC_CH1UF_MASK 0x20UL

#define	_VDAC_IFC_CH1UF_SHIFT 5

#define	_VDAC_IFC_EM23ERR_DEFAULT 0x00000000UL

#define	_VDAC_IFC_EM23ERR_MASK 0x8000UL

#define	_VDAC_IFC_EM23ERR_SHIFT 15

#define	_VDAC_IFC_MASK 0xF0FF803FUL

#define	_VDAC_IFC_OPA0APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IFC_OPA0APORTCONFLICT_MASK 0x10000UL

#define	_VDAC_IFC_OPA0APORTCONFLICT_SHIFT 16

#define	_VDAC_IFC_OPA0OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IFC_OPA0OUTVALID_MASK 0x10000000UL

#define	_VDAC_IFC_OPA0OUTVALID_SHIFT 28

#define	_VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IFC_OPA0PRSTIMEDERR_MASK 0x100000UL

#define	_VDAC_IFC_OPA0PRSTIMEDERR_SHIFT 20

#define	_VDAC_IFC_OPA1APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IFC_OPA1APORTCONFLICT_MASK 0x20000UL

#define	_VDAC_IFC_OPA1APORTCONFLICT_SHIFT 17

#define	_VDAC_IFC_OPA1OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IFC_OPA1OUTVALID_MASK 0x20000000UL

#define	_VDAC_IFC_OPA1OUTVALID_SHIFT 29

#define	_VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IFC_OPA1PRSTIMEDERR_MASK 0x200000UL

#define	_VDAC_IFC_OPA1PRSTIMEDERR_SHIFT 21

#define	_VDAC_IFC_OPA2APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IFC_OPA2APORTCONFLICT_MASK 0x40000UL

#define	_VDAC_IFC_OPA2APORTCONFLICT_SHIFT 18

#define	_VDAC_IFC_OPA2OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IFC_OPA2OUTVALID_MASK 0x40000000UL

#define	_VDAC_IFC_OPA2OUTVALID_SHIFT 30

#define	_VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IFC_OPA2PRSTIMEDERR_MASK 0x400000UL

#define	_VDAC_IFC_OPA2PRSTIMEDERR_SHIFT 22

#define	_VDAC_IFC_OPA3APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IFC_OPA3APORTCONFLICT_MASK 0x80000UL

#define	_VDAC_IFC_OPA3APORTCONFLICT_SHIFT 19

#define	_VDAC_IFC_OPA3OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IFC_OPA3OUTVALID_MASK 0x80000000UL

#define	_VDAC_IFC_OPA3OUTVALID_SHIFT 31

#define	_VDAC_IFC_OPA3PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IFC_OPA3PRSTIMEDERR_MASK 0x800000UL

#define	_VDAC_IFC_OPA3PRSTIMEDERR_SHIFT 23

#define	_VDAC_IFC_RESETVALUE 0x00000000UL

#define	_VDAC_IFS_CH0CD_DEFAULT 0x00000000UL

#define	_VDAC_IFS_CH0CD_MASK 0x1UL

#define	_VDAC_IFS_CH0CD_SHIFT 0

#define	_VDAC_IFS_CH0OF_DEFAULT 0x00000000UL

#define	_VDAC_IFS_CH0OF_MASK 0x4UL

#define	_VDAC_IFS_CH0OF_SHIFT 2

#define	_VDAC_IFS_CH0UF_DEFAULT 0x00000000UL

#define	_VDAC_IFS_CH0UF_MASK 0x10UL

#define	_VDAC_IFS_CH0UF_SHIFT 4

#define	_VDAC_IFS_CH1CD_DEFAULT 0x00000000UL

#define	_VDAC_IFS_CH1CD_MASK 0x2UL

#define	_VDAC_IFS_CH1CD_SHIFT 1

#define	_VDAC_IFS_CH1OF_DEFAULT 0x00000000UL

#define	_VDAC_IFS_CH1OF_MASK 0x8UL

#define	_VDAC_IFS_CH1OF_SHIFT 3

#define	_VDAC_IFS_CH1UF_DEFAULT 0x00000000UL

#define	_VDAC_IFS_CH1UF_MASK 0x20UL

#define	_VDAC_IFS_CH1UF_SHIFT 5

#define	_VDAC_IFS_EM23ERR_DEFAULT 0x00000000UL

#define	_VDAC_IFS_EM23ERR_MASK 0x8000UL

#define	_VDAC_IFS_EM23ERR_SHIFT 15

#define	_VDAC_IFS_MASK 0xF0FF803FUL

#define	_VDAC_IFS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IFS_OPA0APORTCONFLICT_MASK 0x10000UL

#define	_VDAC_IFS_OPA0APORTCONFLICT_SHIFT 16

#define	_VDAC_IFS_OPA0OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IFS_OPA0OUTVALID_MASK 0x10000000UL

#define	_VDAC_IFS_OPA0OUTVALID_SHIFT 28

#define	_VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IFS_OPA0PRSTIMEDERR_MASK 0x100000UL

#define	_VDAC_IFS_OPA0PRSTIMEDERR_SHIFT 20

#define	_VDAC_IFS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IFS_OPA1APORTCONFLICT_MASK 0x20000UL

#define	_VDAC_IFS_OPA1APORTCONFLICT_SHIFT 17

#define	_VDAC_IFS_OPA1OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IFS_OPA1OUTVALID_MASK 0x20000000UL

#define	_VDAC_IFS_OPA1OUTVALID_SHIFT 29

#define	_VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IFS_OPA1PRSTIMEDERR_MASK 0x200000UL

#define	_VDAC_IFS_OPA1PRSTIMEDERR_SHIFT 21

#define	_VDAC_IFS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IFS_OPA2APORTCONFLICT_MASK 0x40000UL

#define	_VDAC_IFS_OPA2APORTCONFLICT_SHIFT 18

#define	_VDAC_IFS_OPA2OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IFS_OPA2OUTVALID_MASK 0x40000000UL

#define	_VDAC_IFS_OPA2OUTVALID_SHIFT 30

#define	_VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IFS_OPA2PRSTIMEDERR_MASK 0x400000UL

#define	_VDAC_IFS_OPA2PRSTIMEDERR_SHIFT 22

#define	_VDAC_IFS_OPA3APORTCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_IFS_OPA3APORTCONFLICT_MASK 0x80000UL

#define	_VDAC_IFS_OPA3APORTCONFLICT_SHIFT 19

#define	_VDAC_IFS_OPA3OUTVALID_DEFAULT 0x00000000UL

#define	_VDAC_IFS_OPA3OUTVALID_MASK 0x80000000UL

#define	_VDAC_IFS_OPA3OUTVALID_SHIFT 31

#define	_VDAC_IFS_OPA3PRSTIMEDERR_DEFAULT 0x00000000UL

#define	_VDAC_IFS_OPA3PRSTIMEDERR_MASK 0x800000UL

#define	_VDAC_IFS_OPA3PRSTIMEDERR_SHIFT 23

#define	_VDAC_IFS_RESETVALUE 0x00000000UL

#define	_VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL

#define	_VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2

#define	_VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL

#define	_VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3

#define	_VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL

#define	_VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4

#define	_VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL

#define	_VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5

#define	_VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL

#define	_VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6

#define	_VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL

#define	_VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7

#define	_VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL

#define	_VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8

#define	_VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL

#define	_VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL

#define	_VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9

#define

VDAC Bit FieldsDevices > VDAC

Macros