MSC_TypeDef Struct ReferenceDevices > MSC

MSC Register Declaration

Definition at line 49 of file efm32tg11b_msc.h .

#include < efm32tg11b_msc.h >

Data Fields

__IOM uint32_t AAPUNLOCKCMD
__IOM uint32_t ADDRB
__IOM uint32_t BOOTLOADERCTRL
__IOM uint32_t CACHECMD
__IOM uint32_t CACHECONFIG0
__IM uint32_t CACHEHITS
__IM uint32_t CACHEMISSES
__IOM uint32_t CMD
__IOM uint32_t CTRL
__IOM uint32_t IEN
__IM uint32_t IF
__IOM uint32_t IFC
__IOM uint32_t IFS
__IOM uint32_t IRQLATENCY
__IOM uint32_t LOCK
__IOM uint32_t MASSLOCK
__IOM uint32_t READCTRL
uint32_t RESERVED0 [1U]
uint32_t RESERVED1 [4U]
uint32_t RESERVED2 [1U]
uint32_t RESERVED3 [5U]
uint32_t RESERVED4 [6U]
__IOM uint32_t STARTUP
__IM uint32_t STATUS
__IOM uint32_t WDATA
__IOM uint32_t WRITECMD
__IOM uint32_t WRITECTRL

Field Documentation

__IOM uint32_t MSC_TypeDef::AAPUNLOCKCMD

Software Unlock AAP Command Register

Definition at line 79 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::ADDRB

Page Erase/Write Address Buffer

Definition at line 54 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::BOOTLOADERCTRL

Bootloader Read and Write Enable, Write Once Register

Definition at line 78 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::CACHECMD

Flash Cache Command Register

Definition at line 65 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::CACHECONFIG0

Cache Configuration Register 0

Definition at line 80 of file efm32tg11b_msc.h .

__IM uint32_t MSC_TypeDef::CACHEHITS

Cache Hits Performance Counter

Definition at line 66 of file efm32tg11b_msc.h .

__IM uint32_t MSC_TypeDef::CACHEMISSES

Cache Misses Performance Counter

Definition at line 67 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::CMD

Command Register

Definition at line 75 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::CTRL

Memory System Control Register

Definition at line 50 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::IEN

Interrupt Enable Register

Definition at line 63 of file efm32tg11b_msc.h .

__IM uint32_t MSC_TypeDef::IF

Interrupt Flag Register

Definition at line 60 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::IFC

Interrupt Flag Clear Register

Definition at line 62 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::IFS

Interrupt Flag Set Register

Definition at line 61 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::IRQLATENCY

Irq Latency Register

Definition at line 71 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::LOCK

Configuration Lock Register

Definition at line 64 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::MASSLOCK

Mass Erase Lock Register

Definition at line 70 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::READCTRL

Read Control Register

Definition at line 51 of file efm32tg11b_msc.h .

uint32_t MSC_TypeDef::RESERVED0[1U]

Reserved for future use

Definition at line 55 of file efm32tg11b_msc.h .

uint32_t MSC_TypeDef::RESERVED1[4U]

Reserved for future use

Definition at line 59 of file efm32tg11b_msc.h .

uint32_t MSC_TypeDef::RESERVED2[1U]

Reserved for future use

Definition at line 69 of file efm32tg11b_msc.h .

uint32_t MSC_TypeDef::RESERVED3[5U]

Reserved for future use

Definition at line 74 of file efm32tg11b_msc.h .

uint32_t MSC_TypeDef::RESERVED4[6U]

Reserved for future use

Definition at line 77 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::STARTUP

Startup Control

Definition at line 72 of file efm32tg11b_msc.h .

__IM uint32_t MSC_TypeDef::STATUS

Status Register

Definition at line 57 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::WDATA

Write Data Register

Definition at line 56 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::WRITECMD

Write Command Register

Definition at line 53 of file efm32tg11b_msc.h .

__IOM uint32_t MSC_TypeDef::WRITECTRL

Write Control Register

Definition at line 52 of file efm32tg11b_msc.h .

The documentation for this struct was generated from the following file:
  • C:/repos/embsw_super_h1/platform/Device/SiliconLabs/EFM32TG11B/Include/ efm32tg11b_msc.h