PartDevices > EFM32TG11B520F128GM80
Macros |
|
#define | __CM0PLUS_REV 0x0001U |
#define | _EFM32_TINY_FAMILY 1 |
#define | _EFM_DEVICE |
#define | _SILICON_LABS_32B_PLATFORM 2 |
#define | _SILICON_LABS_32B_PLATFORM_2 |
#define | _SILICON_LABS_32B_PLATFORM_2_GEN 1 |
#define | _SILICON_LABS_32B_PLATFORM_2_GEN_1 |
#define | _SILICON_LABS_32B_SERIES 1 |
#define | _SILICON_LABS_32B_SERIES_1 |
#define | _SILICON_LABS_32B_SERIES_1_CONFIG 1 |
#define | _SILICON_LABS_32B_SERIES_1_CONFIG_1 |
#define | _SILICON_LABS_GECKO_INTERNAL_SDID 103 |
#define | _SILICON_LABS_GECKO_INTERNAL_SDID_103 |
#define | ACMP_COUNT 2 |
#define | ACMP_PRESENT |
#define | ADC_COUNT 1 |
#define | ADC_PRESENT |
#define | AFACHAN_MAX 140U |
#define | AFCHAN_MAX 120U |
#define | AFCHANLOC_MAX 8U |
#define | BOOTLOADER_COUNT 1 |
#define | BOOTLOADER_PRESENT |
#define | BU_COUNT 1 |
#define | BU_PRESENT |
#define | CAN_COUNT 1 |
#define | CAN_PRESENT |
#define | CMU_COUNT 1 |
#define | CMU_PRESENT |
#define | CRYOTIMER_COUNT 1 |
#define | CRYOTIMER_PRESENT |
#define | CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) |
#define | CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) |
#define | CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) |
#define | CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) |
#define | CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) |
#define | CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) |
#define | CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) |
#define | CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) |
#define | CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) |
#define | CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) |
#define | CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) |
#define | CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) |
#define | CRYPTO_COUNT 1 |
#define | CRYPTO_PRESENT |
#define | CSEN_COUNT 1 |
#define | CSEN_PRESENT |
#define | DCDC_COUNT 1 |
#define | DCDC_PRESENT |
#define | DEVICE_MEM_BASE ((uint32_t) 0xF0040000UL) |
#define | DEVICE_MEM_BITS ((uint32_t) 0x0000000CUL) |
#define | DEVICE_MEM_END ((uint32_t) 0xF0040FFFUL) |
#define | DEVICE_MEM_SIZE ((uint32_t) 0x1000UL) |
#define | DMA_CHAN_COUNT 8 |
#define | EMU_COUNT 1 |
#define | EMU_PRESENT |
#define | EXT_IRQ_COUNT 32 |
#define | FLASH_BASE (0x00000000UL) |
#define | FLASH_MEM_BASE ((uint32_t) 0x00000000UL) |
#define | FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) |
#define | FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) |
#define | FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) |
#define | FLASH_PAGE_SIZE 2048U |
#define | FLASH_SIZE (0x00020000UL) |
#define | GPCRC_COUNT 1 |
#define | GPCRC_PRESENT |
#define | GPIO_COUNT 1 |
#define | GPIO_PRESENT |
#define | I2C_COUNT 2 |
#define | I2C_PRESENT |
#define | LCD_COUNT 1 |
#define | LCD_PRESENT |
#define | LDMA_COUNT 1 |
#define | LDMA_PRESENT |
#define | LESENSE_COUNT 1 |
#define | LESENSE_PRESENT |
#define | LETIMER_COUNT 1 |
#define | LETIMER_PRESENT |
#define | LEUART_COUNT 1 |
#define | LEUART_PRESENT |
#define | MSC_COUNT 1 |
#define | MSC_PRESENT |
#define | MTB_COUNT 1 |
#define | MTB_PRESENT |
#define | PART_NUMBER "EFM32TG11B520F128GM80" |
#define | PCNT_COUNT 1 |
#define | PCNT_PRESENT |
#define | PER1_BITCLR_MEM_BASE ((uint32_t) 0x44050000UL) |
#define | PER1_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) |
#define | PER1_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) |
#define | PER1_BITCLR_MEM_SIZE ((uint32_t) 0xA0000UL) |
#define | PER1_BITSET_MEM_BASE ((uint32_t) 0x46050000UL) |
#define | PER1_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) |
#define | PER1_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) |
#define | PER1_BITSET_MEM_SIZE ((uint32_t) 0xA0000UL) |
#define | PER1_MEM_BASE ((uint32_t) 0x40050000UL) |
#define | PER1_MEM_BITS ((uint32_t) 0x00000014UL) |
#define | PER1_MEM_END ((uint32_t) 0x400EFFFFUL) |
#define | PER1_MEM_SIZE ((uint32_t) 0xA0000UL) |
#define | PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) |
#define | PER_BITCLR_MEM_BITS ((uint32_t) 0x00000013UL) |
#define | PER_BITCLR_MEM_END ((uint32_t) 0x4404FFFFUL) |
#define | PER_BITCLR_MEM_SIZE ((uint32_t) 0x50000UL) |
#define | PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) |
#define | PER_BITSET_MEM_BITS ((uint32_t) 0x00000013UL) |
#define | PER_BITSET_MEM_END ((uint32_t) 0x4604FFFFUL) |
#define | PER_BITSET_MEM_SIZE ((uint32_t) 0x50000UL) |
#define | PER_MEM_BASE ((uint32_t) 0x40000000UL) |
#define | PER_MEM_BITS ((uint32_t) 0x00000013UL) |
#define | PER_MEM_END ((uint32_t) 0x4004FFFFUL) |
#define | PER_MEM_SIZE ((uint32_t) 0x50000UL) |
#define | PRS_CHAN_COUNT 8 |
#define | PRS_COUNT 1 |
#define | PRS_PRESENT |
#define | RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) |
#define | RAM0_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) |
#define | RAM0_CODE_MEM_END ((uint32_t) 0x10007FFFUL) |
#define | RAM0_CODE_MEM_SIZE ((uint32_t) 0x8000UL) |
#define | RAM0_MEM_BASE ((uint32_t) 0x20000000UL) |
#define | RAM0_MEM_BITS ((uint32_t) 0x0000000FUL) |
#define | RAM0_MEM_END ((uint32_t) 0x20007FFFUL) |
#define | RAM0_MEM_SIZE ((uint32_t) 0x8000UL) |
#define | RAM_MEM_BASE ((uint32_t) 0x20000000UL) |
#define | RAM_MEM_BITS ((uint32_t) 0x0000000FUL) |
#define | RAM_MEM_END ((uint32_t) 0x20007FFFUL) |
#define | RAM_MEM_SIZE ((uint32_t) 0x8000UL) |
#define | RMU_COUNT 1 |
#define | RMU_PRESENT |
#define | RTCC_COUNT 1 |
#define | RTCC_PRESENT |
#define | SMU_COUNT 1 |
#define | SMU_PRESENT |
#define | SRAM_BASE (0x20000000UL) |
#define | SRAM_SIZE (0x00008000UL) |
#define | TIMER_COUNT 2 |
#define | TIMER_PRESENT |
#define | TRNG_COUNT 1 |
#define | TRNG_PRESENT |
#define | UART_COUNT 1 |
#define | UART_PRESENT |
#define | USART_COUNT 4 |
#define | USART_PRESENT |
#define | VDAC_COUNT 1 |
#define | VDAC_PRESENT |
#define | WDOG_COUNT 1 |
#define | WDOG_PRESENT |
#define | WTIMER_COUNT 2 |
#define | WTIMER_PRESENT |
Macro Definition Documentation
#define __CM0PLUS_REV 0x0001U |
Cortex-M0+ Core revision r0p1
Definition at line
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#define _EFM32_TINY_FAMILY 1 |
Part family Tiny Gecko MCU Family
Definition at line
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#define _EFM_DEVICE |
Silicon Labs EFM-type MCU
Definition at line
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#define _SILICON_LABS_32B_PLATFORM 2 |
Silicon Labs platform name
Definition at line
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#define _SILICON_LABS_32B_PLATFORM_2 |
Silicon Labs platform name
Definition at line
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#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 |
-
Deprecated:
- Platform 2, generation 1
Definition at line
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#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 |
-
Deprecated:
- Platform 2, generation 1
Definition at line
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#define _SILICON_LABS_32B_SERIES 1 |
Silicon Labs series number
Definition at line
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#define _SILICON_LABS_32B_SERIES_1 |
Silicon Labs series number
Definition at line
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#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 |
Series 1, Configuration 1
Definition at line
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#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 |
Series 1, Configuration 1
Definition at line
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#define _SILICON_LABS_GECKO_INTERNAL_SDID 103 |
Silicon Labs internal use only, may change any time
Definition at line
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#define _SILICON_LABS_GECKO_INTERNAL_SDID_103 |
Silicon Labs internal use only, may change any time
Definition at line
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#define ACMP_COUNT 2 |
2 ACMPs available
Definition at line
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#define ACMP_PRESENT |
ACMP is available in this part
Definition at line
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#define ADC_COUNT 1 |
1 ADCs available
Definition at line
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#define ADC_PRESENT |
ADC is available in this part
Definition at line
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#define AFACHAN_MAX 140U |
Analog AF channels
Definition at line
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#define AFCHAN_MAX 120U |
AF channels connect the different on-chip peripherals with the af-mux
Definition at line
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#define AFCHANLOC_MAX 8U |
AF channel maximum location number
Definition at line
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Referenced by GPIO_DbgLocationSet() .
#define BOOTLOADER_COUNT 1 |
1 BOOTLOADER available
Definition at line
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#define BOOTLOADER_PRESENT |
BOOTLOADER is available in this part
Definition at line
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#define BU_COUNT 1 |
1 BU available
Definition at line
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#define BU_PRESENT |
BU is available in this part
Definition at line
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#define CAN_COUNT 1 |
1 CANs available
Definition at line
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#define CAN_PRESENT |
CAN is available in this part
Definition at line
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#define CMU_COUNT 1 |
1 CMU available
Definition at line
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#define CMU_PRESENT |
CMU is available in this part
Definition at line
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#define CRYOTIMER_COUNT 1 |
1 CRYOTIMER available
Definition at line
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#define CRYOTIMER_PRESENT |
CRYOTIMER is available in this part
Definition at line
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#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) |
CRYPTO0_BITCLR base address
Definition at line
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#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO0_BITCLR used bits
Definition at line
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#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) |
CRYPTO0_BITCLR end address
Definition at line
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of file
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#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO0_BITCLR available address space
Definition at line
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#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) |
CRYPTO0_BITSET base address
Definition at line
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#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO0_BITSET used bits
Definition at line
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#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) |
CRYPTO0_BITSET end address
Definition at line
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#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO0_BITSET available address space
Definition at line
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#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) |
CRYPTO0 base address
Definition at line
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#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO0 used bits
Definition at line
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#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) |
CRYPTO0 end address
Definition at line
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#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO0 available address space
Definition at line
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#define CRYPTO_COUNT 1 |
1 CRYPTOs available
Definition at line
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#define CRYPTO_PRESENT |
CRYPTO is available in this part
Definition at line
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#define CSEN_COUNT 1 |
1 CSEN available
Definition at line
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#define CSEN_PRESENT |
CSEN is available in this part
Definition at line
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#define DCDC_COUNT 1 |
1 DCDC available
Definition at line
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#define DCDC_PRESENT |
DCDC is available in this part
Definition at line
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#define DEVICE_MEM_BASE ((uint32_t) 0xF0040000UL) |
DEVICE base address
Definition at line
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#define DEVICE_MEM_BITS ((uint32_t) 0x0000000CUL) |
DEVICE used bits
Definition at line
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#define DEVICE_MEM_END ((uint32_t) 0xF0040FFFUL) |
DEVICE end address
Definition at line
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#define DEVICE_MEM_SIZE ((uint32_t) 0x1000UL) |
DEVICE available address space
Definition at line
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#define DMA_CHAN_COUNT 8 |
Number of DMA channels
Definition at line
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Referenced by NANDFLASH_Init() .
#define EMU_COUNT 1 |
1 EMU available
Definition at line
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#define EMU_PRESENT |
EMU is available in this part
Definition at line
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#define EXT_IRQ_COUNT 32 |
Number of External (NVIC) interrupts
Definition at line
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Referenced by CORE_GetNvicRamTableHandler() , CORE_IrqIsBlocked() , CORE_NvicIRQDisabled() , CORE_NvicMaskClearIRQ() , CORE_NvicMaskSetIRQ() , and CORE_SetNvicRamTableHandler() .
#define FLASH_BASE (0x00000000UL) |
Flash and SRAM limits for EFM32TG11B520F128GM80 Flash Base Address
Definition at line
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#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) |
Memory Base addresses and limits FLASH base address
Definition at line
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#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) |
FLASH used bits
Definition at line
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#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) |
FLASH end address
Definition at line
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#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) |
FLASH available address space
Definition at line
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#define FLASH_PAGE_SIZE 2048U |
Flash Memory page size
Definition at line
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Referenced by MSC_ErasePage() , and SYSTEM_GetFlashPageSize() .
#define FLASH_SIZE (0x00020000UL) |
Available Flash Memory
Definition at line
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#define GPCRC_COUNT 1 |
1 GPCRC available
Definition at line
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#define GPCRC_PRESENT |
GPCRC is available in this part
Definition at line
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#define GPIO_COUNT 1 |
1 GPIO available
Definition at line
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#define GPIO_PRESENT |
GPIO is available in this part
Definition at line
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#define I2C_COUNT 2 |
2 I2Cs available
Definition at line
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#define I2C_PRESENT |
I2C is available in this part
Definition at line
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#define LCD_COUNT 1 |
1 LCD available
Definition at line
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#define LCD_PRESENT |
LCD is available in this part
Definition at line
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#define LDMA_COUNT 1 |
1 LDMA available
Definition at line
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#define LDMA_PRESENT |
LDMA is available in this part
Definition at line
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#define LESENSE_COUNT 1 |
1 LESENSE available
Definition at line
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#define LESENSE_PRESENT |
LESENSE is available in this part
Definition at line
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#define LETIMER_COUNT 1 |
1 LETIMERs available
Definition at line
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#define LETIMER_PRESENT |
LETIMER is available in this part
Definition at line
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#define LEUART_COUNT 1 |
1 LEUARTs available
Definition at line
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#define LEUART_PRESENT |
LEUART is available in this part
Definition at line
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#define MSC_COUNT 1 |
1 MSC available
Definition at line
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#define MSC_PRESENT |
MSC is available in this part
Definition at line
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#define MTB_COUNT 1 |
1 MTB available
Definition at line
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of file
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#define MTB_PRESENT |
MTB is available in this part
Definition at line
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#define PART_NUMBER "EFM32TG11B520F128GM80" |
Configure part number Part Number
Definition at line
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#define PCNT_COUNT 1 |
1 PCNTs available
Definition at line
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of file
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Referenced by CMU_PCNTClockExternalSet() .
#define PCNT_PRESENT |
PCNT is available in this part
Definition at line
236
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#define PER1_BITCLR_MEM_BASE ((uint32_t) 0x44050000UL) |
PER1_BITCLR base address
Definition at line
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of file
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#define PER1_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) |
PER1_BITCLR used bits
Definition at line
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#define PER1_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) |
PER1_BITCLR end address
Definition at line
159
of file
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#define PER1_BITCLR_MEM_SIZE ((uint32_t) 0xA0000UL) |
PER1_BITCLR available address space
Definition at line
158
of file
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#define PER1_BITSET_MEM_BASE ((uint32_t) 0x46050000UL) |
PER1_BITSET base address
Definition at line
161
of file
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#define PER1_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) |
PER1_BITSET used bits
Definition at line
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of file
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#define PER1_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) |
PER1_BITSET end address
Definition at line
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of file
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#define PER1_BITSET_MEM_SIZE ((uint32_t) 0xA0000UL) |
PER1_BITSET available address space
Definition at line
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of file
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#define PER1_MEM_BASE ((uint32_t) 0x40050000UL) |
PER1 base address
Definition at line
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of file
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#define PER1_MEM_BITS ((uint32_t) 0x00000014UL) |
PER1 used bits
Definition at line
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of file
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#define PER1_MEM_END ((uint32_t) 0x400EFFFFUL) |
PER1 end address
Definition at line
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#define PER1_MEM_SIZE ((uint32_t) 0xA0000UL) |
PER1 available address space
Definition at line
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#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) |
PER_BITCLR base address
Definition at line
153
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Referenced by BUS_RegMaskedClear() .
#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000013UL) |
PER_BITCLR used bits
Definition at line
156
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#define PER_BITCLR_MEM_END ((uint32_t) 0x4404FFFFUL) |
PER_BITCLR end address
Definition at line
155
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#define PER_BITCLR_MEM_SIZE ((uint32_t) 0x50000UL) |
PER_BITCLR available address space
Definition at line
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#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) |
PER_BITSET base address
Definition at line
173
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Referenced by BUS_RegMaskedSet() .
#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000013UL) |
PER_BITSET used bits
Definition at line
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#define PER_BITSET_MEM_END ((uint32_t) 0x4604FFFFUL) |
PER_BITSET end address
Definition at line
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#define PER_BITSET_MEM_SIZE ((uint32_t) 0x50000UL) |
PER_BITSET available address space
Definition at line
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#define PER_MEM_BASE ((uint32_t) 0x40000000UL) |
PER base address
Definition at line
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Referenced by BUS_RegBitRead() , BUS_RegBitWrite() , BUS_RegMaskedClear() , and BUS_RegMaskedSet() .
#define PER_MEM_BITS ((uint32_t) 0x00000013UL) |
PER used bits
Definition at line
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#define PER_MEM_END ((uint32_t) 0x4004FFFFUL) |
PER end address
Definition at line
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#define PER_MEM_SIZE ((uint32_t) 0x50000UL) |
PER available address space
Definition at line
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#define PRS_CHAN_COUNT 8 |
Number of PRS channels
Definition at line
207
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Referenced by PRS_GpioOutputLocation() , PRS_Reset() , and PRS_SourceSignalSet() .
#define PRS_COUNT 1 |
1 PRS available
Definition at line
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#define PRS_PRESENT |
PRS is available in this part
Definition at line
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#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) |
RAM0_CODE base address
Definition at line
145
of file
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#define RAM0_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) |
RAM0_CODE used bits
Definition at line
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#define RAM0_CODE_MEM_END ((uint32_t) 0x10007FFFUL) |
RAM0_CODE end address
Definition at line
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#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x8000UL) |
RAM0_CODE available address space
Definition at line
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of file
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#define RAM0_MEM_BASE ((uint32_t) 0x20000000UL) |
RAM0 base address
Definition at line
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#define RAM0_MEM_BITS ((uint32_t) 0x0000000FUL) |
RAM0 used bits
Definition at line
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#define RAM0_MEM_END ((uint32_t) 0x20007FFFUL) |
RAM0 end address
Definition at line
191
of file
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#define RAM0_MEM_SIZE ((uint32_t) 0x8000UL) |
RAM0 available address space
Definition at line
190
of file
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#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) |
Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips RAM base address
Definition at line
195
of file
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Referenced by EMU_RamPowerDown() .
#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) |
RAM used bits
Definition at line
198
of file
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#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) |
RAM end address
Definition at line
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of file
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#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) |
RAM available address space
Definition at line
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of file
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#define RMU_COUNT 1 |
1 RMU available
Definition at line
255
of file
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#define RMU_PRESENT |
RMU is available in this part
Definition at line
254
of file
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#define RTCC_COUNT 1 |
1 RTCC available
Definition at line
277
of file
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#define RTCC_PRESENT |
RTCC is available in this part
Definition at line
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of file
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#define SMU_COUNT 1 |
1 SMU available
Definition at line
281
of file
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#define SMU_PRESENT |
SMU is available in this part
Definition at line
280
of file
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#define SRAM_BASE (0x20000000UL) |
SRAM Base Address
Definition at line
204
of file
efm32tg11b520f128gm80.h
.
Referenced by BUS_RamBitRead() , BUS_RamBitWrite() , CORE_InitNvicVectorTable() , and EMU_RamPowerDown() .
#define SRAM_SIZE (0x00008000UL) |
Available SRAM Memory
Definition at line
205
of file
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Referenced by CORE_InitNvicVectorTable() , and EMU_RamPowerDown() .
#define TIMER_COUNT 2 |
2 TIMERs available
Definition at line
225
of file
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.
#define TIMER_PRESENT |
TIMER is available in this part
Definition at line
224
of file
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#define TRNG_COUNT 1 |
1 TRNGs available
Definition at line
249
of file
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#define TRNG_PRESENT |
TRNG is available in this part
Definition at line
248
of file
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#define UART_COUNT 1 |
1 UARTs available
Definition at line
231
of file
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#define UART_PRESENT |
UART is available in this part
Definition at line
230
of file
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#define USART_COUNT 4 |
4 USARTs available
Definition at line
229
of file
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#define USART_PRESENT |
USART is available in this part
Definition at line
228
of file
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#define VDAC_COUNT 1 |
1 VDACs available
Definition at line
245
of file
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#define VDAC_PRESENT |
VDAC is available in this part
Definition at line
244
of file
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#define WDOG_COUNT 1 |
1 WDOGs available
Definition at line
247
of file
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.
#define WDOG_PRESENT |
WDOG is available in this part
Definition at line
246
of file
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.
#define WTIMER_COUNT 2 |
2 WTIMERs available
Definition at line
227
of file
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.
#define WTIMER_PRESENT |
WTIMER is available in this part
Definition at line
226
of file
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.