Macros
#define	_DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL

#define	_DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8

#define	_DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL

#define	_DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24

#define	_DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL

#define	_DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL

#define	_DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4

#define	_DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL

#define	_DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20

#define	_DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL

#define	_DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0

#define	_DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL

#define	_DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16

#define	_DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL

#define	_DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24

#define	_DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL

#define	_DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8

#define	_DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL

#define	_DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL

#define	_DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20

#define	_DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL

#define	_DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4

#define	_DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL

#define	_DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16

#define	_DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL

#define	_DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0

#define	_DEVINFO_ADC0CAL2_MASK 0x000000FFUL

#define	_DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL

#define	_DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4

#define	_DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL

#define	_DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0

#define	_DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL

#define	_DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL

#define	_DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4

#define	_DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28

#define	_DEVINFO_CAL_CRC_MASK 0xFFFFUL

#define	_DEVINFO_CAL_CRC_SHIFT 0

#define	_DEVINFO_CAL_MASK 0x00FFFFFFUL

#define	_DEVINFO_CAL_TEMP_MASK 0xFF0000UL

#define	_DEVINFO_CAL_TEMP_SHIFT 16

#define	_DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL

#define	_DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL

#define	_DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16

#define	_DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL

#define	_DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0

#define	_DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL

#define	_DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8

#define	_DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL

#define	_DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16

#define	_DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL

#define	_DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24

#define	_DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL

#define	_DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL

#define	_DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0

#define	_DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL

#define	_DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8

#define	_DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24

#define	_DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL

#define	_DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL

#define	_DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0

#define	_DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL

#define	_DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16

#define	_DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL

#define	_DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8

#define	_DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL

#define	_DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24

#define	_DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL

#define	_DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL

#define	_DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0

#define	_DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL

#define	_DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16

#define	_DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL

#define	_DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8

#define	_DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL

#define	_DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24

#define	_DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL

#define	_DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL

#define	_DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0

#define	_DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL

#define	_DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16

#define	_DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL

#define	_DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8

#define	_DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL

#define	_DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24

#define	_DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL

#define	_DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL

#define	_DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0

#define	_DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL

#define	_DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16

#define	_DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL

#define	_DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8

#define	_DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL

#define	_DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24

#define	_DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL

#define	_DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL

#define	_DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0

#define	_DEVINFO_DEVINFOREV_MASK 0x000000FFUL

#define	_DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL

#define	_DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0

#define	_DEVINFO_EMUTEMP_MASK 0x000000FFUL

#define	_DEVINFO_EUI48H_MASK 0x0000FFFFUL

#define	_DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL

#define	_DEVINFO_EUI48H_OUI48H_SHIFT 0

#define	_DEVINFO_EUI48L_MASK 0xFFFFFFFFUL

#define	_DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL

#define	_DEVINFO_EUI48L_OUI48L_SHIFT 24

#define	_DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL

#define	_DEVINFO_EUI48L_UNIQUEID_SHIFT 0

#define	_DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL

#define	_DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL

#define	_DEVINFO_EXTINFO_CONNECTION_SHIFT 8

#define	_DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL

#define	_DEVINFO_EXTINFO_MASK 0x00FFFFFFUL

#define	_DEVINFO_EXTINFO_REV_MASK 0xFF0000UL

#define	_DEVINFO_EXTINFO_REV_NONE 0x000000FFUL

#define	_DEVINFO_EXTINFO_REV_REV1 0x00000001UL

#define	_DEVINFO_EXTINFO_REV_SHIFT 16

#define	_DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL

#define	_DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL

#define	_DEVINFO_EXTINFO_TYPE_MASK 0xFFUL

#define	_DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL

#define	_DEVINFO_EXTINFO_TYPE_SHIFT 0

#define	_DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL0_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL10_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL11_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL12_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL3_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL6_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL7_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL8_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28

#define	_DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24

#define	_DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL

#define	_DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL

#define	_DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0

#define	_DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL

#define	_DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8

#define	_DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL

#define	_DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16

#define	_DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL

#define	_DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24

#define	_DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL

#define	_DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24

#define	_DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL

#define	_DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL

#define	_DEVINFO_MEMINFO_PINCOUNT_SHIFT 16

#define	_DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL

#define	_DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL

#define	_DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL

#define	_DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL

#define	_DEVINFO_MEMINFO_PKGTYPE_SHIFT 8

#define	_DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL

#define	_DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL

#define	_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL

#define	_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL

#define	_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL

#define	_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL

#define	_DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0

#define	_DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL

#define	_DEVINFO_MODULEINFO_RESERVED1_MASK 0xFFFFFFFFUL

#define	_DEVINFO_MODULEINFO_RESERVED1_SHIFT 0

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