LESENSE_TypeDef Struct ReferenceDevices > LESENSE

LESENSE Register Declaration

Definition at line 49 of file efr32fg14p_lesense.h .

#include < efr32fg14p_lesense.h >

Data Fields

__IOM uint32_t ALTEXCONF
__IOM uint32_t BIASCTRL
LESENSE_BUF_TypeDef BUF [16U]
__IM uint32_t BUFDATA
LESENSE_CH_TypeDef CH [16U]
__IOM uint32_t CHEN
__IOM uint32_t CMD
__IOM uint32_t CTRL
__IM uint32_t CURCH
__IOM uint32_t DECCTRL
__IOM uint32_t DECSTATE
__IOM uint32_t EVALCTRL
__IOM uint32_t IDLECONF
__IOM uint32_t IEN
__IM uint32_t IF
__IOM uint32_t IFC
__IOM uint32_t IFS
__IOM uint32_t PERCTRL
__IOM uint32_t PRSCTRL
__IM uint32_t PTR
uint32_t RESERVED0 [2U]
uint32_t RESERVED1 [38U]
__IOM uint32_t ROUTEPEN
__IOM uint32_t SCANRES
__IOM uint32_t SENSORSTATE
LESENSE_ST_TypeDef ST [32U]
__IM uint32_t STATUS
__IM uint32_t SYNCBUSY
__IOM uint32_t TIMCTRL

Field Documentation

__IOM uint32_t LESENSE_TypeDef::ALTEXCONF

Alternative Excite Pin Configuration

Definition at line 67 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::BIASCTRL

Bias Control Register

Definition at line 54 of file efr32fg14p_lesense.h .

LESENSE_BUF_TypeDef LESENSE_TypeDef::BUF[16U]

Scanresult

Definition at line 79 of file efr32fg14p_lesense.h .

__IM uint32_t LESENSE_TypeDef::BUFDATA

Result Buffer Data Register

Definition at line 62 of file efr32fg14p_lesense.h .

LESENSE_CH_TypeDef LESENSE_TypeDef::CH[16U]

Scanconfig

Definition at line 81 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::CHEN

Channel Enable Register

Definition at line 58 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::CMD

Command Register

Definition at line 57 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::CTRL

Control Register

Definition at line 50 of file efr32fg14p_lesense.h .

__IM uint32_t LESENSE_TypeDef::CURCH

Current Channel Index

Definition at line 63 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::DECCTRL

Decoder Control Register

Definition at line 53 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::DECSTATE

Current Decoder State

Definition at line 64 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::EVALCTRL

LESENSE Evaluation Control

Definition at line 55 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::IDLECONF

GPIO Idle Phase Configuration

Definition at line 66 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::IEN

Interrupt Enable Register

Definition at line 72 of file efr32fg14p_lesense.h .

__IM uint32_t LESENSE_TypeDef::IF

Interrupt Flag Register

Definition at line 69 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::IFC

Interrupt Flag Clear Register

Definition at line 71 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::IFS

Interrupt Flag Set Register

Definition at line 70 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::PERCTRL

Peripheral Control Register

Definition at line 52 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::PRSCTRL

PRS Control Register

Definition at line 56 of file efr32fg14p_lesense.h .

__IM uint32_t LESENSE_TypeDef::PTR

Result Buffer Pointers

Definition at line 61 of file efr32fg14p_lesense.h .

uint32_t LESENSE_TypeDef::RESERVED0[2U]

Reserved for future use

Definition at line 68 of file efr32fg14p_lesense.h .

uint32_t LESENSE_TypeDef::RESERVED1[38U]

Reserved registers

Definition at line 76 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::ROUTEPEN

I/O Routing Register

Definition at line 74 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::SCANRES

Scan Result Register

Definition at line 59 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::SENSORSTATE

Decoder Input Register

Definition at line 65 of file efr32fg14p_lesense.h .

LESENSE_ST_TypeDef LESENSE_TypeDef::ST[32U]

Decoding states

Definition at line 77 of file efr32fg14p_lesense.h .

__IM uint32_t LESENSE_TypeDef::STATUS

Status Register

Definition at line 60 of file efr32fg14p_lesense.h .

__IM uint32_t LESENSE_TypeDef::SYNCBUSY

Synchronization Busy Register

Definition at line 73 of file efr32fg14p_lesense.h .

__IOM uint32_t LESENSE_TypeDef::TIMCTRL

Timing Control Register

Definition at line 51 of file efr32fg14p_lesense.h .


The documentation for this struct was generated from the following file:
  • C:/repos/embsw_super_h1/platform/Device/SiliconLabs/EFR32FG14P/Include/ efr32fg14p_lesense.h