Functions and definitions specific to the breakout board.

Macros
#define	PWRUP_CFG_SC1_TXD GPIO_P_CFGz_Pxy_OUT_ALT
	Give GPIO SC1 TXD and nRTS configurations friendly names.

#define	PWRDN_OUT_SC1_nRTS 1

Custom Baud Rate Definitions
Application Framework NCP Configuration Board Header This board header (dev0680) is not supported in framework NCP applications. NCP applications must use either the dev0680spi or dev0680uart board headers when creating custom NCP applications through the framework. The following define is used with defining a custom baud rate for the UART. This define provides a simple hook into the definition of the baud rates used with the UART. The baudSettings[] array in uart.c links the BAUD_* defines with the actual register values needed for operating the UART. The array baudSettings[] can be edited directly for a custom baud rate or another entry (the register settings) can be provided here with this define.
#define	EMBER_SERIAL_BAUD_CUSTOM 13
	This define is the register setting for generating a baud of.

LED Definitions
The following are used to aid in the abstraction with the LED connections. The microcontroller-specific sources use these definitions so they are able to work across a variety of boards which could have different connections. The names and ports/pins used below are intended to match with a schematic of the system to provide the abstraction. The HalBoardLedPins enum values should always be used when manipulating the state of LEDs, as they directly refer to the GPIOs to which the LEDs are connected. Note: LEDs 0 and 1 are on the RCM. Note: LED 2 is on the breakout board (dev0680). Note: LED 3 simply redirects to LED 2.
enum	HalBoardLedPins { BOARDLED0 = PORTA_PIN(6), BOARDLED1 = PORTA_PIN(7), BOARDLED2 = PORTC_PIN(5), BOARDLED3 = BOARDLED2, BOARD_ACTIVITY_LED = BOARDLED0, BOARD_HEARTBEAT_LED = BOARDLED1, BOARDLED0 = PORTA_PIN(6), BOARDLED1 = PORTA_PIN(7), BOARDLED2 = PORTC_PIN(5), BOARDLED3 = BOARDLED2, BOARD_ACTIVITY_LED = BOARDLED0, BOARD_HEARTBEAT_LED = BOARDLED1 }
	Assign each GPIO with an LED connected to a convenient name. BOARD_ACTIVITY_LED and BOARD_HEARTBEAT_LED provide a further layer of abstraction on top of the 3 LEDs for verbose coding.

Button Definitions
The following are used to aid in the abstraction with the Button connections. The microcontroller-specific sources use these definitions so they are able to work across a variety of boards which could have different connections. The names and ports/pins used below are intended to match with a schematic of the system to provide the abstraction. The BUTTONn macros should always be used with manipulating the buttons as they directly refer to the GPIOs to which the buttons are connected. Note The GPIO number must match the IRQ letter
#define	BUTTON0 PORTB_PIN(6)
	The actual GPIO BUTTON0 is connected to. This define should be used whenever referencing BUTTON0.

#define	BUTTON0_IN (GPIO->P[1].IN)
	The GPIO input register for BUTTON0.

#define	BUTTON0_SEL () do {} while (0)
	Point the proper IRQ at the desired pin for BUTTON0.

#define	BUTTON0_ISR halIrqBIsr
	The interrupt service routine for BUTTON0.

#define	BUTTON0_INTCFG (EVENT_GPIO->CFGB)
	The interrupt configuration register for BUTTON0.

#define	BUTTON0_INT_EN_IRQN IRQB_IRQn
	The interrupt enable bit for BUTTON0.

#define	BUTTON0_INT_EN_BIT BIT32 ( BUTTON0_INT_EN_IRQN )
	The actual GPIO BUTTON0 is connected to. This define should be used whenever referencing BUTTON0.

#define	BUTTON0_FLAG_BIT EVENT_GPIO_FLAG_IRQB
	The interrupt flag bit for BUTTON0.

#define	BUTTON0_MISS_BIT EVENT_MISS_MISS_IRQB
	The missed interrupt bit for BUTTON0.

#define	BUTTON1 PORTC_PIN(6)
	The actual GPIO BUTTON1 is connected to. This define should be used whenever referencing BUTTON1, such as controlling if pieces are compiled in. Remember there may be other things that might want to use IRQC.

#define	BUTTON1_IN (GPIO->P[2].IN)
	The GPIO input register for BUTTON1.

#define	BUTTON1_SEL () do { GPIO->IRQCSEL = PORTC_PIN(6); } while (0)
	Point the proper IRQ at the desired pin for BUTTON1. Remember there may be other things that might want to use IRQC.

#define	BUTTON1_ISR halIrqCIsr
	The interrupt service routine for BUTTON1. Remember there may be other things that might want to use IRQC.

#define	BUTTON1_INTCFG (EVENT_GPIO->CFGC)
	The interrupt configuration register for BUTTON1.

#define	BUTTON1_INT_EN_IRQN IRQC_IRQn
	The interrupt enable bit for BUTTON1.

#define	BUTTON1_INT_EN_BIT BIT32 ( BUTTON1_INT_EN_IRQN )
	The actual GPIO BUTTON0 is connected to. This define should be used whenever referencing BUTTON0.

#define	BUTTON1_FLAG_BIT EVENT_GPIO_FLAG_IRQC
	The interrupt flag bit for BUTTON1.

#define	BUTTON1_MISS_BIT EVENT_MISS_MISS_IRQC
	The missed interrupt bit for BUTTON1.

USB Power State
Define if the USB is self powered or bus powered since the configuration descriptor needs to report to the host the powered state. Note VBUS Monitoring is required for USB to function when the EM358 device is configured as self-powered.
#define	USB_SELFPWRD_STATE (1)
	The USB power state.

USB Remote Wakeup Enable
If the USB device needs to awake the host from suspend, then it needs to have remote wakeup enable. Note The host can deny remote wakeup, keeping the device in suspend. If the device has remote wakeup enabled the configuration descriptor needs to report this fact to the host. Additionally, the USB core in the chip needs to be directly told. Set the define USB_REMOTEWKUPEN_STATE to 0 if remote wake is disabled or 1 if enabled.
#define	USB_REMOTEWKUPEN_STATE (1)
	USB Remote Wakeup Enable.

USB Maximum Power Consumption
The USB device must report the maximum power it will draw from the bus. This is done via the bMaxPower parameter in the Configuration Descriptor reported to the host. The value used is in units of 2mA. Self-powered devices are low power devices and must draw less than 100mA. Systems that have components such as a FEM are likely to consume more than 100mA and are considered high power and therefore must be bus-powered.
#define	USB_MAX_POWER (50)
	USB Max Power parameter (bMaxPower) the driver will report to the host in the Configuration Descriptor.

USB Enumeration Control
The following are used to aid in the abstraction of which GPIO is used for controlloing the pull-up resistor for enumeation. The hardware setup connects the D+ signal to a GPIO via a 1.5kOhm pull-up resistor. Any GPIO can be used since it just needs to be a simple push-pull output configuration.
#define	ENUMCTRL PORTA_PIN(2)
	The actual GPIO ENUMCTRL is connected to. The GPIO only needs to be a simple push-pull output or input.

#define	ENUMCTRL_SETCFG (cfg)
	Set the GPIO's configuration to the provided state. The two states used are GPIO_P_CFGz_Pxy_OUT when the device is enumerated and GPIO_P_CFGz_Pxy_IN when the device is not enumerated.

#define	ENUMCTRL_SET () do { GPIO->P[0].SET = GPIO_P_SET_Px2; } while (0)
	When the GPIO used for enumeration is configured as push-pull, this macro makes it easy to set the output state high.

#define	ENUMCTRL_CLR () do { GPIO->P[0].CLR = GPIO_P_CLR_Px2; } while (0)
	When the GPIO used for enumeration is configured as push-pull, this macro makes it easy to clear the output state low.

USB VBUS Monitoring Support
Note VBUS Monitoring is required for USB to function when the EM358 device is configured as self-powered. The following are used to aid in the abstraction of which GPIO and IRQ is used for VBUS Monitoring. Remember that IRQA and IRQB are fixed to GPIO PB0 and PB6 respectively while IRQC and IRQD can be assigned to any GPIO. Since USB's D- and D+ data pins are fixed to PA0 and PA1 respectively, SC2 can't be used so it makes sense to allocate PA2 for enumeration control and PA3 for VBUS monitoring. Therefore, using PA3 for VBUS monitoring requires IRQC or IRQD. The driver will only try to use VBUSMON functionality if USB_SELFPWRD_STATE is set to 1.
#define	VBUSMON GPIO_P_IN_Px3
	The actual GPIO VBUSMON is connected to. Remember that other pieces might want to use PA3.

#define	VBUSMON_IN (GPIO->P[0].IN)
	The GPIO input register for VBUSMON.

#define	VBUSMON_SETCFG ()
	The GPIO configuration needed for VBUSMON. The configuration needs to be a simple input that will monitor for edge tansitions.

#define	VBUSMON_SEL () do { GPIO->IRQDSEL = PORTA_PIN(3); } while (0)
	Point the proper IRQ at the desired pin for VBUSMON. Remember that other pieces that might want to use IRQC.

#define	VBUSMON_ISR halIrqDIsr
	The interrupt service routine for VBUSMON. Remember that other pieces that might want to use IRQC.

#define	VBUSMON_INTCFG (EVENT_GPIO->CFGD)
	The interrupt configuration register for VBUSMON.

#define	VBUSMON_INT_EN_IRQN IRQD_IRQn
	The interrupt enable bit for VBUSMON.

#define	VBUSMON_INT_EN_BIT BIT32 ( VBUSMON_INT_EN_IRQN )
	The actual GPIO VBUSMON is connected to. Remember that other pieces might want to use PA3.

#define	VBUSMON_FLAG_BIT EVENT_GPIO_FLAG_IRQD
	The interrupt flag bit for VBUSMON.

#define	VBUSMON_MISS_BIT EVENT_MISS_MISS_IRQD
	The missed interrupt bit for VBUSMON.

Radio HoldOff Configuration Definitions
This define does not equate to anything. It is used as a trigger to enable Radio HoldOff support. The following are used to aid in the abstraction with Radio HoldOff (RHO). The microcontroller-specific sources use these definitions so they are able to work across a variety of boards which could have different connections. The names and ports/pins used below are intended to match with a schematic of the system to provide the abstraction. The Radio HoldOff input GPIO is abstracted like BUTTON0/1.
#define	RHO_ASSERTED 1
	The actual GPIO used to control Radio HoldOff.

#define	RHO_CFG (GPIO->P[0].CFGH)
	The GPIO configuration register for Radio HoldOff.

#define	RHO_IN (GPIO->P[0].IN)
	The GPIO input register for Radio HoldOff.

#define	RHO_OUT (GPIO->P[0].OUT)
	The GPIO output register for Radio HoldOff.

#define	RHO_SEL () do { GPIO->IRQDSEL = RHO_GPIO ; } while (0)
	Point the proper IRQ at the desired pin for Radio HoldOff. Remember there may be other things that might want to use this IRQ.

#define	RHO_ISR halIrqDIsr
	The interrupt service routine for Radio HoldOff. Remember there may be other things that might want to use this IRQ.

#define	RHO_INTCFG (EVENT_GPIO->CFGD)
	The interrupt configuration register for Radio HoldOff.

#define	RHO_INT_EN_IRQN IRQD_IRQn
	The interrupt enable bit for Radio HoldOff.

#define	RHO_INT_EN_BIT BIT32 ( RHO_INT_EN_IRQN )
	The actual GPIO used to control Radio HoldOff.

#define	RHO_FLAG_BIT EVENT_GPIO_FLAG_IRQD
	The interrupt flag bit for Radio HoldOff.

#define	RHO_MISS_BIT EVENT_MISS_MISS_IRQD
	The missed interrupt bit for Radio HoldOff.

#define	PWRUP_CFG_DFL_RHO_FOR_RHO GPIO_P_CFGz_Pxy_IN_PUD
	Configuration of GPIO for Radio HoldOff operation.

#define	PWRUP_OUT_DFL_RHO_FOR_RHO GPIO_P_OUT_Pxy_PULLDOWN /* Deassert */
	The actual GPIO used to control Radio HoldOff.

#define	PWRDN_CFG_DFL_RHO_FOR_RHO GPIO_P_CFGz_Pxy_IN_PUD
	The actual GPIO used to control Radio HoldOff.

#define	PWRDN_OUT_DFL_RHO_FOR_RHO GPIO_P_OUT_Pxy_PULLDOWN /* Deassert */
	The actual GPIO used to control Radio HoldOff.

#define	PWRUP_CFG_DFL_RHO_FOR_DFL GPIO_P_CFGz_Pxy_OUT
	Configuration of GPIO for default behavior.

#define	PWRUP_OUT_DFL_RHO_FOR_DFL 1 /* LED default off */
	The actual GPIO used to control Radio HoldOff.

#define	PWRDN_CFG_DFL_RHO_FOR_DFL GPIO_P_CFGz_Pxy_OUT
	The actual GPIO used to control Radio HoldOff.

#define	PWRDN_OUT_DFL_RHO_FOR_DFL 1 /* LED off */
	The actual GPIO used to control Radio HoldOff.

#define	PWRUP_CFG_DFL_RHO PWRUP_CFG_DFL_RHO_FOR_DFL
	The following definitions are helpers for managing Radio HoldOff and should not be modified.

#define	PWRUP_OUT_DFL_RHO PWRUP_OUT_DFL_RHO_FOR_DFL
	The actual GPIO used to control Radio HoldOff.

#define	PWRDN_CFG_DFL_RHO PWRDN_CFG_DFL_RHO_FOR_DFL
	The actual GPIO used to control Radio HoldOff.

#define	PWRDN_OUT_DFL_RHO PWRDN_OUT_DFL_RHO_FOR_DFL
	The actual GPIO used to control Radio HoldOff.

#define	halInternalInitRadioHoldOff () /* no-op */
	The actual GPIO used to control Radio HoldOff.

Temperature sensor ADC channel
Define the analog input channel connected to the LM-20 temperature sensor. The scale factor compensates for different platform input ranges. PB5/ADC0 must be an analog input. PC7 must be an output and set to a high level to power the sensor.
#define	TEMP_SENSOR_ADC_CHANNEL ADC_SOURCE_ADC0_VREF2
	The analog input channel to use for the temperature sensor.

#define	TEMP_SENSOR_SCALE_FACTOR 1
	The scale factor to compensate for different input ranges.

Packet Trace
When PACKET_TRACE is defined, ::GPIO->P[0].CFGH will automatically be setup by halInit() to enable Packet Trace support on PA4 and PA5, in addition to the configuration specified below. Note This define will override any settings for PA4 and PA5.
#define	PACKET_TRACE
	This define does not equate to anything. It is used as a trigger to enable Packet Trace support on the breakout board (dev0680).

ENABLE_OSC32K

When ENABLE_OSC32K is defined, halInit() will configure system timekeeping to utilize the external 32.768 kHz crystal oscillator rather than the internal 1 kHz RC oscillator.

Note: ENABLE_OSC32K is mutually exclusive with ENABLE_ALT_FUNCTION_NTX_ACTIVE since they define conflicting usage of GPIO PC6.

On initial powerup the 32.768 kHz crystal oscillator will take a little while to start stable oscillation. This only happens on initial powerup, not on wake-from-sleep, since the crystal usually stays running in deep sleep mode.

When ENABLE_OSC32K is defined the crystal oscillator is started as part of halInit() . After the crystal is started we delay for OSC32K_STARTUP_DELAY_MS (time in milliseconds). This delay allows the crystal oscillator to stabilize before we start using it for system timing.

If you set OSC32K_STARTUP_DELAY_MS to less than the crystal's startup time:

The system timer won't produce a reliable one millisecond tick before the crystal is stable.
You may see some number of ticks of unknown period occur before the crystal is stable.
halInit() will complete and application code will begin running, but any events based on the system timer will not be accurate until the crystal is stable.
An unstable system timer will only affect the APIs in system-timer.h .

Typical 32.768 kHz crystals measured by Ember take about 400 milliseconds to stabilize. Be sure to characterize your particular crystal's stabilization time since crystal behavior can vary.

#define OSC32K_STARTUP_DELAY_MS (0)

Packet Trace Configuration Defines
Provide the proper set of pin configuration for when the Packet Trace is enabled (look above for the define which enables it). When Packet Trace is not enabled, leave the two PTI pins in their default configuration. If Packet Trace is not being used, feel free to set the pin configurations as desired. The config shown here is simply the Power On Reset defaults.
#define	PWRUP_CFG_PTI_EN GPIO_P_CFGz_Pxy_OUT_ALT
	Give the packet trace configuration a friendly name.

#define	PWRUP_OUT_PTI_EN 0
	Give the packet trace configuration a friendly name.

#define	PWRDN_CFG_PTI_EN GPIO_P_CFGz_Pxy_IN_PUD
	Give the packet trace configuration a friendly name.

#define	PWRDN_OUT_PTI_EN GPIO_P_OUT_Pxy_PULLDOWN
	Give the packet trace configuration a friendly name.

#define	PWRUP_CFG_PTI_DATA GPIO_P_CFGz_Pxy_OUT_ALT
	Give the packet trace configuration a friendly name.

#define	PWRUP_OUT_PTI_DATA 1
	Give the packet trace configuration a friendly name.

#define	PWRDN_CFG_PTI_DATA GPIO_P_CFGz_Pxy_IN_PUD
	Give the packet trace configuration a friendly name.

#define	PWRDN_OUT_PTI_DATA GPIO_P_OUT_Pxy_PULLUP
	Give the packet trace configuration a friendly name.

32kHz Oscillator and nTX_ACTIVE Configuration Defines
Since the 32kHz Oscillator and nTX_ACTIVE both share PC6, their configuration defines are linked and instantiated together. Look above for the defines that enable the 32kHz Oscillator and nTX_ACTIVE. Note ENABLE_OSC32K is mutually exclusive with ENABLE_ALT_FUNCTION_NTX_ACTIVE since they define conflicting usage of GPIO PC6. When using the 32kHz, configure PC6 and PC7 for analog for the XTAL. When using nTX_ACTIVE, configure PC6 for alternate output while awake and a low output when deepsleeping. Also, configure PC7 for TEMP_EN. When not using the 32kHz or nTX_ACTIVE, configure PC6 and PC7 for Button1 and TEMP_EN.
#define	PWRUP_CFG_BUTTON1 GPIO_P_CFGz_Pxy_IN_PUD
	Give GPIO PC6 configuration a friendly name.

#define	PWRUP_OUT_BUTTON1 GPIO_P_OUT_Pxy_PULLUP /* Button needs a pullup */
	Give GPIO PC6 configuration a friendly name.

#define	PWRDN_CFG_BUTTON1 GPIO_P_CFGz_Pxy_IN_PUD
	Give GPIO PC6 configuration a friendly name.

#define	PWRDN_OUT_BUTTON1 GPIO_P_OUT_Pxy_PULLUP /* Button needs a pullup */
	Give GPIO PC6 configuration a friendly name.

#define	CFG_TEMPEN GPIO_P_CFGz_Pxy_OUT
	Give GPIO PC7 configuration a friendly name.

TX_ACTIVE Configuration Defines
Provide the proper set of pin (PC5) configurations for when TX_ACTIVE is enabled (look above for the define which enables it). When TX_ACTIVE is not enabled, configure the pin for LED2.
#define	PWRUP_CFG_LED2 GPIO_P_CFGz_Pxy_OUT
	Give the TX_ACTIVE configuration a friendly name.

#define	PWRUP_OUT_LED2 1 /* LED default off */
	Give the TX_ACTIVE configuration a friendly name.

#define	PWRDN_CFG_LED2 GPIO_P_CFGz_Pxy_OUT
	Give the TX_ACTIVE configuration a friendly name.

#define	PWRDN_OUT_LED2 1 /* LED default off */
	Give the TX_ACTIVE configuration a friendly name.

USB Configuration Defines
Provide the proper set of pin configuration for when USB is not enumerated. Not enumerated primarily refers to the driver not being configured or deep sleep. The configuration used here is only for keeping the USB off the bus. The GPIO configuration used when active is controlled by the USB driver since the driver needs to control the enumeration process (which affects GPIO state.) Note : Using USB requires Serial port 3 to be defined and is only possible on EM3582/EM3586/EM3588/EM359 chips.
#define	PWRUP_CFG_USBDM GPIO_P_CFGz_Pxy_OUT_ALT
	Give the USB configuration a friendly name.

#define	PWRUP_OUT_USBDM 0
	Give the USB configuration a friendly name.

#define	PWRUP_CFG_USBDP GPIO_P_CFGz_Pxy_IN
	Give the USB configuration a friendly name.

#define	PWRUP_OUT_USBDP 0
	Give the USB configuration a friendly name.

#define	PWRUP_CFG_ENUMCTRL GPIO_P_CFGz_Pxy_OUT_ALT
	Give the USB configuration a friendly name.

#define	PWRUP_OUT_ENUMCTRL 0
	Give the USB configuration a friendly name.

#define	PWRUP_CFG_VBUSMON GPIO_P_CFGz_Pxy_OUT
	Give the USB configuration a friendly name.

#define	PWRUP_OUT_VBUSMON 1
	Give the USB configuration a friendly name.

#define	PWRDN_CFG_USBDM GPIO_P_CFGz_Pxy_IN_PUD
	Give the USB configuration a friendly name.

#define	PWRDN_OUT_USBDM GPIO_P_OUT_Pxy_PULLUP
	Give the USB configuration a friendly name.

#define	PWRDN_CFG_USBDP GPIO_P_CFGz_Pxy_IN_PUD
	Give the USB configuration a friendly name.

#define	PWRDN_OUT_USBDP GPIO_P_OUT_Pxy_PULLUP
	Give the USB configuration a friendly name.

#define	PWRDN_CFG_ENUMCTRL GPIO_P_CFGz_Pxy_IN_PUD
	Give the USB configuration a friendly name.

#define	PWRDN_OUT_ENUMCTRL GPIO_P_OUT_Pxy_PULLUP
	Give the USB configuration a friendly name.

#define	PWRDN_CFG_VBUSMON GPIO_P_CFGz_Pxy_OUT
	Give the USB configuration a friendly name.

#define	PWRDN_OUT_VBUSMON 1
	Give the USB configuration a friendly name.

GPIO Configuration Macros
These macros define the GPIO configuration and initial state of the output registers for all the GPIO in the powerup and powerdown modes.
uint16_t	gpioCfgPowerUp [6]
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

uint16_t	gpioCfgPowerDown [6]
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

uint8_t	gpioOutPowerUp [3]
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

uint8_t	gpioOutPowerDown [3]
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

GpioMaskType	gpioRadioPowerBoardMask
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

#define	DEFINE_GPIO_RADIO_POWER_BOARD_MASK_VARIABLE () GpioMaskType gpioRadioPowerBoardMask = 0
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

#define	DEFINE_POWERUP_GPIO_CFG_VARIABLES ()
	Initialize GPIO powerup configuration variables.

#define	DEFINE_POWERUP_GPIO_OUTPUT_DATA_VARIABLES ()
	Initialize GPIO powerup output variables.

#define	DEFINE_POWERDOWN_GPIO_CFG_VARIABLES ()
	Initialize powerdown GPIO configuration variables.

#define	DEFINE_POWERDOWN_GPIO_OUTPUT_DATA_VARIABLES ()
	Initialize powerdown GPIO output variables.

#define	SET_POWERUP_GPIO_CFG_REGISTERS ()
	Set powerup GPIO configuration registers.

#define	SET_POWERUP_GPIO_OUTPUT_DATA_REGISTERS ()
	Set powerup GPIO output registers.

#define	SET_POWERDOWN_GPIO_CFG_REGISTERS ()
	Set powerdown GPIO configuration registers.

#define	SET_POWERDOWN_GPIO_OUTPUT_DATA_REGISTERS ()
	Set powerdown GPIO output registers.

#define	SET_RESUME_GPIO_CFG_REGISTERS ()
	Set resume GPIO configuration registers. Identical to SET_POWERUP.

#define	SET_RESUME_GPIO_OUTPUT_DATA_REGISTERS ()
	Set resume GPIO output registers. Identical to SET_POWERUP.

#define	SET_SUSPEND_GPIO_CFG_REGISTERS ()
	Set suspend GPIO configuration registers. SET_POWERDOWN minus USB regs.

#define	SET_SUSPEND_GPIO_OUTPUT_DATA_REGISTERS ()
	Set suspend GPIO output registers. SET_POWERDOWN minus USB regs.

#define	CONFIGURE_EXTERNAL_REGULATOR_ENABLE () GPIO->DBGCFG &= ~GPIO_DBGCFG_EXTREGEN;
	External regulator enable/disable macro.

GPIO Wake Source Definitions
A convenient define that chooses if this external signal can be used as source to wake from deep sleep. Any change in the state of the signal will wake up the CPU.
#define	WAKE_ON_PA0 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA1 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA2 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA3 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA4 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA5 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA6 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA7 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB0 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB1 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB2 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB3 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB4 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB5 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB6 true
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB7 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC0 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC1 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC2 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC3 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC4 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC5 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC6 true
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC7 false
	true if this GPIO can wake the chip from deep sleep, false if not.

Custom Baud Rate Definitions
The following define is used with defining a custom baud rate for the UART. This define provides a simple hook into the definition of the baud rates used with the UART. The baudSettings[] array in uart.c links the BAUD_* defines with the actual register values needed for operating the UART. The array baudSettings[] can be edited directly for a custom baud rate or another entry (the register settings) can be provided here with this define.
#define	EMBER_SERIAL_BAUD_CUSTOM 13
	This define is the register setting for generating a baud of.

LED Definitions
The following are used to aid in the abstraction with the LED connections. The microcontroller-specific sources use these definitions so they are able to work across a variety of boards which could have different connections. The names and ports/pins used below are intended to match with a schematic of the system to provide the abstraction. The HalBoardLedPins enum values should always be used when manipulating the state of LEDs, as they directly refer to the GPIOs to which the LEDs are connected. Note: LEDs 0 and 1 are on the RCM. Note: LED 2 is on the breakout board (dev0680). Note: LED 3 simply redirects to LED 2.
enum	HalBoardLedPins { BOARDLED0 = PORTA_PIN(6), BOARDLED1 = PORTA_PIN(7), BOARDLED2 = PORTC_PIN(5), BOARDLED3 = BOARDLED2, BOARD_ACTIVITY_LED = BOARDLED0, BOARD_HEARTBEAT_LED = BOARDLED1, BOARDLED0 = PORTA_PIN(6), BOARDLED1 = PORTA_PIN(7), BOARDLED2 = PORTC_PIN(5), BOARDLED3 = BOARDLED2, BOARD_ACTIVITY_LED = BOARDLED0, BOARD_HEARTBEAT_LED = BOARDLED1 }
	Assign each GPIO with an LED connected to a convenient name. BOARD_ACTIVITY_LED and BOARD_HEARTBEAT_LED provide a further layer of abstraction on top of the 3 LEDs for verbose coding.

Button Definitions
The following are used to aid in the abstraction with the Button connections. The microcontroller-specific sources use these definitions so they are able to work across a variety of boards which could have different connections. The names and ports/pins used below are intended to match with a schematic of the system to provide the abstraction. The BUTTONn macros should always be used with manipulating the buttons as they directly refer to the GPIOs to which the buttons are connected. Note The GPIO number must match the IRQ letter
#define	BUTTON0 PORTB_PIN(6)
	The actual GPIO BUTTON0 is connected to. This define should be used whenever referencing BUTTON0.

#define	BUTTON0_IN (GPIO->P[1].IN)
	The GPIO input register for BUTTON0.

#define	BUTTON0_SEL () do {} while (0)
	Point the proper IRQ at the desired pin for BUTTON0.

#define	BUTTON0_ISR halIrqBIsr
	The interrupt service routine for BUTTON0.

#define	BUTTON0_INTCFG (EVENT_GPIO->CFGB)
	The interrupt configuration register for BUTTON0.

#define	BUTTON0_INT_EN_IRQN IRQB_IRQn
	The interrupt enable bit for BUTTON0.

#define	BUTTON0_INT_EN_BIT BIT32 ( BUTTON0_INT_EN_IRQN )
	The actual GPIO BUTTON0 is connected to. This define should be used whenever referencing BUTTON0.

#define	BUTTON0_FLAG_BIT EVENT_GPIO_FLAG_IRQB
	The interrupt flag bit for BUTTON0.

#define	BUTTON0_MISS_BIT EVENT_MISS_MISS_IRQB
	The missed interrupt bit for BUTTON0.

#define	BUTTON1 PORTC_PIN(6)
	The actual GPIO BUTTON1 is connected to. This define should be used whenever referencing BUTTON1.

#define	BUTTON1_IN (GPIO->P[2].IN)
	The GPIO input register for BUTTON1.

#define	BUTTON1_SEL () do { GPIO->IRQCSEL = PORTC_PIN(6); } while (0)
	Point the proper IRQ at the desired pin for BUTTON1.

#define	BUTTON1_ISR halIrqCIsr
	The interrupt service routine for BUTTON1.

#define	BUTTON1_INTCFG (EVENT_GPIO->CFGC)
	The interrupt configuration register for BUTTON1.

#define	BUTTON1_INT_EN_IRQN IRQC_IRQn
	The interrupt enable bit for BUTTON1.

#define	BUTTON1_INT_EN_BIT BIT32 ( BUTTON1_INT_EN_IRQN )
	The actual GPIO BUTTON0 is connected to. This define should be used whenever referencing BUTTON0.

#define	BUTTON1_FLAG_BIT EVENT_GPIO_FLAG_IRQC
	The interrupt flag bit for BUTTON1.

#define	BUTTON1_MISS_BIT EVENT_MISS_MISS_IRQC
	The missed interrupt bit for BUTTON1.

Radio HoldOff Configuration Definitions
This define does not equate to anything. It is used as a trigger to enable Radio HoldOff support. The following are used to aid in the abstraction with Radio HoldOff (RHO). The microcontroller-specific sources use these definitions so they are able to work across a variety of boards which could have different connections. The names and ports/pins used below are intended to match with a schematic of the system to provide the abstraction. The Radio HoldOff input GPIO is abstracted like BUTTON0/1.
#define	RHO_GPIO PORTA_PIN(6)
	The actual GPIO used to control Radio HoldOff.

#define	RHO_ASSERTED 1
	The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

#define	RHO_CFG (GPIO->P[0].CFGH)
	The GPIO configuration register for Radio HoldOff.

#define	RHO_IN (GPIO->P[0].IN)
	The GPIO input register for Radio HoldOff.

#define	RHO_OUT (GPIO->P[0].OUT)
	The GPIO output register for Radio HoldOff.

#define	RHO_SEL () do { GPIO->IRQDSEL = RHO_GPIO ; } while (0)
	Point the proper IRQ at the desired pin for Radio HoldOff. Remember there may be other things that might want to use this IRQ.

#define	RHO_ISR halIrqDIsr
	The interrupt service routine for Radio HoldOff. Remember there may be other things that might want to use this IRQ.

#define	RHO_INTCFG (EVENT_GPIO->CFGD)
	The interrupt configuration register for Radio HoldOff.

#define	RHO_INT_EN_IRQN IRQD_IRQn
	The interrupt enable bit for Radio HoldOff.

#define	RHO_INT_EN_BIT BIT32 ( RHO_INT_EN_IRQN )
	The actual GPIO used to control Radio HoldOff.

#define	RHO_FLAG_BIT EVENT_GPIO_FLAG_IRQD
	The interrupt flag bit for Radio HoldOff.

#define	RHO_MISS_BIT EVENT_MISS_MISS_IRQD
	The missed interrupt bit for Radio HoldOff.

#define	PWRUP_CFG_DFL_RHO_FOR_RHO GPIO_P_CFGz_Pxy_IN_PUD
	Configuration of GPIO for Radio HoldOff operation.

#define	PWRUP_OUT_DFL_RHO_FOR_RHO GPIO_P_OUT_Pxy_PULLDOWN /* Deassert */
	The actual GPIO used to control Radio HoldOff.

#define	PWRDN_CFG_DFL_RHO_FOR_RHO GPIO_P_CFGz_Pxy_IN_PUD
	The actual GPIO used to control Radio HoldOff.

#define	PWRDN_OUT_DFL_RHO_FOR_RHO GPIO_P_OUT_Pxy_PULLDOWN /* Deassert */
	The actual GPIO used to control Radio HoldOff.

#define	PWRUP_CFG_DFL_RHO_FOR_DFL GPIO_P_CFGz_Pxy_OUT
	Configuration of GPIO for default behavior.

#define	PWRUP_OUT_DFL_RHO_FOR_DFL 1 /* LED default off */
	The actual GPIO used to control Radio HoldOff.

#define	PWRDN_CFG_DFL_RHO_FOR_DFL GPIO_P_CFGz_Pxy_OUT
	The actual GPIO used to control Radio HoldOff.

#define	PWRDN_OUT_DFL_RHO_FOR_DFL 1 /* LED off */
	The actual GPIO used to control Radio HoldOff.

#define	PWRUP_CFG_DFL_RHO PWRUP_CFG_DFL_RHO_FOR_DFL
	The following definitions are helpers for managing Radio HoldOff and should not be modified.

#define	PWRUP_OUT_DFL_RHO PWRUP_OUT_DFL_RHO_FOR_DFL
	The actual GPIO used to control Radio HoldOff.

#define	PWRDN_CFG_DFL_RHO PWRDN_CFG_DFL_RHO_FOR_DFL
	The actual GPIO used to control Radio HoldOff.

#define	PWRDN_OUT_DFL_RHO PWRDN_OUT_DFL_RHO_FOR_DFL
	The actual GPIO used to control Radio HoldOff.

#define	halInternalInitRadioHoldOff () /* no-op */
	The actual GPIO used to control Radio HoldOff.

#define	ADJUST_GPIO_CONFIG_DFL_RHO (enableRadioHoldOff)
	The actual GPIO used to control Radio HoldOff.

Temperature sensor ADC channel
Define the analog input channel connected to the LM-20 temperature sensor. The scale factor compensates for different platform input ranges. PB5/ADC0 must be an analog input. PC7 must be an output and set to a high level to power the sensor.
#define	TEMP_SENSOR_ADC_CHANNEL ADC_SOURCE_ADC0_VREF2
	The analog input channel to use for the temperature sensor.

#define	TEMP_SENSOR_SCALE_FACTOR 1
	The scale factor to compensate for different input ranges.

Packet Trace
When PACKET_TRACE is defined, ::GPIO->P[0].CFGH will automatically be setup by halInit() to enable Packet Trace support on PA4 and PA5, in addition to the configuration specified below. Note This define will override any settings for PA4 and PA5.
#define	PACKET_TRACE
	This define does not equate to anything. It is used as a trigger to enable Packet Trace support on the breakout board (dev0680).

ENABLE_OSC32K

When ENABLE_OSC32K is defined, halInit() will configure system timekeeping to utilize the external 32.768 kHz crystal oscillator rather than the internal 1 kHz RC oscillator.

Note: ENABLE_OSC32K is mutually exclusive with ENABLE_ALT_FUNCTION_NTX_ACTIVE since they define conflicting usage of GPIO PC6.

On initial powerup the 32.768 kHz crystal oscillator will take a little while to start stable oscillation. This only happens on initial powerup, not on wake-from-sleep, since the crystal usually stays running in deep sleep mode.

When ENABLE_OSC32K is defined the crystal oscillator is started as part of halInit() . After the crystal is started we delay for OSC32K_STARTUP_DELAY_MS (time in milliseconds). This delay allows the crystal oscillator to stabilize before we start using it for system timing.

If you set OSC32K_STARTUP_DELAY_MS to less than the crystal's startup time:

The system timer won't produce a reliable one millisecond tick before the crystal is stable.
You may see some number of ticks of unknown period occur before the crystal is stable.
halInit() will complete and application code will begin running, but any events based on the system timer will not be accurate until the crystal is stable.
An unstable system timer will only affect the APIs in system-timer.h .

Typical 32.768 kHz crystals measured by Ember take about 400 milliseconds to stabilize. Be sure to characterize your particular crystal's stabilization time since crystal behavior can vary.

#define OSC32K_STARTUP_DELAY_MS (0)

ENABLE_ALT_FUNCTION_TX_ACTIVE
This define does not equate to anything. It is used as a trigger to enable the REG_EN alternate function on PA7. Default is to not enable REG_EN functionality on PA7. When ENABLE_ALT_FUNCTION_TX_ACTIVE is defined, halInit() and halPowerUp() will enable the TX_ACTIVE alternate functionality of PC5. halPowerDown() will configure PC5 to be a low output. TX_ACTIVE can be used for external PA power management and RF switching logic. In transmit mode the Tx baseband drives TX_ACTIVE high. In receive mode the TX_ACTIVE signal is low. This define will override any settings for PC5.
#define	ENABLE_ALT_FUNCTION_TX_ACTIVE
	This define does not equate to anything. It is used as a trigger to enable the TX_ACTIVE alternate function on PC5. It is enabled by default in this board file because the SiGe SE2432L requires the TX_ACTIVE alternate function to operate properly.

EEPROM_USES_SHUTDOWN_CONTROL
This define does not equate to anything. It is used as a trigger to enable the nTX_ACTIVE alternate function on PC6. Default is to not enable nTX_ACTIVE functionality on PC6. When EEPROM_USES_SHUTDOWN_CONTROL is defined, logic is enabled in the EEPROM driver which drives PB7 high upon EEPROM initialization. In Ember reference designs, PB7 acts as an EEPROM enable pin and therefore must be driven high in order to use the EEPROM. This option is intended to be enabled when running app-bootloader on designs based on current Ember reference designs.
#define	EEPROM_USES_SHUTDOWN_CONTROL
	This define does not equate to anything. It is used as a trigger to enable the logic that drives PB7 high in the EEPROM driver.

Packet Trace Configuration Defines
Provide the proper set of pin configuration for when the Packet Trace is enabled (look above for the define which enables it). When Packet Trace is not enabled, leave the two PTI pins in their default configuration. If Packet Trace is not being used, feel free to set the pin configurations as desired. The config shown here is simply the Power On Reset defaults.
#define	PWRUP_CFG_PTI_EN GPIO_P_CFGz_Pxy_OUT_ALT
	Give the packet trace configuration a friendly name.

#define	PWRUP_OUT_PTI_EN 0
	Give the packet trace configuration a friendly name.

#define	PWRDN_CFG_PTI_EN GPIO_P_CFGz_Pxy_IN_PUD
	Give the packet trace configuration a friendly name.

#define	PWRDN_OUT_PTI_EN GPIO_P_OUT_Pxy_PULLDOWN
	Give the packet trace configuration a friendly name.

#define	PWRUP_CFG_PTI_DATA GPIO_P_CFGz_Pxy_OUT_ALT
	Give the packet trace configuration a friendly name.

#define	PWRUP_OUT_PTI_DATA 1
	Give the packet trace configuration a friendly name.

#define	PWRDN_CFG_PTI_DATA GPIO_P_CFGz_Pxy_IN_PUD
	Give the packet trace configuration a friendly name.

#define	PWRDN_OUT_PTI_DATA GPIO_P_OUT_Pxy_PULLUP
	Give the packet trace configuration a friendly name.

32kHz Oscillator and nTX_ACTIVE Configuration Defines
Since the 32kHz Oscillator and nTX_ACTIVE both share PC6, their configuration defines are linked and instantiated together. Look above for the defines that enable the 32kHz Oscillator and nTX_ACTIVE. Note ENABLE_OSC32K is mutually exclusive with ENABLE_ALT_FUNCTION_NTX_ACTIVE since they define conflicting usage of GPIO PC6. When using the 32kHz, configure PC6 and PC7 for analog for the XTAL. When using nTX_ACTIVE, configure PC6 for alternate output while awake and a low output when deepsleeping. Also, configure PC7 for TEMP_EN. When not using the 32kHz or nTX_ACTIVE, configure PC6 and PC7 for Button1 and TEMP_EN.
#define	PWRUP_CFG_BUTTON1 GPIO_P_CFGz_Pxy_IN_PUD
	Give GPIO PC6 configuration a friendly name.

#define	PWRUP_OUT_BUTTON1 GPIO_P_OUT_Pxy_PULLUP /* Button needs a pullup */
	Give GPIO PC6 configuration a friendly name.

#define	PWRDN_CFG_BUTTON1 GPIO_P_CFGz_Pxy_IN_PUD
	Give GPIO PC6 configuration a friendly name.

#define	PWRDN_OUT_BUTTON1 GPIO_P_OUT_Pxy_PULLUP /* Button needs a pullup */
	Give GPIO PC6 configuration a friendly name.

#define	CFG_TEMPEN GPIO_P_CFGz_Pxy_OUT
	Give GPIO PC7 configuration a friendly name.

TX_ACTIVE Configuration Defines
Provide the proper set of pin (PC5) configurations for when TX_ACTIVE is enabled (look above for the define which enables it). When TX_ACTIVE is not enabled, configure the pin for LED2.
#define	PWRUP_CFG_LED2 GPIO_P_CFGz_Pxy_OUT_ALT
	Give the TX_ACTIVE configuration a friendly name.

#define	PWRUP_OUT_LED2 0
	Give the TX_ACTIVE configuration a friendly name.

#define	PWRDN_CFG_LED2 GPIO_P_CFGz_Pxy_OUT
	Give the TX_ACTIVE configuration a friendly name.

#define	PWRDN_OUT_LED2 0
	Give the TX_ACTIVE configuration a friendly name.

GPIO Configuration Macros
These macros define the GPIO configuration and initial state of the output registers for all the GPIO in the powerup and powerdown modes.
uint16_t	gpioCfgPowerUp [6]
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

uint16_t	gpioCfgPowerDown [6]
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

uint8_t	gpioOutPowerUp [3]
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

uint8_t	gpioOutPowerDown [3]
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

GpioMaskType	gpioRadioPowerBoardMask
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

#define	FEM_CTX_BIT ( BIT32 (PORTC_PIN(5)))
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

#define	FEM_CRX_BIT (0)
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

#define	DEFINE_GPIO_RADIO_POWER_BOARD_MASK_VARIABLE ()
	Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

#define	DEFINE_POWERUP_GPIO_CFG_VARIABLES ()
	Initialize GPIO powerup configuration variables.

#define	DEFINE_POWERUP_GPIO_OUTPUT_DATA_VARIABLES ()
	Initialize GPIO powerup output variables.

#define	DEFINE_POWERDOWN_GPIO_CFG_VARIABLES ()
	Initialize powerdown GPIO configuration variables.

#define	DEFINE_POWERDOWN_GPIO_OUTPUT_DATA_VARIABLES ()
	Initialize powerdown GPIO output variables.

#define	SET_POWERUP_GPIO_CFG_REGISTERS ()
	Set powerup GPIO configuration registers.

#define	SET_POWERUP_GPIO_OUTPUT_DATA_REGISTERS ()
	Set powerup GPIO output registers.

#define	SET_POWERDOWN_GPIO_CFG_REGISTERS ()
	Set powerdown GPIO configuration registers.

#define	SET_POWERDOWN_GPIO_OUTPUT_DATA_REGISTERS ()
	Set powerdown GPIO output registers.

#define	CONFIGURE_EXTERNAL_REGULATOR_ENABLE () GPIO->DBGCFG &= ~GPIO_DBGCFG_EXTREGEN;
	External regulator enable/disable macro.

GPIO Wake Source Definitions
A convenient define that chooses if this external signal can be used as source to wake from deep sleep. Any change in the state of the signal will wake up the CPU.
#define	WAKE_ON_PA0 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA1 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA2 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA3 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA4 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA5 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA6 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PA7 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB0 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB1 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB2 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB3 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB4 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB5 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB6 true
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PB7 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC0 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC1 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC2 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC3 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC4 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC5 false
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC6 true
	true if this GPIO can wake the chip from deep sleep, false if not.

#define	WAKE_ON_PC7 false
	true if this GPIO can wake the chip from deep sleep, false if not.

Detailed Description

Functions and definitions specific to the breakout board.

Note: The file dev0680.h is intended to be copied, renamed, and customized for customer-specific hardware.

The file dev0680.h is the default BOARD_HEADER file used with the breakout board of the development kit.

The EM35x on a dev0680 BoB has the following example GPIO configuration. This board file and the default HAL setup reflects this configuration.

PA0 - SC2MOSI
PA1 - SC2MISO
PA2 - SC2SCLK
PA3 - SC2nSSEL
PA4 - PTI_EN
PA5 - PTI_DATA
PA6 - LED (on RCM), or Radio HoldOff
PA7 - LED (on RCM)
PB0 - Power Amplifier shutdown control / TRACEDATA2
PB1 - SC1TXD
PB2 - SC1RXD
PB3 - SC1nCTS
PB4 - SC1nRTS
PB5 - TEMP_SENSE
PB6 - Button (IRQB fixed to PB6)
PB7 - Buzzer (also used for DataFlash Enable)
PC0 - JTAG (JRST) / TRACEDATA1
PC1 - Power Amplifier antenna select control / TRACEDATA3
PC2 - JTAG (JTDO) / SWO / TRACEDATA0
PC3 - JTAG (JTDI) / TRACECLK
PC4 - JTAG (JTMS) / SWDIO
PC5 - LED (on BoB)
PC6 - Button (IRQC pointed to PC6)
PC7 - TEMP_EN

Note: The file ref0657.h is a special variant of dev0680.h intended only for use with the SiGe SE2432L reference design.

The file dev0680.h is the default BOARD_HEADER file used with the breakout board of the development kit.

The EM35x on a dev0680 BoB has the following example GPIO configuration. This board file and the default HAL setup reflects this configuration.

PA0 - SC2MOSI
PA1 - SC2MISO
PA2 - SC2SCLK
PA3 - SC2nSSEL
PA4 - PTI_EN
PA5 - PTI_DATA
PA6 - LED (on RCM), or Radio HoldOff
PA7 - LED (on RCM)
PB0 - Power Amplifier shutdown control
PB1 - SC1TXD
PB2 - SC1RXD
PB3 - SC1nCTS
PB4 - SC1nRTS
PB5 - TEMP_SENSE (also used for SiGe SE2432L CPS)
PB6 - Button (IRQB fixed to PB6)
PB7 - Buzzer (also used for DataFlash Enable)
PC0 - JTAG (JRST)
PC1 - Power Amplifier antenna select control
PC2 - JTAG (JTDO) / SWO
PC3 - JTAG (JTDI)
PC4 - JTAG (JTMS)
PC5 - TX_ACTIVE (FEM CTX)
PC6 - Button (IRQC pointed to PC6)
PC7 - TEMP_EN

Macro Definition Documentation

◆ ADJUST_GPIO_CONFIG_DFL_RHO

#define ADJUST_GPIO_CONFIG_DFL_RHO ( enableRadioHoldOff )

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use.

◆ BUTTON0 [1/2]

#define BUTTON0 PORTB_PIN(6)

The actual GPIO BUTTON0 is connected to. This define should be used whenever referencing BUTTON0.

◆ BUTTON0 [2/2]

#define BUTTON0 PORTB_PIN(6)

The actual GPIO BUTTON0 is connected to. This define should be used whenever referencing BUTTON0.

◆ BUTTON0_FLAG_BIT [1/2]

#define BUTTON0_FLAG_BIT EVENT_GPIO_FLAG_IRQB

The interrupt flag bit for BUTTON0.

◆ BUTTON0_FLAG_BIT [2/2]

#define BUTTON0_FLAG_BIT EVENT_GPIO_FLAG_IRQB

The interrupt flag bit for BUTTON0.

◆ BUTTON0_IN [1/2]

#define BUTTON0_IN (GPIO->P[1].IN)

The GPIO input register for BUTTON0.

◆ BUTTON0_IN [2/2]

#define BUTTON0_IN (GPIO->P[1].IN)

The GPIO input register for BUTTON0.

◆ BUTTON0_INT_EN_BIT [1/2]

#define BUTTON0_INT_EN_BIT BIT32 ( BUTTON0_INT_EN_IRQN )

The actual GPIO BUTTON0 is connected to. This define should be used whenever referencing BUTTON0.

◆ BUTTON0_INT_EN_BIT [2/2]

#define BUTTON0_INT_EN_BIT BIT32 ( BUTTON0_INT_EN_IRQN )

The actual GPIO BUTTON0 is connected to. This define should be used whenever referencing BUTTON0.

◆ BUTTON0_INT_EN_IRQN [1/2]

#define BUTTON0_INT_EN_IRQN IRQB_IRQn

The interrupt enable bit for BUTTON0.

◆ BUTTON0_INT_EN_IRQN [2/2]

#define BUTTON0_INT_EN_IRQN IRQB_IRQn

The interrupt enable bit for BUTTON0.

◆ BUTTON0_INTCFG [1/2]

#define BUTTON0_INTCFG (EVENT_GPIO->CFGB)

The interrupt configuration register for BUTTON0.

◆ BUTTON0_INTCFG [2/2]

#define BUTTON0_INTCFG (EVENT_GPIO->CFGB)

The interrupt configuration register for BUTTON0.

◆ BUTTON0_ISR [1/2]

#define BUTTON0_ISR halIrqBIsr

The interrupt service routine for BUTTON0.

◆ BUTTON0_ISR [2/2]

#define BUTTON0_ISR halIrqBIsr

The interrupt service routine for BUTTON0.

◆ BUTTON0_MISS_BIT [1/2]

#define BUTTON0_MISS_BIT EVENT_MISS_MISS_IRQB

The missed interrupt bit for BUTTON0.

◆ BUTTON0_MISS_BIT [2/2]

#define BUTTON0_MISS_BIT EVENT_MISS_MISS_IRQB

The missed interrupt bit for BUTTON0.

◆ BUTTON0_SEL [1/2]

#define BUTTON0_SEL ( ) do {} while (0)

Point the proper IRQ at the desired pin for BUTTON0.

Note: IRQB is fixed and as such does not need any selection operation.

◆ BUTTON0_SEL [2/2]

#define BUTTON0_SEL ( ) do {} while (0)

Point the proper IRQ at the desired pin for BUTTON0.

Note: IRQB is fixed and as such does not need any selection operation.

◆ BUTTON1 [1/2]

#define BUTTON1 PORTC_PIN(6)

The actual GPIO BUTTON1 is connected to. This define should be used whenever referencing BUTTON1.

◆ BUTTON1 [2/2]

#define BUTTON1 PORTC_PIN(6)

The actual GPIO BUTTON1 is connected to. This define should be used whenever referencing BUTTON1, such as controlling if pieces are compiled in. Remember there may be other things that might want to use IRQC.

◆ BUTTON1_FLAG_BIT [1/2]

#define BUTTON1_FLAG_BIT EVENT_GPIO_FLAG_IRQC

The interrupt flag bit for BUTTON1.

◆ BUTTON1_FLAG_BIT [2/2]

#define BUTTON1_FLAG_BIT EVENT_GPIO_FLAG_IRQC

The interrupt flag bit for BUTTON1.

◆ BUTTON1_IN [1/2]

#define BUTTON1_IN (GPIO->P[2].IN)

The GPIO input register for BUTTON1.

◆ BUTTON1_IN [2/2]

#define BUTTON1_IN (GPIO->P[2].IN)

The GPIO input register for BUTTON1.

◆ BUTTON1_INT_EN_BIT [1/2]

#define BUTTON1_INT_EN_BIT BIT32 ( BUTTON1_INT_EN_IRQN )

The actual GPIO BUTTON0 is connected to. This define should be used whenever referencing BUTTON0.

◆ BUTTON1_INT_EN_BIT [2/2]

#define BUTTON1_INT_EN_BIT BIT32 ( BUTTON1_INT_EN_IRQN )

The actual GPIO BUTTON0 is connected to. This define should be used whenever referencing BUTTON0.

◆ BUTTON1_INT_EN_IRQN [1/2]

#define BUTTON1_INT_EN_IRQN IRQC_IRQn

The interrupt enable bit for BUTTON1.

◆ BUTTON1_INT_EN_IRQN [2/2]

#define BUTTON1_INT_EN_IRQN IRQC_IRQn

The interrupt enable bit for BUTTON1.

◆ BUTTON1_INTCFG [1/2]

#define BUTTON1_INTCFG (EVENT_GPIO->CFGC)

The interrupt configuration register for BUTTON1.

◆ BUTTON1_INTCFG [2/2]

#define BUTTON1_INTCFG (EVENT_GPIO->CFGC)

The interrupt configuration register for BUTTON1.

◆ BUTTON1_ISR [1/2]

#define BUTTON1_ISR halIrqCIsr

The interrupt service routine for BUTTON1.

◆ BUTTON1_ISR [2/2]

#define BUTTON1_ISR halIrqCIsr

The interrupt service routine for BUTTON1. Remember there may be other things that might want to use IRQC.

◆ BUTTON1_MISS_BIT [1/2]

#define BUTTON1_MISS_BIT EVENT_MISS_MISS_IRQC

The missed interrupt bit for BUTTON1.

◆ BUTTON1_MISS_BIT [2/2]

#define BUTTON1_MISS_BIT EVENT_MISS_MISS_IRQC

The missed interrupt bit for BUTTON1.

◆ BUTTON1_SEL [1/2]

#define BUTTON1_SEL ( ) do { GPIO->IRQCSEL = PORTC_PIN(6); } while (0)

Point the proper IRQ at the desired pin for BUTTON1.

Note: For this board, IRQC is pointed at PC6

◆ BUTTON1_SEL [2/2]

#define BUTTON1_SEL ( ) do { GPIO->IRQCSEL = PORTC_PIN(6); } while (0)

Point the proper IRQ at the desired pin for BUTTON1. Remember there may be other things that might want to use IRQC.

Note: For this board, IRQC is pointed at PC6

◆ CFG_TEMPEN [1/2]

#define CFG_TEMPEN GPIO_P_CFGz_Pxy_OUT

Give GPIO PC7 configuration a friendly name.

ENABLE_OSC32K

◆ CFG_TEMPEN [2/2]

#define CFG_TEMPEN GPIO_P_CFGz_Pxy_OUT

Give GPIO PC7 configuration a friendly name.

ENABLE_OSC32K

◆ CONFIGURE_EXTERNAL_REGULATOR_ENABLE [1/2]

#define CONFIGURE_EXTERNAL_REGULATOR_ENABLE ( ) GPIO->DBGCFG &= ~GPIO_DBGCFG_EXTREGEN;

External regulator enable/disable macro.

◆ CONFIGURE_EXTERNAL_REGULATOR_ENABLE [2/2]

#define CONFIGURE_EXTERNAL_REGULATOR_ENABLE ( ) GPIO->DBGCFG &= ~GPIO_DBGCFG_EXTREGEN;

External regulator enable/disable macro.

◆ DEFINE_GPIO_RADIO_POWER_BOARD_MASK_VARIABLE [1/2]

#define DEFINE_GPIO_RADIO_POWER_BOARD_MASK_VARIABLE ( )

Value:

         GpioMaskType
         
          gpioRadioPowerBoardMask
         
         = { (
         
          BIT32
         
         (PORTB_PIN(0))
         
          /* FEM_CSD */
         
         \
        
         |
         
          BIT32
         
         (PORTB_PIN(5))
         
          /* FEM_CPS */
         
         \
        
         |
         
          FEM_CTX_BIT
         
         \
        
         |
         
          FEM_CRX_BIT
         
         \
        
         ) }

Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

◆ DEFINE_GPIO_RADIO_POWER_BOARD_MASK_VARIABLE [2/2]

#define DEFINE_GPIO_RADIO_POWER_BOARD_MASK_VARIABLE ( ) GpioMaskType gpioRadioPowerBoardMask = 0

Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

◆ DEFINE_POWERDOWN_GPIO_CFG_VARIABLES [1/2]

#define DEFINE_POWERDOWN_GPIO_CFG_VARIABLES ( )

Value:

         uint16_t
         
          gpioCfgPowerDown
         
         [6] = {                                                                  \
        
         ((GPIO_P_CFGz_Pxy_IN_PUD     << _GPIO_P_CFGL_Px0_SHIFT)                                         \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD     << _GPIO_P_CFGL_Px1_SHIFT)                                       \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD     << _GPIO_P_CFGL_Px2_SHIFT)                                       \
        
         | (GPIO_P_CFGz_Pxy_OUT        << _GPIO_P_CFGL_Px3_SHIFT)),                                     \
        
         ((
         
          PWRDN_CFG_PTI_EN
         
         << _GPIO_P_CFGH_Px4_SHIFT)                                                 \
        
         | (
         
          PWRDN_CFG_PTI_DATA
         
         << _GPIO_P_CFGH_Px5_SHIFT)                                               \
        
         | (
         
          PWRDN_CFG_DFL_RHO
         
         << _GPIO_P_CFGH_Px6_SHIFT)                                               \
        
         | (GPIO_P_CFGz_Pxy_OUT        << _GPIO_P_CFGH_Px7_SHIFT)),                                     \
        
         ((GPIO_P_CFGz_Pxy_OUT        << _GPIO_P_CFGL_Px0_SHIFT)                                         \
        
         | (GPIO_P_CFGz_Pxy_OUT        << _GPIO_P_CFGL_Px1_SHIFT)
         
          /* SC1TXD  */
         
         \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD     << _GPIO_P_CFGL_Px2_SHIFT)
         
          /* SC1RXD  */
         
         \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD     << _GPIO_P_CFGL_Px3_SHIFT)),
         
          /* SC1nCTS */
         
         \
        
         ((GPIO_P_CFGz_Pxy_OUT        << _GPIO_P_CFGH_Px4_SHIFT)
         
          /* SC1nRTS */
         
         \
        
         | (GPIO_P_CFGz_Pxy_OUT        << _GPIO_P_CFGH_Px5_SHIFT)                                       \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD     << _GPIO_P_CFGH_Px6_SHIFT)                                       \
        
         |
         
          /* need to use pulldown for sleep */
         
         \
        
         (GPIO_P_CFGz_Pxy_IN_PUD     << _GPIO_P_CFGH_Px7_SHIFT)),                                       \
        
         ((GPIO_P_CFGz_Pxy_IN_PUD     << _GPIO_P_CFGL_Px0_SHIFT)                                         \
        
         | (GPIO_P_CFGz_Pxy_OUT        << _GPIO_P_CFGL_Px1_SHIFT)                                       \
        
         | (GPIO_P_CFGz_Pxy_OUT        << _GPIO_P_CFGL_Px2_SHIFT)                                       \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD     << _GPIO_P_CFGL_Px3_SHIFT)),                                     \
        
         ((GPIO_P_CFGz_Pxy_IN_PUD     << _GPIO_P_CFGH_Px4_SHIFT)                                         \
        
         | (
         
          PWRDN_CFG_LED2
         
         << _GPIO_P_CFGH_Px5_SHIFT)                                               \
        
         | (
         
          PWRDN_CFG_BUTTON1
         
         << _GPIO_P_CFGH_Px6_SHIFT)                                               \
        
         | (
         
          CFG_TEMPEN
         
         << _GPIO_P_CFGH_Px7_SHIFT))                                              \
        
         }

Initialize powerdown GPIO configuration variables.

◆ DEFINE_POWERDOWN_GPIO_CFG_VARIABLES [2/2]

#define DEFINE_POWERDOWN_GPIO_CFG_VARIABLES ( )

Value:

         uint16_t
         
          gpioCfgPowerDown
         
         [6] = {                                                               \
        
         ((
         
          PWRDN_CFG_USBDM
         
         << _GPIO_P_CFGL_Px0_SHIFT)                                        \
        
         | (
         
          PWRDN_CFG_USBDP
         
         << _GPIO_P_CFGL_Px1_SHIFT)                                      \
        
         | (
         
          PWRDN_CFG_ENUMCTRL
         
         << _GPIO_P_CFGL_Px2_SHIFT)                                      \
        
         | (
         
          PWRDN_CFG_VBUSMON
         
         << _GPIO_P_CFGL_Px3_SHIFT)),                                    \
        
         ((
         
          PWRDN_CFG_PTI_EN
         
         << _GPIO_P_CFGH_Px4_SHIFT)                                        \
        
         | (
         
          PWRDN_CFG_PTI_DATA
         
         << _GPIO_P_CFGH_Px5_SHIFT)                                      \
        
         | (
         
          PWRDN_CFG_DFL_RHO
         
         << _GPIO_P_CFGH_Px6_SHIFT)                                      \
        
         | (GPIO_P_CFGz_Pxy_OUT     << _GPIO_P_CFGH_Px7_SHIFT)),                                     \
        
         ((GPIO_P_CFGz_Pxy_OUT     << _GPIO_P_CFGL_Px0_SHIFT)                                         \
        
         | (GPIO_P_CFGz_Pxy_OUT     << _GPIO_P_CFGL_Px1_SHIFT)
         
          /* SC1TXD  */
         
         \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD  << _GPIO_P_CFGL_Px2_SHIFT)
         
          /* SC1RXD  */
         
         \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD  << _GPIO_P_CFGL_Px3_SHIFT)),
         
          /* SC1nCTS */
         
         \
        
         ((GPIO_P_CFGz_Pxy_OUT     << _GPIO_P_CFGH_Px4_SHIFT)
         
          /* SC1nRTS */
         
         \
        
         |
         
          /* disable analog for sleep */
         
         \
        
         (GPIO_P_CFGz_Pxy_IN_PUD  << _GPIO_P_CFGH_Px5_SHIFT)                                         \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD  << _GPIO_P_CFGH_Px6_SHIFT)                                       \
        
         |
         
          /* need to use pulldown for sleep */
         
         \
        
         (GPIO_P_CFGz_Pxy_IN_PUD  << _GPIO_P_CFGH_Px7_SHIFT)),                                       \
        
         ((GPIO_P_CFGz_Pxy_IN_PUD  << _GPIO_P_CFGL_Px0_SHIFT)                                         \
        
         | (GPIO_P_CFGz_Pxy_OUT     << _GPIO_P_CFGL_Px1_SHIFT)                                       \
        
         | (GPIO_P_CFGz_Pxy_OUT     << _GPIO_P_CFGL_Px2_SHIFT)                                       \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD  << _GPIO_P_CFGL_Px3_SHIFT)),                                     \
        
         ((GPIO_P_CFGz_Pxy_IN_PUD  << _GPIO_P_CFGH_Px4_SHIFT)                                         \
        
         | (
         
          PWRDN_CFG_LED2
         
         << _GPIO_P_CFGH_Px5_SHIFT)                                      \
        
         | (
         
          PWRDN_CFG_BUTTON1
         
         << _GPIO_P_CFGH_Px6_SHIFT)                                      \
        
         | (
         
          CFG_TEMPEN
         
         << _GPIO_P_CFGH_Px7_SHIFT))                                     \
        
         }

Initialize powerdown GPIO configuration variables.

◆ DEFINE_POWERDOWN_GPIO_OUTPUT_DATA_VARIABLES [1/2]

#define DEFINE_POWERDOWN_GPIO_OUTPUT_DATA_VARIABLES ( )

Initialize powerdown GPIO output variables.

◆ DEFINE_POWERDOWN_GPIO_OUTPUT_DATA_VARIABLES [2/2]

#define DEFINE_POWERDOWN_GPIO_OUTPUT_DATA_VARIABLES ( )

Initialize powerdown GPIO output variables.

◆ DEFINE_POWERUP_GPIO_CFG_VARIABLES [1/2]

#define DEFINE_POWERUP_GPIO_CFG_VARIABLES ( )

Value:

         uint16_t
         
          gpioCfgPowerUp
         
         [6] = {                                                                  \
        
         ((GPIO_P_CFGz_Pxy_OUT_ALT    << _GPIO_P_CFGL_Px0_SHIFT)                                       \
        
         | (GPIO_P_CFGz_Pxy_IN         << _GPIO_P_CFGL_Px1_SHIFT)                                     \
        
         | (GPIO_P_CFGz_Pxy_OUT_ALT    << _GPIO_P_CFGL_Px2_SHIFT)                                     \
        
         | (GPIO_P_CFGz_Pxy_OUT        << _GPIO_P_CFGL_Px3_SHIFT)),                                   \
        
         ((
         
          PWRUP_CFG_PTI_EN
         
         << _GPIO_P_CFGH_Px4_SHIFT)                                               \
        
         | (
         
          PWRUP_CFG_PTI_DATA
         
         << _GPIO_P_CFGH_Px5_SHIFT)                                             \
        
         | (
         
          PWRUP_CFG_DFL_RHO
         
         << _GPIO_P_CFGH_Px6_SHIFT)                                             \
        
         | (GPIO_P_CFGz_Pxy_OUT        << _GPIO_P_CFGH_Px7_SHIFT)),                                   \
        
         ((GPIO_P_CFGz_Pxy_OUT        << _GPIO_P_CFGL_Px0_SHIFT)                                       \
        
         | (GPIO_P_CFGz_Pxy_OUT_ALT    << _GPIO_P_CFGL_Px1_SHIFT)
         
          /* SC1TXD  */
         
         \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD     << _GPIO_P_CFGL_Px2_SHIFT)
         
          /* SC1RXD  */
         
         \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD     << _GPIO_P_CFGL_Px3_SHIFT)),
         
          /* SC1nCTS */
         
         \
        
         ((GPIO_P_CFGz_Pxy_OUT_ALT    << _GPIO_P_CFGH_Px4_SHIFT)
         
          /* SC1nRTS */
         
         \
        
         | (GPIO_P_CFGz_Pxy_OUT        << _GPIO_P_CFGH_Px5_SHIFT)                                     \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD     << _GPIO_P_CFGH_Px6_SHIFT)                                     \
        
         | (GPIO_P_CFGz_Pxy_OUT_ALT    << _GPIO_P_CFGH_Px7_SHIFT)),                                   \
        
         ((GPIO_P_CFGz_Pxy_OUT_ALT    << _GPIO_P_CFGL_Px0_SHIFT)                                       \
        
         | (GPIO_P_CFGz_Pxy_OUT        << _GPIO_P_CFGL_Px1_SHIFT)                                     \
        
         | (GPIO_P_CFGz_Pxy_OUT_ALT    << _GPIO_P_CFGL_Px2_SHIFT)                                     \
        
         | (GPIO_P_CFGz_Pxy_IN         << _GPIO_P_CFGL_Px3_SHIFT)),                                   \
        
         ((GPIO_P_CFGz_Pxy_IN         << _GPIO_P_CFGH_Px4_SHIFT)                                       \
        
         | (
         
          PWRUP_CFG_LED2
         
         << _GPIO_P_CFGH_Px5_SHIFT)                                             \
        
         | (
         
          PWRUP_CFG_BUTTON1
         
         << _GPIO_P_CFGH_Px6_SHIFT)                                             \
        
         | (
         
          CFG_TEMPEN
         
         << _GPIO_P_CFGH_Px7_SHIFT))                                            \
        
         }

Initialize GPIO powerup configuration variables.

◆ DEFINE_POWERUP_GPIO_CFG_VARIABLES [2/2]

#define DEFINE_POWERUP_GPIO_CFG_VARIABLES ( )

Value:

         uint16_t
         
          gpioCfgPowerUp
         
         [6] = {                                                                 \
        
         ((
         
          PWRUP_CFG_USBDM
         
         << _GPIO_P_CFGL_Px0_SHIFT)                                       \
        
         | (
         
          PWRUP_CFG_USBDP
         
         << _GPIO_P_CFGL_Px1_SHIFT)                                     \
        
         | (
         
          PWRUP_CFG_ENUMCTRL
         
         << _GPIO_P_CFGL_Px2_SHIFT)                                     \
        
         | (
         
          PWRUP_CFG_VBUSMON
         
         << _GPIO_P_CFGL_Px3_SHIFT)),                                   \
        
         ((
         
          PWRUP_CFG_PTI_EN
         
         << _GPIO_P_CFGH_Px4_SHIFT)                                       \
        
         | (
         
          PWRUP_CFG_PTI_DATA
         
         << _GPIO_P_CFGH_Px5_SHIFT)                                     \
        
         | (
         
          PWRUP_CFG_DFL_RHO
         
         << _GPIO_P_CFGH_Px6_SHIFT)                                     \
        
         | (GPIO_P_CFGz_Pxy_OUT      << _GPIO_P_CFGH_Px7_SHIFT)),                                    \
        
         ((GPIO_P_CFGz_Pxy_OUT      << _GPIO_P_CFGL_Px0_SHIFT)                                        \
        
         | (
         
          PWRUP_CFG_SC1_TXD
         
         << _GPIO_P_CFGL_Px1_SHIFT)
         
          /* SC1TXD  */
         
         \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD   << _GPIO_P_CFGL_Px2_SHIFT)
         
          /* SC1RXD  */
         
         \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD   << _GPIO_P_CFGL_Px3_SHIFT)),
         
          /* SC1nCTS */
         
         \
        
         ((GPIO_P_CFGz_Pxy_OUT_ALT  << _GPIO_P_CFGH_Px4_SHIFT)
         
          /* SC1nRTS */
         
         \
        
         | (GPIO_P_CFGz_Pxy_ANALOG   << _GPIO_P_CFGH_Px5_SHIFT)                                      \
        
         | (GPIO_P_CFGz_Pxy_IN_PUD   << _GPIO_P_CFGH_Px6_SHIFT)                                      \
        
         | (GPIO_P_CFGz_Pxy_OUT_ALT  << _GPIO_P_CFGH_Px7_SHIFT)),                                    \
        
         ((GPIO_P_CFGz_Pxy_IN       << _GPIO_P_CFGL_Px0_SHIFT)                                        \
        
         | (GPIO_P_CFGz_Pxy_OUT      << _GPIO_P_CFGL_Px1_SHIFT)                                      \
        
         | (GPIO_P_CFGz_Pxy_OUT_ALT  << _GPIO_P_CFGL_Px2_SHIFT)                                      \
        
         | (GPIO_P_CFGz_Pxy_IN       << _GPIO_P_CFGL_Px3_SHIFT)),                                    \
        
         ((GPIO_P_CFGz_Pxy_IN       << _GPIO_P_CFGH_Px4_SHIFT)                                        \
        
         | (
         
          PWRUP_CFG_LED2
         
         << _GPIO_P_CFGH_Px5_SHIFT)                                     \
        
         | (
         
          PWRUP_CFG_BUTTON1
         
         << _GPIO_P_CFGH_Px6_SHIFT)                                     \
        
         | (
         
          CFG_TEMPEN
         
         << _GPIO_P_CFGH_Px7_SHIFT))                                    \
        
         }

Initialize GPIO powerup configuration variables.

◆ DEFINE_POWERUP_GPIO_OUTPUT_DATA_VARIABLES [1/2]

#define DEFINE_POWERUP_GPIO_OUTPUT_DATA_VARIABLES ( )

Initialize GPIO powerup output variables.

◆ DEFINE_POWERUP_GPIO_OUTPUT_DATA_VARIABLES [2/2]

#define DEFINE_POWERUP_GPIO_OUTPUT_DATA_VARIABLES ( )

Value:

         uint8_t
         
          gpioOutPowerUp
         
         [3] = {                                                          \
        
         ((
         
          PWRUP_OUT_USBDM
         
         << _GPIO_P_OUT_Px0_SHIFT)                                       \
        
         | (
         
          PWRUP_OUT_USBDP
         
         << _GPIO_P_OUT_Px1_SHIFT)                                     \
        
         | (
         
          PWRUP_OUT_ENUMCTRL
         
         << _GPIO_P_OUT_Px2_SHIFT)                                     \
        
         | (
         
          PWRUP_OUT_VBUSMON
         
         << _GPIO_P_OUT_Px3_SHIFT)                                     \
        
         | (
         
          PWRUP_OUT_PTI_EN
         
         << _GPIO_P_OUT_Px4_SHIFT)                                     \
        
         | (
         
          PWRUP_OUT_PTI_DATA
         
         << _GPIO_P_OUT_Px5_SHIFT)                                     \
        
         | (
         
          PWRUP_OUT_DFL_RHO
         
         << _GPIO_P_OUT_Px6_SHIFT)                                     \
        
         |
         
          /* LED default off */
         
         \
        
         (1                  << _GPIO_P_OUT_Px7_SHIFT)),                                     \
        
         ((1                  << _GPIO_P_OUT_Px0_SHIFT)                                       \
        
         | (1                  << _GPIO_P_OUT_Px1_SHIFT)
         
          /* SC1TXD  */
         
         \
        
         | (1                  << _GPIO_P_OUT_Px2_SHIFT)
         
          /* SC1RXD  */
         
         \
        
         | (1                  << _GPIO_P_OUT_Px3_SHIFT)
         
          /* SC1nCTS */
         
         \
        
         | (0                  << _GPIO_P_OUT_Px4_SHIFT)
         
          /* SC1nRTS */
         
         \
        
         | (0                  << _GPIO_P_OUT_Px5_SHIFT)                                     \
        
         |
         
          /* PB6 has button needing a pullup */
         
         \
        
         (1                  << _GPIO_P_OUT_Px6_SHIFT)                                       \
        
         | (0                  << _GPIO_P_OUT_Px7_SHIFT)),                                   \
        
         ((0                  << _GPIO_P_OUT_Px0_SHIFT)                                       \
        
         | (0                  << _GPIO_P_OUT_Px1_SHIFT)                                     \
        
         | (1                  << _GPIO_P_OUT_Px2_SHIFT)                                     \
        
         | (0                  << _GPIO_P_OUT_Px3_SHIFT)                                     \
        
         | (0                  << _GPIO_P_OUT_Px4_SHIFT)                                     \
        
         | (
         
          PWRUP_OUT_LED2
         
         << _GPIO_P_OUT_Px5_SHIFT)                                     \
        
         | (
         
          PWRUP_OUT_BUTTON1
         
         << _GPIO_P_OUT_Px6_SHIFT)                                     \
        
         |
         
          /* Temp Sensor default on */
         
         \
        
         (1                  << _GPIO_P_OUT_Px7_SHIFT))                                      \
        
         }

Initialize GPIO powerup output variables.

◆ EEPROM_USES_SHUTDOWN_CONTROL

#define EEPROM_USES_SHUTDOWN_CONTROL

This define does not equate to anything. It is used as a trigger to enable the logic that drives PB7 high in the EEPROM driver.

◆ EMBER_SERIAL_BAUD_CUSTOM [1/2]

#define EMBER_SERIAL_BAUD_CUSTOM 13

This define is the register setting for generating a baud of.

Refer to the EM35x datasheet's discussion on UART baud rates for the equation used to derive this value.

◆ EMBER_SERIAL_BAUD_CUSTOM [2/2]

#define EMBER_SERIAL_BAUD_CUSTOM 13

This define is the register setting for generating a baud of.

Refer to the EM35x datasheet's discussion on UART baud rates for the equation used to derive this value.

◆ ENABLE_ALT_FUNCTION_TX_ACTIVE

#define ENABLE_ALT_FUNCTION_TX_ACTIVE

This define does not equate to anything. It is used as a trigger to enable the TX_ACTIVE alternate function on PC5. It is enabled by default in this board file because the SiGe SE2432L requires the TX_ACTIVE alternate function to operate properly.

◆ ENUMCTRL

#define ENUMCTRL PORTA_PIN(2)

The actual GPIO ENUMCTRL is connected to. The GPIO only needs to be a simple push-pull output or input.

◆ ENUMCTRL_CLR

#define ENUMCTRL_CLR ( ) do { GPIO->P[0].CLR = GPIO_P_CLR_Px2; } while (0)

When the GPIO used for enumeration is configured as push-pull, this macro makes it easy to clear the output state low.

◆ ENUMCTRL_SET

#define ENUMCTRL_SET ( ) do { GPIO->P[0].SET = GPIO_P_SET_Px2; } while (0)

When the GPIO used for enumeration is configured as push-pull, this macro makes it easy to set the output state high.

◆ ENUMCTRL_SETCFG

#define ENUMCTRL_SETCFG ( cfg )

Value:

         
          do
         
         {
         
          SET_CMSIS_REG_FIELD
         
         (GPIO->P[0].CFGL, \
        
         GPIO_P_CFGL_Px2, \
        
         cfg);            \
        
         }
         
          while
         
         (0)

Set the GPIO's configuration to the provided state. The two states used are GPIO_P_CFGz_Pxy_OUT when the device is enumerated and GPIO_P_CFGz_Pxy_IN when the device is not enumerated.

◆ FEM_CRX_BIT

#define FEM_CRX_BIT (0)

Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

◆ FEM_CTX_BIT

#define FEM_CTX_BIT ( BIT32 (PORTC_PIN(5)))

Define the mask for GPIO relevant to the radio in the context of power state. Each bit in the mask indicates the corresponding GPIO which should be affected when invoking halStackRadioPowerUpBoard() or halStackRadioPowerDownBoard() .

◆ halInternalInitRadioHoldOff [1/2]

#define halInternalInitRadioHoldOff ( ) /* no-op */

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use.

◆ halInternalInitRadioHoldOff [2/2]

#define halInternalInitRadioHoldOff ( ) /* no-op */

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use. The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

◆ OSC32K_STARTUP_DELAY_MS [1/2]

#define OSC32K_STARTUP_DELAY_MS (0)

◆ OSC32K_STARTUP_DELAY_MS [2/2]

#define OSC32K_STARTUP_DELAY_MS (0)

◆ PACKET_TRACE [1/2]

#define PACKET_TRACE

This define does not equate to anything. It is used as a trigger to enable Packet Trace support on the breakout board (dev0680).

◆ PACKET_TRACE [2/2]

#define PACKET_TRACE

This define does not equate to anything. It is used as a trigger to enable Packet Trace support on the breakout board (dev0680).

◆ PWRDN_CFG_BUTTON1 [1/2]

#define PWRDN_CFG_BUTTON1 GPIO_P_CFGz_Pxy_IN_PUD

Give GPIO PC6 configuration a friendly name.

◆ PWRDN_CFG_BUTTON1 [2/2]

#define PWRDN_CFG_BUTTON1 GPIO_P_CFGz_Pxy_IN_PUD

Give GPIO PC6 configuration a friendly name.

◆ PWRDN_CFG_DFL_RHO [1/2]

#define PWRDN_CFG_DFL_RHO PWRDN_CFG_DFL_RHO_FOR_DFL

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use.

◆ PWRDN_CFG_DFL_RHO [2/2]

#define PWRDN_CFG_DFL_RHO PWRDN_CFG_DFL_RHO_FOR_DFL

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use. The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

◆ PWRDN_CFG_DFL_RHO_FOR_DFL [1/2]

#define PWRDN_CFG_DFL_RHO_FOR_DFL GPIO_P_CFGz_Pxy_OUT

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use.

◆ PWRDN_CFG_DFL_RHO_FOR_DFL [2/2]

#define PWRDN_CFG_DFL_RHO_FOR_DFL GPIO_P_CFGz_Pxy_OUT

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use. The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

◆ PWRDN_CFG_DFL_RHO_FOR_RHO [1/2]

#define PWRDN_CFG_DFL_RHO_FOR_RHO GPIO_P_CFGz_Pxy_IN_PUD

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use.

◆ PWRDN_CFG_DFL_RHO_FOR_RHO [2/2]

#define PWRDN_CFG_DFL_RHO_FOR_RHO GPIO_P_CFGz_Pxy_IN_PUD

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use. The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

◆ PWRDN_CFG_ENUMCTRL

#define PWRDN_CFG_ENUMCTRL GPIO_P_CFGz_Pxy_IN_PUD

Give the USB configuration a friendly name.

◆ PWRDN_CFG_LED2 [1/2]

#define PWRDN_CFG_LED2 GPIO_P_CFGz_Pxy_OUT

Give the TX_ACTIVE configuration a friendly name.

◆ PWRDN_CFG_LED2 [2/2]

#define PWRDN_CFG_LED2 GPIO_P_CFGz_Pxy_OUT

Give the TX_ACTIVE configuration a friendly name.

ENABLE_ALT_FUNCTION_TX_ACTIVE

◆ PWRDN_CFG_PTI_DATA [1/2]

#define PWRDN_CFG_PTI_DATA GPIO_P_CFGz_Pxy_IN_PUD

Give the packet trace configuration a friendly name.

◆ PWRDN_CFG_PTI_DATA [2/2]

#define PWRDN_CFG_PTI_DATA GPIO_P_CFGz_Pxy_IN_PUD

Give the packet trace configuration a friendly name.

◆ PWRDN_CFG_PTI_EN [1/2]

#define PWRDN_CFG_PTI_EN GPIO_P_CFGz_Pxy_IN_PUD

Give the packet trace configuration a friendly name.

◆ PWRDN_CFG_PTI_EN [2/2]

#define PWRDN_CFG_PTI_EN GPIO_P_CFGz_Pxy_IN_PUD

Give the packet trace configuration a friendly name.

◆ PWRDN_CFG_USBDM

#define PWRDN_CFG_USBDM GPIO_P_CFGz_Pxy_IN_PUD

Give the USB configuration a friendly name.

◆ PWRDN_CFG_USBDP

#define PWRDN_CFG_USBDP GPIO_P_CFGz_Pxy_IN_PUD

Give the USB configuration a friendly name.

◆ PWRDN_CFG_VBUSMON

#define PWRDN_CFG_VBUSMON GPIO_P_CFGz_Pxy_OUT

Give the USB configuration a friendly name.

◆ PWRDN_OUT_BUTTON1 [1/2]

#define PWRDN_OUT_BUTTON1 GPIO_P_OUT_Pxy_PULLUP /* Button needs a pullup */

Give GPIO PC6 configuration a friendly name.

◆ PWRDN_OUT_BUTTON1 [2/2]

#define PWRDN_OUT_BUTTON1 GPIO_P_OUT_Pxy_PULLUP /* Button needs a pullup */

Give GPIO PC6 configuration a friendly name.

◆ PWRDN_OUT_DFL_RHO [1/2]

#define PWRDN_OUT_DFL_RHO PWRDN_OUT_DFL_RHO_FOR_DFL

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use.

◆ PWRDN_OUT_DFL_RHO [2/2]

#define PWRDN_OUT_DFL_RHO PWRDN_OUT_DFL_RHO_FOR_DFL

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use. The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

◆ PWRDN_OUT_DFL_RHO_FOR_DFL [1/2]

#define PWRDN_OUT_DFL_RHO_FOR_DFL 1 /* LED off */

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use.

◆ PWRDN_OUT_DFL_RHO_FOR_DFL [2/2]

#define PWRDN_OUT_DFL_RHO_FOR_DFL 1 /* LED off */

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use. The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

◆ PWRDN_OUT_DFL_RHO_FOR_RHO [1/2]

#define PWRDN_OUT_DFL_RHO_FOR_RHO GPIO_P_OUT_Pxy_PULLDOWN /* Deassert */

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use.

◆ PWRDN_OUT_DFL_RHO_FOR_RHO [2/2]

#define PWRDN_OUT_DFL_RHO_FOR_RHO GPIO_P_OUT_Pxy_PULLDOWN /* Deassert */

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use. The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

◆ PWRDN_OUT_ENUMCTRL

#define PWRDN_OUT_ENUMCTRL GPIO_P_OUT_Pxy_PULLUP

Give the USB configuration a friendly name.

◆ PWRDN_OUT_LED2 [1/2]

#define PWRDN_OUT_LED2 0

Give the TX_ACTIVE configuration a friendly name.

◆ PWRDN_OUT_LED2 [2/2]

#define PWRDN_OUT_LED2 1 /* LED default off */

Give the TX_ACTIVE configuration a friendly name.

ENABLE_ALT_FUNCTION_TX_ACTIVE

◆ PWRDN_OUT_PTI_DATA [1/2]

#define PWRDN_OUT_PTI_DATA GPIO_P_OUT_Pxy_PULLUP

Give the packet trace configuration a friendly name.

◆ PWRDN_OUT_PTI_DATA [2/2]

#define PWRDN_OUT_PTI_DATA GPIO_P_OUT_Pxy_PULLUP

Give the packet trace configuration a friendly name.

◆ PWRDN_OUT_PTI_EN [1/2]

#define PWRDN_OUT_PTI_EN GPIO_P_OUT_Pxy_PULLDOWN

Give the packet trace configuration a friendly name.

◆ PWRDN_OUT_PTI_EN [2/2]

#define PWRDN_OUT_PTI_EN GPIO_P_OUT_Pxy_PULLDOWN

Give the packet trace configuration a friendly name.

◆ PWRDN_OUT_SC1_nRTS

#define PWRDN_OUT_SC1_nRTS 1

◆ PWRDN_OUT_USBDM

#define PWRDN_OUT_USBDM GPIO_P_OUT_Pxy_PULLUP

Give the USB configuration a friendly name.

◆ PWRDN_OUT_USBDP

#define PWRDN_OUT_USBDP GPIO_P_OUT_Pxy_PULLUP

Give the USB configuration a friendly name.

◆ PWRDN_OUT_VBUSMON

#define PWRDN_OUT_VBUSMON 1

Give the USB configuration a friendly name.

◆ PWRUP_CFG_BUTTON1 [1/2]

#define PWRUP_CFG_BUTTON1 GPIO_P_CFGz_Pxy_IN_PUD

Give GPIO PC6 configuration a friendly name.

◆ PWRUP_CFG_BUTTON1 [2/2]

#define PWRUP_CFG_BUTTON1 GPIO_P_CFGz_Pxy_IN_PUD

Give GPIO PC6 configuration a friendly name.

◆ PWRUP_CFG_DFL_RHO [1/2]

#define PWRUP_CFG_DFL_RHO PWRUP_CFG_DFL_RHO_FOR_DFL

The following definitions are helpers for managing Radio HoldOff and should not be modified.

(defined(RADIO_HOLDOFF) && defined(RHO_GPIO))

◆ PWRUP_CFG_DFL_RHO [2/2]

#define PWRUP_CFG_DFL_RHO PWRUP_CFG_DFL_RHO_FOR_DFL

The following definitions are helpers for managing Radio HoldOff and should not be modified.

(defined(RADIO_HOLDOFF) && defined(RHO_GPIO))

◆ PWRUP_CFG_DFL_RHO_FOR_DFL [1/2]

#define PWRUP_CFG_DFL_RHO_FOR_DFL GPIO_P_CFGz_Pxy_OUT

Configuration of GPIO for default behavior.

◆ PWRUP_CFG_DFL_RHO_FOR_DFL [2/2]

#define PWRUP_CFG_DFL_RHO_FOR_DFL GPIO_P_CFGz_Pxy_OUT

Configuration of GPIO for default behavior.

◆ PWRUP_CFG_DFL_RHO_FOR_RHO [1/2]

#define PWRUP_CFG_DFL_RHO_FOR_RHO GPIO_P_CFGz_Pxy_IN_PUD

Configuration of GPIO for Radio HoldOff operation.

◆ PWRUP_CFG_DFL_RHO_FOR_RHO [2/2]

#define PWRUP_CFG_DFL_RHO_FOR_RHO GPIO_P_CFGz_Pxy_IN_PUD

Configuration of GPIO for Radio HoldOff operation.

◆ PWRUP_CFG_ENUMCTRL

#define PWRUP_CFG_ENUMCTRL GPIO_P_CFGz_Pxy_OUT_ALT

Give the USB configuration a friendly name.

◆ PWRUP_CFG_LED2 [1/2]

#define PWRUP_CFG_LED2 GPIO_P_CFGz_Pxy_OUT_ALT

Give the TX_ACTIVE configuration a friendly name.

◆ PWRUP_CFG_LED2 [2/2]

#define PWRUP_CFG_LED2 GPIO_P_CFGz_Pxy_OUT

Give the TX_ACTIVE configuration a friendly name.

ENABLE_ALT_FUNCTION_TX_ACTIVE

◆ PWRUP_CFG_PTI_DATA [1/2]

#define PWRUP_CFG_PTI_DATA GPIO_P_CFGz_Pxy_OUT_ALT

Give the packet trace configuration a friendly name.

◆ PWRUP_CFG_PTI_DATA [2/2]

#define PWRUP_CFG_PTI_DATA GPIO_P_CFGz_Pxy_OUT_ALT

Give the packet trace configuration a friendly name.

◆ PWRUP_CFG_PTI_EN [1/2]

#define PWRUP_CFG_PTI_EN GPIO_P_CFGz_Pxy_OUT_ALT

Give the packet trace configuration a friendly name.

◆ PWRUP_CFG_PTI_EN [2/2]

#define PWRUP_CFG_PTI_EN GPIO_P_CFGz_Pxy_OUT_ALT

Give the packet trace configuration a friendly name.

◆ PWRUP_CFG_SC1_TXD

#define PWRUP_CFG_SC1_TXD GPIO_P_CFGz_Pxy_OUT_ALT

Give GPIO SC1 TXD and nRTS configurations friendly names.

SLEEPY_IP_MODEM_UART

◆ PWRUP_CFG_USBDM

#define PWRUP_CFG_USBDM GPIO_P_CFGz_Pxy_OUT_ALT

Give the USB configuration a friendly name.

◆ PWRUP_CFG_USBDP

#define PWRUP_CFG_USBDP GPIO_P_CFGz_Pxy_IN

Give the USB configuration a friendly name.

◆ PWRUP_CFG_VBUSMON

#define PWRUP_CFG_VBUSMON GPIO_P_CFGz_Pxy_OUT

Give the USB configuration a friendly name.

◆ PWRUP_OUT_BUTTON1 [1/2]

#define PWRUP_OUT_BUTTON1 GPIO_P_OUT_Pxy_PULLUP /* Button needs a pullup */

Give GPIO PC6 configuration a friendly name.

◆ PWRUP_OUT_BUTTON1 [2/2]

#define PWRUP_OUT_BUTTON1 GPIO_P_OUT_Pxy_PULLUP /* Button needs a pullup */

Give GPIO PC6 configuration a friendly name.

◆ PWRUP_OUT_DFL_RHO [1/2]

#define PWRUP_OUT_DFL_RHO PWRUP_OUT_DFL_RHO_FOR_DFL

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use.

◆ PWRUP_OUT_DFL_RHO [2/2]

#define PWRUP_OUT_DFL_RHO PWRUP_OUT_DFL_RHO_FOR_DFL

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use. The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

◆ PWRUP_OUT_DFL_RHO_FOR_DFL [1/2]

#define PWRUP_OUT_DFL_RHO_FOR_DFL 1 /* LED default off */

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use.

◆ PWRUP_OUT_DFL_RHO_FOR_DFL [2/2]

#define PWRUP_OUT_DFL_RHO_FOR_DFL 1 /* LED default off */

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use. The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

◆ PWRUP_OUT_DFL_RHO_FOR_RHO [1/2]

#define PWRUP_OUT_DFL_RHO_FOR_RHO GPIO_P_OUT_Pxy_PULLDOWN /* Deassert */

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use.

◆ PWRUP_OUT_DFL_RHO_FOR_RHO [2/2]

#define PWRUP_OUT_DFL_RHO_FOR_RHO GPIO_P_OUT_Pxy_PULLDOWN /* Deassert */

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use. The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

◆ PWRUP_OUT_ENUMCTRL

#define PWRUP_OUT_ENUMCTRL 0

Give the USB configuration a friendly name.

◆ PWRUP_OUT_LED2 [1/2]

#define PWRUP_OUT_LED2 0

Give the TX_ACTIVE configuration a friendly name.

◆ PWRUP_OUT_LED2 [2/2]

#define PWRUP_OUT_LED2 1 /* LED default off */

Give the TX_ACTIVE configuration a friendly name.

ENABLE_ALT_FUNCTION_TX_ACTIVE

◆ PWRUP_OUT_PTI_DATA [1/2]

#define PWRUP_OUT_PTI_DATA 1

Give the packet trace configuration a friendly name.

◆ PWRUP_OUT_PTI_DATA [2/2]

#define PWRUP_OUT_PTI_DATA 1

Give the packet trace configuration a friendly name.

◆ PWRUP_OUT_PTI_EN [1/2]

#define PWRUP_OUT_PTI_EN 0

Give the packet trace configuration a friendly name.

◆ PWRUP_OUT_PTI_EN [2/2]

#define PWRUP_OUT_PTI_EN 0

Give the packet trace configuration a friendly name.

◆ PWRUP_OUT_USBDM

#define PWRUP_OUT_USBDM 0

Give the USB configuration a friendly name.

◆ PWRUP_OUT_USBDP

#define PWRUP_OUT_USBDP 0

Give the USB configuration a friendly name.

◆ PWRUP_OUT_VBUSMON

#define PWRUP_OUT_VBUSMON 1

Give the USB configuration a friendly name.

◆ RHO_ASSERTED [1/2]

#define RHO_ASSERTED 1

The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

◆ RHO_ASSERTED [2/2]

#define RHO_ASSERTED 1

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use. The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

◆ RHO_CFG [1/2]

#define RHO_CFG (GPIO->P[0].CFGH)

The GPIO configuration register for Radio HoldOff.

◆ RHO_CFG [2/2]

#define RHO_CFG (GPIO->P[0].CFGH)

The GPIO configuration register for Radio HoldOff.

◆ RHO_FLAG_BIT [1/2]

#define RHO_FLAG_BIT EVENT_GPIO_FLAG_IRQD

The interrupt flag bit for Radio HoldOff.

◆ RHO_FLAG_BIT [2/2]

#define RHO_FLAG_BIT EVENT_GPIO_FLAG_IRQD

The interrupt flag bit for Radio HoldOff.

◆ RHO_GPIO

#define RHO_GPIO PORTA_PIN(6)

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use.

◆ RHO_IN [1/2]

#define RHO_IN (GPIO->P[0].IN)

The GPIO input register for Radio HoldOff.

◆ RHO_IN [2/2]

#define RHO_IN (GPIO->P[0].IN)

The GPIO input register for Radio HoldOff.

◆ RHO_INT_EN_BIT [1/2]

#define RHO_INT_EN_BIT BIT32 ( RHO_INT_EN_IRQN )

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use.

◆ RHO_INT_EN_BIT [2/2]

#define RHO_INT_EN_BIT BIT32 ( RHO_INT_EN_IRQN )

The actual GPIO used to control Radio HoldOff.

Note: If RHO_GPIO is not defined, then Radio HoldOff support will not be built in even for runtime use. The GPIO signal level to assert Radio HoldOff (1=high, 0=low).

◆ RHO_INT_EN_IRQN [1/2]

#define RHO_INT_EN_IRQN IRQD_IRQn

The interrupt enable bit for Radio HoldOff.

◆ RHO_INT_EN_IRQN [2/2]

#define RHO_INT_EN_IRQN IRQD_IRQn

The interrupt enable bit for Radio HoldOff.

◆ RHO_INTCFG [1/2]

#define RHO_INTCFG (EVENT_GPIO->CFGD)

The interrupt configuration register for Radio HoldOff.

◆ RHO_INTCFG [2/2]

#define RHO_INTCFG (EVENT_GPIO->CFGD)

The interrupt configuration register for Radio HoldOff.

◆ RHO_ISR [1/2]

#define RHO_ISR halIrqDIsr

The interrupt service routine for Radio HoldOff. Remember there may be other things that might want to use this IRQ.

◆ RHO_ISR [2/2]

#define RHO_ISR halIrqDIsr

The interrupt service routine for Radio HoldOff. Remember there may be other things that might want to use this IRQ.

◆ RHO_MISS_BIT [1/2]

#define RHO_MISS_BIT EVENT_MISS_MISS_IRQD

The missed interrupt bit for Radio HoldOff.

◆ RHO_MISS_BIT [2/2]

#define RHO_MISS_BIT EVENT_MISS_MISS_IRQD

The missed interrupt bit for Radio HoldOff.

◆ RHO_OUT [1/2]

#define RHO_OUT (GPIO->P[0].OUT)

The GPIO output register for Radio HoldOff.

◆ RHO_OUT [2/2]

#define RHO_OUT (GPIO->P[0].OUT)

The GPIO output register for Radio HoldOff.

◆ RHO_SEL [1/2]

#define RHO_SEL ( ) do { GPIO->IRQDSEL = RHO_GPIO ; } while (0)

Point the proper IRQ at the desired pin for Radio HoldOff. Remember there may be other things that might want to use this IRQ.

◆ RHO_SEL [2/2]

#define RHO_SEL ( ) do { GPIO->IRQDSEL = RHO_GPIO ; } while (0)

Point the proper IRQ at the desired pin for Radio HoldOff. Remember there may be other things that might want to use this IRQ.

◆ SET_POWERDOWN_GPIO_CFG_REGISTERS [1/2]

#define SET_POWERDOWN_GPIO_CFG_REGISTERS ( )

Value:

         GPIO->P[0].CFGL =
         
          gpioCfgPowerDown
         
         [0];   \
        
         GPIO->P[0].CFGH =
         
          gpioCfgPowerDown
         
         [1];   \
        
         GPIO->P[1].CFGL =
         
          gpioCfgPowerDown
         
         [2];   \
        
         GPIO->P[1].CFGH =
         
          gpioCfgPowerDown
         
         [3];   \
        
         GPIO->P[2].CFGL =
         
          gpioCfgPowerDown
         
         [4];   \
        
         GPIO->P[2].CFGH =
         
          gpioCfgPowerDown
         
         [5];

Set powerdown GPIO configuration registers.

◆ SET_POWERDOWN_GPIO_CFG_REGISTERS [2/2]

#define SET_POWERDOWN_GPIO_CFG_REGISTERS ( )

Value:

         GPIO->P[0].CFGL =
         
          gpioCfgPowerDown
         
         [0];   \
        
         GPIO->P[0].CFGH =
         
          gpioCfgPowerDown
         
         [1];   \
        
         GPIO->P[1].CFGL =
         
          gpioCfgPowerDown
         
         [2];   \
        
         GPIO->P[1].CFGH =
         
          gpioCfgPowerDown
         
         [3];   \
        
         GPIO->P[2].CFGL =
         
          gpioCfgPowerDown
         
         [4];   \
        
         GPIO->P[2].CFGH =
         
          gpioCfgPowerDown
         
         [5];

Set powerdown GPIO configuration registers.

◆ SET_POWERDOWN_GPIO_OUTPUT_DATA_REGISTERS [1/2]

#define SET_POWERDOWN_GPIO_OUTPUT_DATA_REGISTERS ( )

Value:

         GPIO->P[0].OUT =
         
          gpioOutPowerDown
         
         [0];            \
        
         GPIO->P[1].OUT =
         
          gpioOutPowerDown
         
         [1];            \
        
         GPIO->P[2].OUT =
         
          gpioOutPowerDown
         
         [2];

Set powerdown GPIO output registers.

◆ SET_POWERDOWN_GPIO_OUTPUT_DATA_REGISTERS [2/2]

#define SET_POWERDOWN_GPIO_OUTPUT_DATA_REGISTERS ( )

Value:

         GPIO->P[0].OUT =
         
          gpioOutPowerDown
         
         [0];            \
        
         GPIO->P[1].OUT =
         
          gpioOutPowerDown
         
         [1];            \
        
         GPIO->P[2].OUT =
         
          gpioOutPowerDown
         
         [2];

Set powerdown GPIO output registers.

◆ SET_POWERUP_GPIO_CFG_REGISTERS [1/2]

#define SET_POWERUP_GPIO_CFG_REGISTERS ( )

Value:

         GPIO->P[0].CFGL =
         
          gpioCfgPowerUp
         
         [0];   \
        
         GPIO->P[0].CFGH =
         
          gpioCfgPowerUp
         
         [1];   \
        
         GPIO->P[1].CFGL =
         
          gpioCfgPowerUp
         
         [2];   \
        
         GPIO->P[1].CFGH =
         
          gpioCfgPowerUp
         
         [3];   \
        
         GPIO->P[2].CFGL =
         
          gpioCfgPowerUp
         
         [4];   \
        
         GPIO->P[2].CFGH =
         
          gpioCfgPowerUp
         
         [5];

Set powerup GPIO configuration registers.

◆ SET_POWERUP_GPIO_CFG_REGISTERS [2/2]

#define SET_POWERUP_GPIO_CFG_REGISTERS ( )

Value:

         GPIO->P[0].CFGL =
         
          gpioCfgPowerUp
         
         [0];   \
        
         GPIO->P[0].CFGH =
         
          gpioCfgPowerUp
         
         [1];   \
        
         GPIO->P[1].CFGL =
         
          gpioCfgPowerUp
         
         [2];   \
        
         GPIO->P[1].CFGH =
         
          gpioCfgPowerUp
         
         [3];   \
        
         GPIO->P[2].CFGL =
         
          gpioCfgPowerUp
         
         [4];   \
        
         GPIO->P[2].CFGH =
         
          gpioCfgPowerUp
         
         [5];

Set powerup GPIO configuration registers.

◆ SET_POWERUP_GPIO_OUTPUT_DATA_REGISTERS [1/2]

#define SET_POWERUP_GPIO_OUTPUT_DATA_REGISTERS ( )

Value:

         GPIO->P[0].OUT =
         
          gpioOutPowerUp
         
         [0];            \
        
         GPIO->P[1].OUT =
         
          gpioOutPowerUp
         
         [1];            \
        
         GPIO->P[2].OUT =
         
          gpioOutPowerUp
         
         [2];

Set powerup GPIO output registers.

◆ SET_POWERUP_GPIO_OUTPUT_DATA_REGISTERS [2/2]

#define SET_POWERUP_GPIO_OUTPUT_DATA_REGISTERS ( )

Value:

         GPIO->P[0].OUT =
         
          gpioOutPowerUp
         
         [0];            \
        
         GPIO->P[1].OUT =
         
          gpioOutPowerUp
         
         [1];            \
        
         GPIO->P[2].OUT =
         
          gpioOutPowerUp
         
         [2];

Set powerup GPIO output registers.

◆ SET_RESUME_GPIO_CFG_REGISTERS

#define SET_RESUME_GPIO_CFG_REGISTERS ( )

Value:

         
          /* GPIO->P[0].CFGL USB untouched! */
         
         \
        
         GPIO->P[0].CFGH =
         
          gpioCfgPowerUp
         
         [1];  \
        
         GPIO->P[1].CFGL =
         
          gpioCfgPowerUp
         
         [2];  \
        
         GPIO->P[1].CFGH =
         
          gpioCfgPowerUp
         
         [3];  \
        
         GPIO->P[2].CFGL =
         
          gpioCfgPowerUp
         
         [4];  \
        
         GPIO->P[2].CFGH =
         
          gpioCfgPowerUp
         
         [5];

Set resume GPIO configuration registers. Identical to SET_POWERUP.

◆ SET_RESUME_GPIO_OUTPUT_DATA_REGISTERS

#define SET_RESUME_GPIO_OUTPUT_DATA_REGISTERS ( )

Value:

         GPIO->P[0].OUT = (GPIO->P[0].OUT & 0x0F)
         
          /*USB untouched*/
         
         \
        
         | (
         
          gpioOutPowerUp
         
         [0] & 0xF0);             \
        
         GPIO->P[1].OUT =
         
          gpioOutPowerUp
         
         [1];                        \
        
         GPIO->P[2].OUT =
         
          gpioOutPowerUp
         
         [2];

Set resume GPIO output registers. Identical to SET_POWERUP.

◆ SET_SUSPEND_GPIO_CFG_REGISTERS

#define SET_SUSPEND_GPIO_CFG_REGISTERS ( )

Value:

         
          /* GPIO->P[0].CFGL USB untouched! */
         
         \
        
         GPIO->P[0].CFGH =
         
          gpioCfgPowerDown
         
         [1]; \
        
         GPIO->P[1].CFGL =
         
          gpioCfgPowerDown
         
         [2]; \
        
         GPIO->P[1].CFGH =
         
          gpioCfgPowerDown
         
         [3]; \
        
         GPIO->P[2].CFGL =
         
          gpioCfgPowerDown
         
         [4]; \
        
         GPIO->P[2].CFGH =
         
          gpioCfgPowerDown
         
         [5];

Set suspend GPIO configuration registers. SET_POWERDOWN minus USB regs.

◆ SET_SUSPEND_GPIO_OUTPUT_DATA_REGISTERS

#define SET_SUSPEND_GPIO_OUTPUT_DATA_REGISTERS ( )

Value:

         GPIO->P[0].OUT = (GPIO->P[0].OUT & 0x0F)
         
          /*USB untouched*/
         
         \
        
         | (
         
          gpioOutPowerDown
         
         [0] & 0xF0);            \
        
         GPIO->P[1].OUT =
         
          gpioOutPowerDown
         
         [1];                       \
        
         GPIO->P[2].OUT =
         
          gpioOutPowerDown
         
         [2];

Set suspend GPIO output registers. SET_POWERDOWN minus USB regs.

◆ TEMP_SENSOR_ADC_CHANNEL [1/2]

#define TEMP_SENSOR_ADC_CHANNEL ADC_SOURCE_ADC0_VREF2

The analog input channel to use for the temperature sensor.

◆ TEMP_SENSOR_ADC_CHANNEL [2/2]

#define TEMP_SENSOR_ADC_CHANNEL ADC_SOURCE_ADC0_VREF2

The analog input channel to use for the temperature sensor.

◆ TEMP_SENSOR_SCALE_FACTOR [1/2]

#define TEMP_SENSOR_SCALE_FACTOR 1

The scale factor to compensate for different input ranges.

◆ TEMP_SENSOR_SCALE_FACTOR [2/2]

#define TEMP_SENSOR_SCALE_FACTOR 1

The scale factor to compensate for different input ranges.

◆ USB_MAX_POWER

#define USB_MAX_POWER (50)

USB Max Power parameter (bMaxPower) the driver will report to the host in the Configuration Descriptor.

◆ USB_REMOTEWKUPEN_STATE

#define USB_REMOTEWKUPEN_STATE (1)

USB Remote Wakeup Enable.

Set the define USB_REMOTEWKUPEN_STATE: 0 remote wakeup is disabled. 1 remote wakeup is enabled.

◆ USB_SELFPWRD_STATE

#define USB_SELFPWRD_STATE (1)

The USB power state.

Set the define USB_SELFPWRD_STATE: 0 if the device is bus powered. 1 if the device self powered.

◆ VBUSMON

#define VBUSMON GPIO_P_IN_Px3

The actual GPIO VBUSMON is connected to. Remember that other pieces might want to use PA3.

Leaving VBUSMON undefined will keep VBUS Monitoring functionality from being compiled in and not conflict with other pieces that might want to use the GPIO or IRQ that VBUS Monitoring needs.

◆ VBUSMON_FLAG_BIT

#define VBUSMON_FLAG_BIT EVENT_GPIO_FLAG_IRQD

The interrupt flag bit for VBUSMON.

◆ VBUSMON_IN

#define VBUSMON_IN (GPIO->P[0].IN)

The GPIO input register for VBUSMON.

◆ VBUSMON_INT_EN_BIT

#define VBUSMON_INT_EN_BIT BIT32 ( VBUSMON_INT_EN_IRQN )

The actual GPIO VBUSMON is connected to. Remember that other pieces might want to use PA3.

Leaving VBUSMON undefined will keep VBUS Monitoring functionality from being compiled in and not conflict with other pieces that might want to use the GPIO or IRQ that VBUS Monitoring needs.

◆ VBUSMON_INT_EN_IRQN

#define VBUSMON_INT_EN_IRQN IRQD_IRQn

The interrupt enable bit for VBUSMON.

◆ VBUSMON_INTCFG

#define VBUSMON_INTCFG (EVENT_GPIO->CFGD)

The interrupt configuration register for VBUSMON.

◆ VBUSMON_ISR

#define VBUSMON_ISR halIrqDIsr

The interrupt service routine for VBUSMON. Remember that other pieces that might want to use IRQC.

◆ VBUSMON_MISS_BIT

#define VBUSMON_MISS_BIT EVENT_MISS_MISS_IRQD

The missed interrupt bit for VBUSMON.

◆ VBUSMON_SEL

#define VBUSMON_SEL ( ) do { GPIO->IRQDSEL = PORTA_PIN(3); } while (0)

Point the proper IRQ at the desired pin for VBUSMON. Remember that other pieces that might want to use IRQC.

Note: For this board, IRQC is pointed at PA3.

◆ VBUSMON_SETCFG

#define VBUSMON_SETCFG ( )

Value:

         
          do
         
         {
         
          SET_CMSIS_REG_FIELD
         
         (GPIO->P[0].CFGL,      \
        
         GPIO_P_CFGL_Px3,      \
        
         _GPIO_P_CFGL_Px3_IN); \
        
         }
         
          while
         
         (0)

The GPIO configuration needed for VBUSMON. The configuration needs to be a simple input that will monitor for edge tansitions.