em_core.h File Reference

Core interrupt handling API.

Version
5.5.0

License

Copyright 2016 Silicon Laboratories, Inc. www.silabs.com

Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:

  1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software.
  2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
  3. This notice may not be removed or altered from any source distribution.

DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no obligation to support this Software. Silicon Labs is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.

Silicon Labs will not be liable for any consequential, incidental, or special damages, or any other relief, or for any claim by any third party, arising from your use of this Software.

Definition in file em_core.h.

#include "em_device.h"
#include "em_common.h"
#include <stdbool.h>

Data Structures

struct  CORE_nvicMask_t
 

Macros

#define CORE_ATOMIC_IRQ_DISABLE()    CORE_AtomicDisableIrq()
 
#define CORE_ATOMIC_IRQ_ENABLE()    CORE_AtomicEnableIrq()
 
#define CORE_ATOMIC_METHOD_BASEPRI   1
 
#define CORE_ATOMIC_METHOD_PRIMASK   0
 
#define CORE_ATOMIC_SECTION(yourcode)
 
#define CORE_CRITICAL_IRQ_DISABLE()   CORE_CriticalDisableIrq()
 
#define CORE_CRITICAL_IRQ_ENABLE()   CORE_CriticalEnableIrq()
 
#define CORE_CRITICAL_SECTION(yourcode)
 
#define CORE_DECLARE_IRQ_STATE   CORE_irqState_t irqState
 
#define CORE_DECLARE_NVIC_MASK(x)    CORE_nvicMask_t x
 
#define CORE_DECLARE_NVIC_STATE   CORE_nvicMask_t nvicState
 
#define CORE_DECLARE_NVIC_ZEROMASK(x)   CORE_nvicMask_t x = { { 0 } }
 
#define CORE_DEFAULT_VECTOR_TABLE_ENTRIES   (EXT_IRQ_COUNT + 16)
 
#define CORE_ENTER_ATOMIC()    irqState = CORE_EnterAtomic()
 
#define CORE_ENTER_CRITICAL()    irqState = CORE_EnterCritical()
 
#define CORE_ENTER_NVIC(disable)   CORE_EnterNvicMask(&nvicState, disable)
 
#define CORE_EXIT_ATOMIC()    CORE_ExitAtomic(irqState)
 
#define CORE_EXIT_CRITICAL()    CORE_ExitCritical(irqState)
 
#define CORE_EXIT_NVIC()    CORE_NvicEnableMask(&nvicState)
 
#define CORE_IN_IRQ_CONTEXT()    CORE_InIrqContext()
 
#define CORE_IRQ_DISABLED()    CORE_IrqIsDisabled()
 
#define CORE_NVIC_DISABLE(mask)    CORE_NvicDisableMask(mask)
 
#define CORE_NVIC_ENABLE(mask)    CORE_NvicEnableMask(mask)
 
#define CORE_NVIC_REG_WORDS   ((EXT_IRQ_COUNT + 31) / 32)
 
#define CORE_NVIC_SECTION(mask, yourcode)
 
#define CORE_YIELD_ATOMIC()    CORE_YieldAtomic()
 
#define CORE_YIELD_CRITICAL()    CORE_YieldCritical()
 
#define CORE_YIELD_NVIC(enable)    CORE_YieldNvicMask(enable)
 

Typedefs

typedef uint32_t CORE_irqState_t
 

Functions

void CORE_AtomicDisableIrq (void)
 Disable interrupts.
 
void CORE_AtomicEnableIrq (void)
 Enable interrupts.
 
void CORE_CriticalDisableIrq (void)
 Disable interrupts.
 
void CORE_CriticalEnableIrq (void)
 Enable interrupts.
 
CORE_irqState_t CORE_EnterAtomic (void)
 Enter an ATOMIC section.
 
CORE_irqState_t CORE_EnterCritical (void)
 Enter a CRITICAL section.
 
void CORE_EnterNvicMask (CORE_nvicMask_t *nvicState, const CORE_nvicMask_t *disable)
 Enter a NVIC mask section.
 
void CORE_ExitAtomic (CORE_irqState_t irqState)
 Exit an ATOMIC section.
 
void CORE_ExitCritical (CORE_irqState_t irqState)
 Exit a CRITICAL section.
 
void CORE_GetNvicEnabledMask (CORE_nvicMask_t *mask)
 Get the current NVIC enable mask state.
 
bool CORE_GetNvicMaskDisableState (const CORE_nvicMask_t *mask)
 Get NVIC disable state for a given mask.
 
void * CORE_GetNvicRamTableHandler (IRQn_Type irqN)
 Utility function to get the handler for a specific interrupt.
 
bool CORE_InIrqContext (void)
 Check whether the current CPU operation mode is handler mode.
 
void CORE_InitNvicVectorTable (uint32_t *sourceTable, uint32_t sourceSize, uint32_t *targetTable, uint32_t targetSize, void *defaultHandler, bool overwriteActive)
 Initialize an interrupt vector table by copying table entries from a source to a target table.
 
bool CORE_IrqIsBlocked (IRQn_Type irqN)
 Check if a specific interrupt is disabled or blocked.
 
bool CORE_IrqIsDisabled (void)
 Check if interrupts are disabled.
 
void CORE_NvicDisableMask (const CORE_nvicMask_t *disable)
 Disable NVIC interrupts.
 
void CORE_NvicEnableMask (const CORE_nvicMask_t *enable)
 Set current NVIC interrupt enable mask.
 
bool CORE_NvicIRQDisabled (IRQn_Type irqN)
 Check if an NVIC interrupt is disabled.
 
void CORE_NvicMaskClearIRQ (IRQn_Type irqN, CORE_nvicMask_t *mask)
 Utility function to clear an IRQn bit in a NVIC enable/disable mask.
 
void CORE_NvicMaskSetIRQ (IRQn_Type irqN, CORE_nvicMask_t *mask)
 Utility function to set an IRQn bit in a NVIC enable/disable mask.
 
void CORE_SetNvicRamTableHandler (IRQn_Type irqN, void *handler)
 Utility function to set the handler for a specific interrupt.
 
void CORE_YieldAtomic (void)
 Brief interrupt enable/disable sequence to allow handling of pending interrupts.
 
void CORE_YieldCritical (void)
 Brief interrupt enable/disable sequence to allow handling of pending interrupts.
 
void CORE_YieldNvicMask (const CORE_nvicMask_t *enable)
 Brief NVIC interrupt enable/disable sequence to allow handling of pending interrupts.