DMAREQ Bit FieldsDevices > DMAREQ
Macros | |
#define | DMAREQ_ADC0_SCAN ((8 << 16) + 1) |
#define | DMAREQ_ADC0_SINGLE ((8 << 16) + 0) |
#define | DMAREQ_ADC1_SCAN ((9 << 16) + 1) |
#define | DMAREQ_ADC1_SINGLE ((9 << 16) + 0) |
#define | DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) |
#define | DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) |
#define | DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) |
#define | DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) |
#define | DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) |
#define | DMAREQ_CSEN_BSLN ((61 << 16) + 1) |
#define | DMAREQ_CSEN_DATA ((61 << 16) + 0) |
#define | DMAREQ_EBI_DDEMPTY ((50 << 16) + 3) |
#define | DMAREQ_EBI_HSYNC ((50 << 16) + 5) |
#define | DMAREQ_EBI_PXL0EMPTY ((50 << 16) + 0) |
#define | DMAREQ_EBI_PXL1EMPTY ((50 << 16) + 1) |
#define | DMAREQ_EBI_PXLFULL ((50 << 16) + 2) |
#define | DMAREQ_EBI_VSYNC ((50 << 16) + 4) |
#define | DMAREQ_I2C0_RXDATAV ((22 << 16) + 0) |
#define | DMAREQ_I2C0_TXBL ((22 << 16) + 1) |
#define | DMAREQ_I2C1_RXDATAV ((23 << 16) + 0) |
#define | DMAREQ_I2C1_TXBL ((23 << 16) + 1) |
#define | DMAREQ_I2C2_RXDATAV ((24 << 16) + 0) |
#define | DMAREQ_I2C2_TXBL ((24 << 16) + 1) |
#define | DMAREQ_LESENSE_BUFDATAV ((62 << 16) + 0) |
#define | DMAREQ_LEUART0_RXDATAV ((20 << 16) + 0) |
#define | DMAREQ_LEUART0_TXBL ((20 << 16) + 1) |
#define | DMAREQ_LEUART0_TXEMPTY ((20 << 16) + 2) |
#define | DMAREQ_LEUART1_RXDATAV ((21 << 16) + 0) |
#define | DMAREQ_LEUART1_TXBL ((21 << 16) + 1) |
#define | DMAREQ_LEUART1_TXEMPTY ((21 << 16) + 2) |
#define | DMAREQ_MSC_WDATA ((48 << 16) + 0) |
#define | DMAREQ_PRS_REQ0 ((1 << 16) + 0) |
#define | DMAREQ_PRS_REQ1 ((1 << 16) + 1) |
#define | DMAREQ_TIMER0_CC0 ((25 << 16) + 1) |
#define | DMAREQ_TIMER0_CC1 ((25 << 16) + 2) |
#define | DMAREQ_TIMER0_CC2 ((25 << 16) + 3) |
#define | DMAREQ_TIMER0_UFOF ((25 << 16) + 0) |
#define | DMAREQ_TIMER1_CC0 ((26 << 16) + 1) |
#define | DMAREQ_TIMER1_CC1 ((26 << 16) + 2) |
#define | DMAREQ_TIMER1_CC2 ((26 << 16) + 3) |
#define | DMAREQ_TIMER1_CC3 ((26 << 16) + 4) |
#define | DMAREQ_TIMER1_UFOF ((26 << 16) + 0) |
#define | DMAREQ_TIMER2_CC0 ((27 << 16) + 1) |
#define | DMAREQ_TIMER2_CC1 ((27 << 16) + 2) |
#define | DMAREQ_TIMER2_CC2 ((27 << 16) + 3) |
#define | DMAREQ_TIMER2_UFOF ((27 << 16) + 0) |
#define | DMAREQ_TIMER3_CC0 ((28 << 16) + 1) |
#define | DMAREQ_TIMER3_CC1 ((28 << 16) + 2) |
#define | DMAREQ_TIMER3_CC2 ((28 << 16) + 3) |
#define | DMAREQ_TIMER3_UFOF ((28 << 16) + 0) |
#define | DMAREQ_TIMER4_CC0 ((29 << 16) + 1) |
#define | DMAREQ_TIMER4_CC1 ((29 << 16) + 2) |
#define | DMAREQ_TIMER4_CC2 ((29 << 16) + 3) |
#define | DMAREQ_TIMER4_UFOF ((29 << 16) + 0) |
#define | DMAREQ_TIMER5_CC0 ((30 << 16) + 1) |
#define | DMAREQ_TIMER5_CC1 ((30 << 16) + 2) |
#define | DMAREQ_TIMER5_CC2 ((30 << 16) + 3) |
#define | DMAREQ_TIMER5_UFOF ((30 << 16) + 0) |
#define | DMAREQ_TIMER6_CC0 ((31 << 16) + 1) |
#define | DMAREQ_TIMER6_CC1 ((31 << 16) + 2) |
#define | DMAREQ_TIMER6_CC2 ((31 << 16) + 3) |
#define | DMAREQ_TIMER6_UFOF ((31 << 16) + 0) |
#define | DMAREQ_UART0_RXDATAV ((18 << 16) + 0) |
#define | DMAREQ_UART0_TXBL ((18 << 16) + 1) |
#define | DMAREQ_UART0_TXEMPTY ((18 << 16) + 2) |
#define | DMAREQ_UART1_RXDATAV ((19 << 16) + 0) |
#define | DMAREQ_UART1_TXBL ((19 << 16) + 1) |
#define | DMAREQ_UART1_TXEMPTY ((19 << 16) + 2) |
#define | DMAREQ_USART0_RXDATAV ((12 << 16) + 0) |
#define | DMAREQ_USART0_TXBL ((12 << 16) + 1) |
#define | DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) |
#define | DMAREQ_USART1_RXDATAV ((13 << 16) + 0) |
#define | DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) |
#define | DMAREQ_USART1_TXBL ((13 << 16) + 1) |
#define | DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) |
#define | DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) |
#define | DMAREQ_USART2_RXDATAV ((14 << 16) + 0) |
#define | DMAREQ_USART2_TXBL ((14 << 16) + 1) |
#define | DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) |
#define | DMAREQ_USART3_RXDATAV ((15 << 16) + 0) |
#define | DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) |
#define | DMAREQ_USART3_TXBL ((15 << 16) + 1) |
#define | DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) |
#define | DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) |
#define | DMAREQ_USART4_RXDATAV ((16 << 16) + 0) |
#define | DMAREQ_USART4_RXDATAVRIGHT ((16 << 16) + 3) |
#define | DMAREQ_USART4_TXBL ((16 << 16) + 1) |
#define | DMAREQ_USART4_TXBLRIGHT ((16 << 16) + 4) |
#define | DMAREQ_USART4_TXEMPTY ((16 << 16) + 2) |
#define | DMAREQ_USART5_RXDATAV ((17 << 16) + 0) |
#define | DMAREQ_USART5_TXBL ((17 << 16) + 1) |
#define | DMAREQ_USART5_TXEMPTY ((17 << 16) + 2) |
#define | DMAREQ_VDAC0_CH0 ((10 << 16) + 0) |
#define | DMAREQ_VDAC0_CH1 ((10 << 16) + 1) |
#define | DMAREQ_WTIMER0_CC0 ((32 << 16) + 1) |
#define | DMAREQ_WTIMER0_CC1 ((32 << 16) + 2) |
#define | DMAREQ_WTIMER0_CC2 ((32 << 16) + 3) |
#define | DMAREQ_WTIMER0_UFOF ((32 << 16) + 0) |
#define | DMAREQ_WTIMER1_CC0 ((33 << 16) + 1) |
#define | DMAREQ_WTIMER1_CC1 ((33 << 16) + 2) |
#define | DMAREQ_WTIMER1_CC2 ((33 << 16) + 3) |
#define | DMAREQ_WTIMER1_CC3 ((33 << 16) + 4) |
#define | DMAREQ_WTIMER1_UFOF ((33 << 16) + 0) |
#define | DMAREQ_WTIMER2_CC0 ((34 << 16) + 1) |
#define | DMAREQ_WTIMER2_CC1 ((34 << 16) + 2) |
#define | DMAREQ_WTIMER2_CC2 ((34 << 16) + 3) |
#define | DMAREQ_WTIMER2_UFOF ((34 << 16) + 0) |
#define | DMAREQ_WTIMER3_CC0 ((35 << 16) + 1) |
#define | DMAREQ_WTIMER3_CC1 ((35 << 16) + 2) |
#define | DMAREQ_WTIMER3_CC2 ((35 << 16) + 3) |
#define | DMAREQ_WTIMER3_UFOF ((35 << 16) + 0) |
Macro Definition Documentation
#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) |
DMA channel select for ADC0_SCAN
Definition at line 53
of file efm32gg11b_dmareq.h
.
#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) |
DMA channel select for ADC0_SINGLE
Definition at line 52
of file efm32gg11b_dmareq.h
.
#define DMAREQ_ADC1_SCAN ((9 << 16) + 1) |
DMA channel select for ADC1_SCAN
Definition at line 55
of file efm32gg11b_dmareq.h
.
#define DMAREQ_ADC1_SINGLE ((9 << 16) + 0) |
DMA channel select for ADC1_SINGLE
Definition at line 54
of file efm32gg11b_dmareq.h
.
#define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) |
DMA channel select for CRYPTO0_DATA0RD
Definition at line 149
of file efm32gg11b_dmareq.h
.
#define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) |
DMA channel select for CRYPTO0_DATA0WR
Definition at line 147
of file efm32gg11b_dmareq.h
.
#define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) |
DMA channel select for CRYPTO0_DATA0XWR
Definition at line 148
of file efm32gg11b_dmareq.h
.
#define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) |
DMA channel select for CRYPTO0_DATA1RD
Definition at line 151
of file efm32gg11b_dmareq.h
.
#define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) |
DMA channel select for CRYPTO0_DATA1WR
Definition at line 150
of file efm32gg11b_dmareq.h
.
#define DMAREQ_CSEN_BSLN ((61 << 16) + 1) |
DMA channel select for CSEN_BSLN
Definition at line 159
of file efm32gg11b_dmareq.h
.
#define DMAREQ_CSEN_DATA ((61 << 16) + 0) |
DMA channel select for CSEN_DATA
Definition at line 158
of file efm32gg11b_dmareq.h
.
#define DMAREQ_EBI_DDEMPTY ((50 << 16) + 3) |
DMA channel select for EBI_DDEMPTY
Definition at line 155
of file efm32gg11b_dmareq.h
.
#define DMAREQ_EBI_HSYNC ((50 << 16) + 5) |
DMA channel select for EBI_HSYNC
Definition at line 157
of file efm32gg11b_dmareq.h
.
#define DMAREQ_EBI_PXL0EMPTY ((50 << 16) + 0) |
DMA channel select for EBI_PXL0EMPTY
Definition at line 152
of file efm32gg11b_dmareq.h
.
#define DMAREQ_EBI_PXL1EMPTY ((50 << 16) + 1) |
DMA channel select for EBI_PXL1EMPTY
Definition at line 153
of file efm32gg11b_dmareq.h
.
#define DMAREQ_EBI_PXLFULL ((50 << 16) + 2) |
DMA channel select for EBI_PXLFULL
Definition at line 154
of file efm32gg11b_dmareq.h
.
#define DMAREQ_EBI_VSYNC ((50 << 16) + 4) |
DMA channel select for EBI_VSYNC
Definition at line 156
of file efm32gg11b_dmareq.h
.
#define DMAREQ_I2C0_RXDATAV ((22 << 16) + 0) |
DMA channel select for I2C0_RXDATAV
Definition at line 94
of file efm32gg11b_dmareq.h
.
#define DMAREQ_I2C0_TXBL ((22 << 16) + 1) |
DMA channel select for I2C0_TXBL
Definition at line 95
of file efm32gg11b_dmareq.h
.
#define DMAREQ_I2C1_RXDATAV ((23 << 16) + 0) |
DMA channel select for I2C1_RXDATAV
Definition at line 96
of file efm32gg11b_dmareq.h
.
#define DMAREQ_I2C1_TXBL ((23 << 16) + 1) |
DMA channel select for I2C1_TXBL
Definition at line 97
of file efm32gg11b_dmareq.h
.
#define DMAREQ_I2C2_RXDATAV ((24 << 16) + 0) |
DMA channel select for I2C2_RXDATAV
Definition at line 98
of file efm32gg11b_dmareq.h
.
#define DMAREQ_I2C2_TXBL ((24 << 16) + 1) |
DMA channel select for I2C2_TXBL
Definition at line 99
of file efm32gg11b_dmareq.h
.
#define DMAREQ_LESENSE_BUFDATAV ((62 << 16) + 0) |
DMA channel select for LESENSE_BUFDATAV
Definition at line 160
of file efm32gg11b_dmareq.h
.
#define DMAREQ_LEUART0_RXDATAV ((20 << 16) + 0) |
DMA channel select for LEUART0_RXDATAV
Definition at line 88
of file efm32gg11b_dmareq.h
.
#define DMAREQ_LEUART0_TXBL ((20 << 16) + 1) |
DMA channel select for LEUART0_TXBL
Definition at line 89
of file efm32gg11b_dmareq.h
.
#define DMAREQ_LEUART0_TXEMPTY ((20 << 16) + 2) |
DMA channel select for LEUART0_TXEMPTY
Definition at line 90
of file efm32gg11b_dmareq.h
.
#define DMAREQ_LEUART1_RXDATAV ((21 << 16) + 0) |
DMA channel select for LEUART1_RXDATAV
Definition at line 91
of file efm32gg11b_dmareq.h
.
#define DMAREQ_LEUART1_TXBL ((21 << 16) + 1) |
DMA channel select for LEUART1_TXBL
Definition at line 92
of file efm32gg11b_dmareq.h
.
#define DMAREQ_LEUART1_TXEMPTY ((21 << 16) + 2) |
DMA channel select for LEUART1_TXEMPTY
Definition at line 93
of file efm32gg11b_dmareq.h
.
#define DMAREQ_MSC_WDATA ((48 << 16) + 0) |
DMA channel select for MSC_WDATA
Definition at line 146
of file efm32gg11b_dmareq.h
.
#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) |
DMA channel select for PRS_REQ0
Definition at line 50
of file efm32gg11b_dmareq.h
.
#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) |
DMA channel select for PRS_REQ1
Definition at line 51
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER0_CC0 ((25 << 16) + 1) |
DMA channel select for TIMER0_CC0
Definition at line 101
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER0_CC1 ((25 << 16) + 2) |
DMA channel select for TIMER0_CC1
Definition at line 102
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER0_CC2 ((25 << 16) + 3) |
DMA channel select for TIMER0_CC2
Definition at line 103
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER0_UFOF ((25 << 16) + 0) |
DMA channel select for TIMER0_UFOF
Definition at line 100
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER1_CC0 ((26 << 16) + 1) |
DMA channel select for TIMER1_CC0
Definition at line 105
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER1_CC1 ((26 << 16) + 2) |
DMA channel select for TIMER1_CC1
Definition at line 106
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER1_CC2 ((26 << 16) + 3) |
DMA channel select for TIMER1_CC2
Definition at line 107
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER1_CC3 ((26 << 16) + 4) |
DMA channel select for TIMER1_CC3
Definition at line 108
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER1_UFOF ((26 << 16) + 0) |
DMA channel select for TIMER1_UFOF
Definition at line 104
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER2_CC0 ((27 << 16) + 1) |
DMA channel select for TIMER2_CC0
Definition at line 110
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER2_CC1 ((27 << 16) + 2) |
DMA channel select for TIMER2_CC1
Definition at line 111
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER2_CC2 ((27 << 16) + 3) |
DMA channel select for TIMER2_CC2
Definition at line 112
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER2_UFOF ((27 << 16) + 0) |
DMA channel select for TIMER2_UFOF
Definition at line 109
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER3_CC0 ((28 << 16) + 1) |
DMA channel select for TIMER3_CC0
Definition at line 114
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER3_CC1 ((28 << 16) + 2) |
DMA channel select for TIMER3_CC1
Definition at line 115
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER3_CC2 ((28 << 16) + 3) |
DMA channel select for TIMER3_CC2
Definition at line 116
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER3_UFOF ((28 << 16) + 0) |
DMA channel select for TIMER3_UFOF
Definition at line 113
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER4_CC0 ((29 << 16) + 1) |
DMA channel select for TIMER4_CC0
Definition at line 118
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER4_CC1 ((29 << 16) + 2) |
DMA channel select for TIMER4_CC1
Definition at line 119
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER4_CC2 ((29 << 16) + 3) |
DMA channel select for TIMER4_CC2
Definition at line 120
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER4_UFOF ((29 << 16) + 0) |
DMA channel select for TIMER4_UFOF
Definition at line 117
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER5_CC0 ((30 << 16) + 1) |
DMA channel select for TIMER5_CC0
Definition at line 122
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER5_CC1 ((30 << 16) + 2) |
DMA channel select for TIMER5_CC1
Definition at line 123
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER5_CC2 ((30 << 16) + 3) |
DMA channel select for TIMER5_CC2
Definition at line 124
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER5_UFOF ((30 << 16) + 0) |
DMA channel select for TIMER5_UFOF
Definition at line 121
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER6_CC0 ((31 << 16) + 1) |
DMA channel select for TIMER6_CC0
Definition at line 126
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER6_CC1 ((31 << 16) + 2) |
DMA channel select for TIMER6_CC1
Definition at line 127
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER6_CC2 ((31 << 16) + 3) |
DMA channel select for TIMER6_CC2
Definition at line 128
of file efm32gg11b_dmareq.h
.
#define DMAREQ_TIMER6_UFOF ((31 << 16) + 0) |
DMA channel select for TIMER6_UFOF
Definition at line 125
of file efm32gg11b_dmareq.h
.
#define DMAREQ_UART0_RXDATAV ((18 << 16) + 0) |
DMA channel select for UART0_RXDATAV
Definition at line 82
of file efm32gg11b_dmareq.h
.
#define DMAREQ_UART0_TXBL ((18 << 16) + 1) |
DMA channel select for UART0_TXBL
Definition at line 83
of file efm32gg11b_dmareq.h
.
#define DMAREQ_UART0_TXEMPTY ((18 << 16) + 2) |
DMA channel select for UART0_TXEMPTY
Definition at line 84
of file efm32gg11b_dmareq.h
.
#define DMAREQ_UART1_RXDATAV ((19 << 16) + 0) |
DMA channel select for UART1_RXDATAV
Definition at line 85
of file efm32gg11b_dmareq.h
.
#define DMAREQ_UART1_TXBL ((19 << 16) + 1) |
DMA channel select for UART1_TXBL
Definition at line 86
of file efm32gg11b_dmareq.h
.
#define DMAREQ_UART1_TXEMPTY ((19 << 16) + 2) |
DMA channel select for UART1_TXEMPTY
Definition at line 87
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) |
DMA channel select for USART0_RXDATAV
Definition at line 58
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART0_TXBL ((12 << 16) + 1) |
DMA channel select for USART0_TXBL
Definition at line 59
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) |
DMA channel select for USART0_TXEMPTY
Definition at line 60
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) |
DMA channel select for USART1_RXDATAV
Definition at line 61
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) |
DMA channel select for USART1_RXDATAVRIGHT
Definition at line 64
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART1_TXBL ((13 << 16) + 1) |
DMA channel select for USART1_TXBL
Definition at line 62
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) |
DMA channel select for USART1_TXBLRIGHT
Definition at line 65
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) |
DMA channel select for USART1_TXEMPTY
Definition at line 63
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) |
DMA channel select for USART2_RXDATAV
Definition at line 66
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART2_TXBL ((14 << 16) + 1) |
DMA channel select for USART2_TXBL
Definition at line 67
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) |
DMA channel select for USART2_TXEMPTY
Definition at line 68
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART3_RXDATAV ((15 << 16) + 0) |
DMA channel select for USART3_RXDATAV
Definition at line 69
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) |
DMA channel select for USART3_RXDATAVRIGHT
Definition at line 72
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART3_TXBL ((15 << 16) + 1) |
DMA channel select for USART3_TXBL
Definition at line 70
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) |
DMA channel select for USART3_TXBLRIGHT
Definition at line 73
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) |
DMA channel select for USART3_TXEMPTY
Definition at line 71
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART4_RXDATAV ((16 << 16) + 0) |
DMA channel select for USART4_RXDATAV
Definition at line 74
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART4_RXDATAVRIGHT ((16 << 16) + 3) |
DMA channel select for USART4_RXDATAVRIGHT
Definition at line 77
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART4_TXBL ((16 << 16) + 1) |
DMA channel select for USART4_TXBL
Definition at line 75
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART4_TXBLRIGHT ((16 << 16) + 4) |
DMA channel select for USART4_TXBLRIGHT
Definition at line 78
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART4_TXEMPTY ((16 << 16) + 2) |
DMA channel select for USART4_TXEMPTY
Definition at line 76
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART5_RXDATAV ((17 << 16) + 0) |
DMA channel select for USART5_RXDATAV
Definition at line 79
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART5_TXBL ((17 << 16) + 1) |
DMA channel select for USART5_TXBL
Definition at line 80
of file efm32gg11b_dmareq.h
.
#define DMAREQ_USART5_TXEMPTY ((17 << 16) + 2) |
DMA channel select for USART5_TXEMPTY
Definition at line 81
of file efm32gg11b_dmareq.h
.
#define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) |
DMA channel select for VDAC0_CH0
Definition at line 56
of file efm32gg11b_dmareq.h
.
#define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) |
DMA channel select for VDAC0_CH1
Definition at line 57
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER0_CC0 ((32 << 16) + 1) |
DMA channel select for WTIMER0_CC0
Definition at line 130
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER0_CC1 ((32 << 16) + 2) |
DMA channel select for WTIMER0_CC1
Definition at line 131
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER0_CC2 ((32 << 16) + 3) |
DMA channel select for WTIMER0_CC2
Definition at line 132
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER0_UFOF ((32 << 16) + 0) |
DMA channel select for WTIMER0_UFOF
Definition at line 129
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER1_CC0 ((33 << 16) + 1) |
DMA channel select for WTIMER1_CC0
Definition at line 134
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER1_CC1 ((33 << 16) + 2) |
DMA channel select for WTIMER1_CC1
Definition at line 135
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER1_CC2 ((33 << 16) + 3) |
DMA channel select for WTIMER1_CC2
Definition at line 136
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER1_CC3 ((33 << 16) + 4) |
DMA channel select for WTIMER1_CC3
Definition at line 137
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER1_UFOF ((33 << 16) + 0) |
DMA channel select for WTIMER1_UFOF
Definition at line 133
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER2_CC0 ((34 << 16) + 1) |
DMA channel select for WTIMER2_CC0
Definition at line 139
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER2_CC1 ((34 << 16) + 2) |
DMA channel select for WTIMER2_CC1
Definition at line 140
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER2_CC2 ((34 << 16) + 3) |
DMA channel select for WTIMER2_CC2
Definition at line 141
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER2_UFOF ((34 << 16) + 0) |
DMA channel select for WTIMER2_UFOF
Definition at line 138
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER3_CC0 ((35 << 16) + 1) |
DMA channel select for WTIMER3_CC0
Definition at line 143
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER3_CC1 ((35 << 16) + 2) |
DMA channel select for WTIMER3_CC1
Definition at line 144
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER3_CC2 ((35 << 16) + 3) |
DMA channel select for WTIMER3_CC2
Definition at line 145
of file efm32gg11b_dmareq.h
.
#define DMAREQ_WTIMER3_UFOF ((35 << 16) + 0) |
DMA channel select for WTIMER3_UFOF
Definition at line 142
of file efm32gg11b_dmareq.h
.