LDMA - Linked DMA

Description

Linked Direct Memory Access (LDMA) Peripheral API.

LDMA API functions provide full support for the LDMA peripheral.

LDMA supports these DMA transfer types:

  • Memory to memory.
  • Memory to peripheral.
  • Peripheral to memory.
  • Peripheral to peripheral.
  • Constant value to memory.

LDMA supports linked lists of DMA descriptors allowing:

  • Circular and ping-pong buffer transfers.
  • Scatter-gather transfers.
  • Looped transfers.

LDMA has some advanced features:

  • Intra-channel synchronization (SYNC), allowing hardware events to pause and restart a DMA sequence.
  • Immediate-write (WRI), allowing DMA to write a constant anywhere in the memory map.
  • Complex flow control allowing if-else constructs.

Basic understanding of LDMA controller is assumed. Please refer to the reference manual for further details. The LDMA examples described in the reference manual are particularly helpful in understanding LDMA operations.

In order to use the DMA controller, the initialization function LDMA_Init() must have been executed once (normally during system initialization).

DMA transfers are initiated by a call to LDMA_StartTransfer() , transfer properties are controlled by the contents of LDMA_TransferCfg_t and LDMA_Descriptor_t structure parameters. The LDMA_Descriptor_t structure parameter may be a pointer to an array of descriptors, descriptors in array should be linked together as needed.

Transfer and descriptor initialization macros are provided for the most common transfer types. Due to the flexibility of LDMA peripheral, only a small subset of all possible initializer macros are provided, users should create new ones when needed.

Examples of LDMA usage:

A simple memory to memory transfer:

/* A single transfer of 4 half words. */
static const LDMA_TransferCfg_t transferCfg = LDMA_TRANSFER_CFG_MEMORY ();
static const LDMA_Descriptor_t desc = LDMA_DESCRIPTOR_SINGLE_M2M_HALF (src, dst, 4);
void ldmaTransfer( void )
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT ;
LDMA_Init (&init);
/* Start the memory transfer */
LDMA_StartTransfer (0, &transferCfg, &desc);
}


A linked list of three memory to memory transfers:

/* A transfer consisting of 3 descriptors linked together and each descriptor
* transfers 4 words from the source to the destination. */
static const LDMA_TransferCfg_t transferCfg1 = LDMA_TRANSFER_CFG_MEMORY ();
static const LDMA_Descriptor_t descList[] =
{
LDMA_DESCRIPTOR_LINKREL_M2M_WORD (src, dst, 4, 1),
LDMA_DESCRIPTOR_LINKREL_M2M_WORD (src + 4, dst + 4, 4, 1),
LDMA_DESCRIPTOR_SINGLE_M2M_WORD (src + 8, dst + 8, 4)
};
void ldmaLinkedTransfer( void )
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT ;
LDMA_Init (&init);
/* Start the linked memory transfer */
LDMA_StartTransfer (0, &transferCfg1, &descList[0]);
}


DMA from serial port peripheral to memory:

#if !defined(USART1) && defined(USART0)
/* The LDMA transfer should be triggered by the USART0 RX data available signal. */
static const LDMA_TransferCfg_t usart0RxTransfer =
LDMA_TRANSFER_CFG_PERIPHERAL ( ldmaPeripheralSignal_USART0_RXDATAV );
/* Transfer 4 bytes from the USART0 RX FIFO to memory. */
static const LDMA_Descriptor_t usart0RxDesc =
LDMA_DESCRIPTOR_SINGLE_P2M_BYTE (&USART0->RXDATA, // Peripheral address
dst, // Destination (SRAM)
4); // Number of byte transfers
void ldmaPeripheralTransfer( void )
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT ;
LDMA_Init (&init);
/* Start the peripheral transfer which is triggered by the USART0
* peripheral RXDATAV signal. */
LDMA_StartTransfer (0, &usart0RxTransfer, &usart0RxDesc);
}
#elif defined(USART1)
/* The LDMA transfer should be triggered by the USART1 RX data available signal. */
static const LDMA_TransferCfg_t usart1RxTransfer =
LDMA_TRANSFER_CFG_PERIPHERAL ( ldmaPeripheralSignal_USART1_RXDATAV );
/* Transfer 4 bytes from the USART1 RX FIFO to memory. */
static const LDMA_Descriptor_t usart1RxDesc =
LDMA_DESCRIPTOR_SINGLE_P2M_BYTE (&USART1->RXDATA, // Peripheral address
dst, // Destination (SRAM)
4); // Number of byte transfers
void ldmaPeripheralTransfer( void )
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT ;
LDMA_Init (&init);
/* Start the peripheral transfer which is triggered by the USART1
* peripheral RXDATAV signal. */
LDMA_StartTransfer (0, &usart1RxTransfer, &usart1RxDesc);
}
#elif defined(EUSART0)
/* The LDMA transfer should be triggered by the EUSART0 RX data available signal. */
static const LDMA_TransferCfg_t eusart0RxTransfer =
LDMA_TRANSFER_CFG_PERIPHERAL (ldmaPeripheralSignal_EUSART0_RXFL);
/* Transfer 4 bytes from the EUSART0 RX FIFO to memory. */
static const LDMA_Descriptor_t eusart0RxDesc =
LDMA_DESCRIPTOR_SINGLE_P2M_BYTE (&EUSART0->RXDATA, // Peripheral address
dst, // Destination (SRAM)
4); // Number of byte transfers
void ldmaPeripheralTransfer( void )
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT ;
LDMA_Init (&init);
/* Start the peripheral transfer which is triggered by the EUSART0
* peripheral RXFL signal. */
LDMA_StartTransfer (0, &eusart0RxTransfer, &eusart0RxDesc);
}
#endif


Ping-pong DMA from serial port peripheral to memory:

#if !defined(USART1) && defined(USART0)
/* Two buffers used in the ping-pong transfer from USART0. */
static volatile uint8_t buffer0[5];
static volatile uint8_t buffer1[5];
/* The LDMA transfer should be triggered by the USART0 RX data available signal. */
static const LDMA_TransferCfg_t usart0Transfer =
LDMA_TRANSFER_CFG_PERIPHERAL ( ldmaPeripheralSignal_USART0_RXDATAV );
/* Both descriptors transfer 5 bytes from the USART0 rx data register into
* one of the buffers. Note that the first descriptor uses a relative address
* of 1 to link to the next descriptor, while the last descriptor uses a
* relative address of -1 to link to the first descriptor. */
static const LDMA_Descriptor_t rxLoop[] =
{
LDMA_DESCRIPTOR_LINKREL_P2M_BYTE (&USART0->RXDATA, buffer0, 5, 1),
LDMA_DESCRIPTOR_LINKREL_P2M_BYTE (&USART0->RXDATA, buffer1, 5, -1)
};
void ldmaPingPongTransfer( void )
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT ;
LDMA_Init (&init);
/* Start the peripheral transfer which is triggered by the USART0
* peripheral RXDATAV signal. */
LDMA_StartTransfer (0, &usart0Transfer, &rxLoop[0]);
}
#elif defined(USART1)
/* Two buffers used in the ping-pong transfer from USART1. */
static volatile uint8_t buffer0[5];
static volatile uint8_t buffer1[5];
/* The LDMA transfer should be triggered by the USART1 RX data available signal. */
static const LDMA_TransferCfg_t usart1Transfer =
LDMA_TRANSFER_CFG_PERIPHERAL ( ldmaPeripheralSignal_USART1_RXDATAV );
/* Both descriptors transfer 5 bytes from the USART1 rx data register into
* one of the buffers. Note that the first descriptor uses a relative address
* of 1 to link to the next descriptor, while the last descriptor uses a
* relative address of -1 to link to the first descriptor. */
static const LDMA_Descriptor_t rxLoop[] =
{
LDMA_DESCRIPTOR_LINKREL_P2M_BYTE (&USART1->RXDATA, buffer0, 5, 1),
LDMA_DESCRIPTOR_LINKREL_P2M_BYTE (&USART1->RXDATA, buffer1, 5, -1)
};
void ldmaPingPongTransfer( void )
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT ;
LDMA_Init (&init);
/* Start the peripheral transfer which is triggered by the USART1
* peripheral RXDATAV signal. */
LDMA_StartTransfer (0, &usart1Transfer, &rxLoop[0]);
}
#elif defined(EUSART0)
/* Two buffers used in the ping-pong transfer from EUSART0. */
static volatile uint8_t buffer0[5];
static volatile uint8_t buffer1[5];
/* The LDMA transfer should be triggered by the EUSART0 RX data available signal. */
static const LDMA_TransferCfg_t eusart0Transfer =
LDMA_TRANSFER_CFG_PERIPHERAL (ldmaPeripheralSignal_EUSART0_RXFL);
/* Both descriptors transfer 5 bytes from the EUSART0 rx data register into
* one of the buffers. Note that the first descriptor uses a relative address
* of 1 to link to the next descriptor, while the last descriptor uses a
* relative address of -1 to link to the first descriptor. */
static const LDMA_Descriptor_t rxLoop[] =
{
LDMA_DESCRIPTOR_LINKREL_P2M_BYTE (&EUSART0->RXDATA, buffer0, 5, 1),
LDMA_DESCRIPTOR_LINKREL_P2M_BYTE (&EUSART0->RXDATA, buffer1, 5, -1)
};
void ldmaPingPongTransfer( void )
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT ;
LDMA_Init (&init);
/* Start the peripheral transfer which is triggered by the EUSART0
* peripheral RXFL signal. */
LDMA_StartTransfer (0, &eusart0Transfer, &rxLoop[0]);
}
#endif
Note
LDMA module does not implement LDMA interrupt handler. A template for an LDMA IRQ handler is included here as an example.
/* Template for an LDMA IRQ handler. */
void LDMA_IRQHandler( void )
{
uint32_t ch;
/* Get all pending and enabled interrupts. */
uint32_t pending = LDMA_IntGetEnabled ();
/* Loop here on an LDMA error to enable debugging. */
while (pending & LDMA_IF_ERROR) {
}
/* Iterate over all LDMA channels. */
for (ch = 0; ch < DMA_CHAN_COUNT; ch++) {
uint32_t mask = 0x1 << ch;
if (pending & mask) {
/* Clear interrupt flag. */
#if defined (LDMA_HAS_SET_CLEAR)
LDMA->IF_CLR = mask;
#else
LDMA->IFC = mask;
#endif
/* Do more stuff here, execute callbacks etc. */
}
}
}

Data Structures

union LDMA_Descriptor_t
DMA descriptor.
struct LDMA_Init_t
LDMA initialization configuration structure.
struct LDMA_TransferCfg_t
DMA transfer configuration structure.

Functions

void LDMA_DeInit (void)
De-initialize the LDMA controller.
void LDMA_EnableChannelRequest (int ch, bool enable)
Enable or disable an LDMA channel request.
void LDMA_Init (const LDMA_Init_t *init)
Initialize the LDMA controller.
void LDMA_StartTransfer (int ch, const LDMA_TransferCfg_t *transfer, const LDMA_Descriptor_t *descriptor)
Start a DMA transfer.
void LDMA_StopTransfer (int ch)
Stop a DMA transfer.
bool LDMA_TransferDone (int ch)
Check if a DMA transfer has completed.
uint32_t LDMA_TransferRemainingCount (int ch)
Get the number of items remaining in a transfer.
bool LDMA_ChannelEnabled (int ch)
Check if a certain channel is enabled.
void LDMA_IntClear (uint32_t flags)
Clear one or more pending LDMA interrupts.
void LDMA_IntDisable (uint32_t flags)
Disable one or more LDMA interrupts.
void LDMA_IntEnable (uint32_t flags)
Enable one or more LDMA interrupts.
uint32_t LDMA_IntGet (void)
Get pending LDMA interrupt flags.
uint32_t LDMA_IntGetEnabled (void)
Get enabled and pending LDMA interrupt flags.
void LDMA_IntSet (uint32_t flags)
Set one or more pending LDMA interrupts.

Macros

#define LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD 4
Size in words of a non-extended DMA descriptor.
#define LDMA_DESCRIPTOR_EXTEND_SIZE_WORD 7
Size in words of an extended DMA descriptor.
#define LDMA_INIT_DEFAULT
Default DMA initialization structure.
#define LDMA_TRANSFER_CFG_MEMORY ()
Generic DMA transfer configuration for memory to memory transfers.
#define LDMA_TRANSFER_CFG_MEMORY_LOOP (loopCnt)
Generic DMA transfer configuration for looped memory to memory transfers.
#define LDMA_TRANSFER_CFG_PERIPHERAL (signal)
Generic DMA transfer configuration for memory to/from peripheral transfers.
#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP (signal, loopCnt)
Generic DMA transfer configuration for looped memory to/from peripheral transfers.
#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD (src, dest, count)
DMA descriptor initializer for single memory to memory word transfer.
#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF (src, dest, count)
DMA descriptor initializer for single memory to memory half-word transfer.
#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE (src, dest, count)
DMA descriptor initializer for single memory to memory byte transfer.
#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD (src, dest, count)
DMA descriptor initializer for linked memory to memory word transfer.
#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF (src, dest, count)
DMA descriptor initializer for linked memory to memory half-word transfer.
#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE (src, dest, count)
DMA descriptor initializer for linked memory to memory byte transfer.
#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD (src, dest, count, linkjmp)
DMA descriptor initializer for linked memory to memory word transfer.
#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF (src, dest, count, linkjmp)
DMA descriptor initializer for linked memory to memory half-word transfer.
#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE (src, dest, count, linkjmp)
DMA descriptor initializer for linked memory to memory byte transfer.
#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE (src, dest, count)
DMA descriptor initializer for byte transfers from a peripheral to memory.
#define LDMA_DESCRIPTOR_SINGLE_P2P_BYTE (src, dest, count)
DMA descriptor initializer for byte transfers from a peripheral to a peripheral.
#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE (src, dest, count)
DMA descriptor initializer for byte transfers from memory to a peripheral.
#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE (src, dest, count, linkjmp)
DMA descriptor initializer for byte transfers from a peripheral to memory.
#define LDMA_DESCRIPTOR_LINKREL_P2M_WORD (src, dest, count, linkjmp)
DMA descriptor initializer for word transfers from a peripheral to memory.
#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE (src, dest, count, linkjmp)
DMA descriptor initializer for byte transfers from memory to a peripheral.
#define LDMA_DESCRIPTOR_SINGLE_WRITE (value, address)
DMA descriptor initializer for Immediate WRITE transfer.
#define LDMA_DESCRIPTOR_LINKABS_WRITE (value, address)
DMA descriptor initializer for Immediate WRITE transfer.
#define LDMA_DESCRIPTOR_LINKREL_WRITE (value, address, linkjmp)
DMA descriptor initializer for Immediate WRITE transfer.
#define LDMA_DESCRIPTOR_SINGLE_SYNC (set, clr, matchValue, matchEnable)
DMA descriptor initializer for SYNC transfer.
#define LDMA_DESCRIPTOR_LINKABS_SYNC (set, clr, matchValue, matchEnable)
DMA descriptor initializer for SYNC transfer.
#define LDMA_DESCRIPTOR_LINKREL_SYNC (set, clr, matchValue, matchEnable, linkjmp)
DMA descriptor initializer for SYNC transfer.

Enumerations

enum LDMA_CtrlBlockSize_t {
ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1,
ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2,
ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3,
ldmaCtrlBlockSizeUnit4 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT4,
ldmaCtrlBlockSizeUnit6 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT6,
ldmaCtrlBlockSizeUnit8 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT8,
ldmaCtrlBlockSizeUnit16 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT16,
ldmaCtrlBlockSizeUnit32 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT32,
ldmaCtrlBlockSizeUnit64 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT64,
ldmaCtrlBlockSizeUnit128 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT128,
ldmaCtrlBlockSizeUnit256 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT256,
ldmaCtrlBlockSizeUnit512 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT512,
ldmaCtrlBlockSizeUnit1024 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024,
ldmaCtrlBlockSizeAll = _LDMA_CH_CTRL_BLOCKSIZE_ALL
}
Controls the number of unit data transfers per arbitration cycle, providing a means to balance DMA channels' load on the controller.
enum LDMA_CtrlStructType_t {
ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER,
ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE,
ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE
}
DMA structure type.
enum LDMA_CtrlReqMode_t {
ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK,
ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL
}
DMA transfer block or cycle selector.
enum LDMA_CtrlSrcInc_t {
ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE,
ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO,
ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR,
ldmaCtrlSrcIncNone = _LDMA_CH_CTRL_SRCINC_NONE
}
Source address increment unit size.
enum LDMA_CtrlSize_t {
ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE,
ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD,
ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD
}
DMA transfer unit size.
enum LDMA_CtrlDstInc_t {
ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE,
ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO,
ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR,
ldmaCtrlDstIncNone = _LDMA_CH_CTRL_DSTINC_NONE
}
Destination address increment unit size.
enum LDMA_CtrlSrcAddrMode_t {
ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE,
ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE
}
Source addressing mode.
enum LDMA_CtrlDstAddrMode_t {
ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE,
ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE
}
Destination addressing mode.
enum LDMA_LinkMode_t {
ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE,
ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE
}
DMA link load address mode.
enum LDMA_CfgArbSlots_t {
ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE,
ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO,
ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR,
ldmaCfgArbSlotsAs8 = _LDMA_CH_CFG_ARBSLOTS_EIGHT
}
Insert extra arbitration slots to increase channel arbitration priority.
enum LDMA_CfgSrcIncSign_t {
ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE,
ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE
}
Source address increment sign.
enum LDMA_CfgDstIncSign_t {
ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE,
ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE
}
Destination address increment sign.
enum LDMA_PeripheralSignal_t {
ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE,
ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0,
ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0,
ldmaPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1,
ldmaPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1,
ldmaPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
ldmaPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
ldmaPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
ldmaPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
ldmaPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
ldmaPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN,
ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN,
ldmaPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI,
ldmaPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI,
ldmaPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI,
ldmaPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI,
ldmaPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI,
ldmaPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI,
ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0,
ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0,
ldmaPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1,
ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1,
ldmaPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2,
ldmaPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2,
ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE,
ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0,
ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0,
ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0,
ldmaPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1,
ldmaPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1,
ldmaPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1,
ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC,
ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS,
ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS,
ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
ldmaPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2,
ldmaPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2,
ldmaPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2,
ldmaPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2,
ldmaPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3,
ldmaPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3,
ldmaPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3,
ldmaPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3,
ldmaPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4,
ldmaPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4,
ldmaPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4,
ldmaPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4,
ldmaPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5,
ldmaPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5,
ldmaPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5,
ldmaPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5,
ldmaPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6,
ldmaPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6,
ldmaPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6,
ldmaPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6,
ldmaPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0,
ldmaPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0,
ldmaPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0,
ldmaPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1,
ldmaPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1,
ldmaPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1,
ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0,
ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0,
ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0,
ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1,
ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1,
ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1,
ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1,
ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1,
ldmaPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2,
ldmaPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2,
ldmaPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2,
ldmaPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3,
ldmaPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3,
ldmaPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3,
ldmaPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3,
ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3,
ldmaPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4,
ldmaPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4,
ldmaPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4,
ldmaPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4,
ldmaPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4,
ldmaPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5,
ldmaPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5,
ldmaPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5,
ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0,
ldmaPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0,
ldmaPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0,
ldmaPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0,
ldmaPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0,
ldmaPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0,
ldmaPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1,
ldmaPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1,
ldmaPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1,
ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1,
ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1,
ldmaPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2,
ldmaPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2,
ldmaPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2,
ldmaPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2,
ldmaPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3,
ldmaPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3,
ldmaPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3,
ldmaPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3
}
Peripherals that can trigger LDMA transfers.

Function Documentation

◆ LDMA_DeInit()

void LDMA_DeInit ( void )

De-initialize the LDMA controller.

LDMA interrupts are disabled and the LDMA clock is stopped.

◆ LDMA_EnableChannelRequest()

void LDMA_EnableChannelRequest ( int ch,
bool enable
)

Enable or disable an LDMA channel request.

Use this function to enable or disable an LDMA channel request. This will prevent the LDMA from proceeding after its current transaction if disabled.

Parameters
[in] ch LDMA channel to enable or disable requests.
[in] enable If 'true', the request will be enabled. If 'false', the request will be disabled.

◆ LDMA_Init()

void LDMA_Init ( const LDMA_Init_t * init )

Initialize the LDMA controller.

This function will disable all the LDMA channels and enable the LDMA bus clock in the CMU. This function will also enable the LDMA IRQ in the NVIC and set the LDMA IRQ priority to a user-configurable priority. The LDMA interrupt priority is configured using the LDMA_Init_t structure.

Note
Since this function enables the LDMA IRQ, always add a custom LDMA_IRQHandler to the application to handle any interrupts from LDMA.
Parameters
[in] init A pointer to the initialization structure used to configure the LDMA.

◆ LDMA_StartTransfer()

void LDMA_StartTransfer ( int ch,
const LDMA_TransferCfg_t * transfer,
const LDMA_Descriptor_t * descriptor
)

Start a DMA transfer.

Parameters
[in] ch A DMA channel.
[in] transfer The initialization structure used to configure the transfer.
[in] descriptor The transfer descriptor, which can be an array of descriptors linked together. Each descriptor's fields stored in RAM will be loaded into the certain hardware registers at the proper time to perform the DMA transfer.

◆ LDMA_StopTransfer()

void LDMA_StopTransfer ( int ch )

Stop a DMA transfer.

Note
The DMA will complete the current AHB burst transfer before stopping.
Parameters
[in] ch A DMA channel to stop.

◆ LDMA_TransferDone()

bool LDMA_TransferDone ( int ch )

Check if a DMA transfer has completed.

Parameters
[in] ch A DMA channel to check.
Returns
True if transfer has completed, false if not.

◆ LDMA_TransferRemainingCount()

uint32_t LDMA_TransferRemainingCount ( int ch )

Get the number of items remaining in a transfer.

Note
This function does not take into account that a DMA transfer with a chain of linked transfers might be ongoing. It will only check the count for the current transfer.
Parameters
[in] ch The channel number of the transfer to check.
Returns
A number of items remaining in the transfer.

◆ LDMA_ChannelEnabled()

bool LDMA_ChannelEnabled ( int ch )
inline

Check if a certain channel is enabled.

Parameters
[in] ch LDMA channel to check.
Returns
return true if the LDMA channel is enabled and false if the channel is not enabled.

◆ LDMA_IntClear()

void LDMA_IntClear ( uint32_t flags )
inline

Clear one or more pending LDMA interrupts.

Parameters
[in] flags Pending LDMA interrupt sources to clear. Use one or more valid interrupt flags for the LDMA module. The flags are LDMA_IFC_ERROR and one done flag for each channel.

◆ LDMA_IntDisable()

void LDMA_IntDisable ( uint32_t flags )
inline

Disable one or more LDMA interrupts.

Parameters
[in] flags LDMA interrupt sources to disable. Use one or more valid interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR and one done flag for each channel.

◆ LDMA_IntEnable()

void LDMA_IntEnable ( uint32_t flags )
inline

Enable one or more LDMA interrupts.

Note
Depending on the use, a pending interrupt may already be set prior to enabling the interrupt. To ignore a pending interrupt, consider using LDMA_IntClear() prior to enabling the interrupt.
Parameters
[in] flags LDMA interrupt sources to enable. Use one or more valid interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR and one done flag for each channel.

◆ LDMA_IntGet()

uint32_t LDMA_IntGet ( void )
inline

Get pending LDMA interrupt flags.

Note
Event bits are not cleared by the use of this function.
Returns
LDMA interrupt sources pending. Returns one or more valid interrupt flags for LDMA module. The flags are LDMA_IF_ERROR and one flag for each LDMA channel.

◆ LDMA_IntGetEnabled()

uint32_t LDMA_IntGetEnabled ( void )
inline

Get enabled and pending LDMA interrupt flags.

Useful for handling more interrupt sources in the same interrupt handler.

Note
Interrupt flags are not cleared by the use of this function.
Returns
Pending and enabled LDMA interrupt sources Return value is the bitwise AND of
  • the enabled interrupt sources in LDMA_IEN and
  • the pending interrupt flags LDMA_IF

◆ LDMA_IntSet()

void LDMA_IntSet ( uint32_t flags )
inline

Set one or more pending LDMA interrupts.

Parameters
[in] flags LDMA interrupt sources to set to pending. Use one or more valid interrupt flags for LDMA module. The flags are LDMA_IFS_ERROR and one done flag for each LDMA channel.

Macro Definition Documentation

◆ LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD

#define LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD   4

Size in words of a non-extended DMA descriptor.

◆ LDMA_DESCRIPTOR_EXTEND_SIZE_WORD

#define LDMA_DESCRIPTOR_EXTEND_SIZE_WORD   7

Size in words of an extended DMA descriptor.

◆ LDMA_INIT_DEFAULT

#define LDMA_INIT_DEFAULT
Value:
{ \
.ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT, /* Fixed priority arbitration.*/ \
.ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \
.ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \
.ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \
}

Default DMA initialization structure.

◆ LDMA_TRANSFER_CFG_MEMORY

#define LDMA_TRANSFER_CFG_MEMORY ( )
Value:
{ \
0, 0, 0, 0, 0, \
false, false , ldmaCfgArbSlotsAs1 , \
ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos , 0 \
}

Generic DMA transfer configuration for memory to memory transfers.

◆ LDMA_TRANSFER_CFG_MEMORY_LOOP

#define LDMA_TRANSFER_CFG_MEMORY_LOOP ( loopCnt )
Value:
{ \
0, 0, 0, 0, 0, \
false, false , ldmaCfgArbSlotsAs1 , \
ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos , \
loopCnt \
}

Generic DMA transfer configuration for looped memory to memory transfers.

◆ LDMA_TRANSFER_CFG_PERIPHERAL

#define LDMA_TRANSFER_CFG_PERIPHERAL ( signal )
Value:
{ \
signal, 0, 0, 0, 0, \
false, false , ldmaCfgArbSlotsAs1 , \
ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos , 0 \
}

Generic DMA transfer configuration for memory to/from peripheral transfers.

◆ LDMA_TRANSFER_CFG_PERIPHERAL_LOOP

#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP ( signal,
loopCnt
)
Value:
{ \
signal, 0, 0, 0, 0, \
false, false , ldmaCfgArbSlotsAs1 , \
ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos , loopCnt \
}

Generic DMA transfer configuration for looped memory to/from peripheral transfers.

◆ LDMA_DESCRIPTOR_SINGLE_M2M_WORD

#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD ( src,
dest,
count
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 1, \
.reqMode = ldmaCtrlReqModeAll , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne , \
.size = ldmaCtrlSizeWord , \
.dstInc = ldmaCtrlDstIncOne , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = 0, \
.link = 0, \
.linkAddr = 0 \
} \
}

DMA descriptor initializer for single memory to memory word transfer.

Parameters
[in] src Source data address.
[in] dest Destination data address.
[in] count Number of words to transfer.

◆ LDMA_DESCRIPTOR_SINGLE_M2M_HALF

#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF ( src,
dest,
count
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 1, \
.reqMode = ldmaCtrlReqModeAll , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne , \
.size = ldmaCtrlSizeHalf , \
.dstInc = ldmaCtrlDstIncOne , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = 0, \
.link = 0, \
.linkAddr = 0 \
} \
}

DMA descriptor initializer for single memory to memory half-word transfer.

Parameters
[in] src Source data address.
[in] dest Destination data address.
[in] count Number of half-words to transfer.

◆ LDMA_DESCRIPTOR_SINGLE_M2M_BYTE

#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE ( src,
dest,
count
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 1, \
.reqMode = ldmaCtrlReqModeAll , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne , \
.size = ldmaCtrlSizeByte , \
.dstInc = ldmaCtrlDstIncOne , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = 0, \
.link = 0, \
.linkAddr = 0 \
} \
}

DMA descriptor initializer for single memory to memory byte transfer.

Parameters
[in] src Source data address.
[in] dest Destination data address.
[in] count Number of bytes to transfer.

◆ LDMA_DESCRIPTOR_LINKABS_M2M_WORD

#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD ( src,
dest,
count
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 0, \
.reqMode = ldmaCtrlReqModeAll , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne , \
.size = ldmaCtrlSizeWord , \
.dstInc = ldmaCtrlDstIncOne , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = ldmaLinkModeAbs , \
.link = 1, \
.linkAddr = 0 /* Must be set runtime ! */ \
} \
}

DMA descriptor initializer for linked memory to memory word transfer.

Link address must be an absolute address.

Note
The linkAddr member of the transfer descriptor is not initialized. linkAddr must be initialized by using the proper bits right-shift to get the correct bits from the absolute address. _LDMA_CH_LINK_LINKADDR_SHIFT should be used for that operation:
desc.linkAddr = ((int32_t)&next_desc) >> _LDMA_CH_LINK_LINKADDR_SHIFT;
The opposite bit shift (left) must be done if linkAddr is read.
Parameters
[in] src Source data address.
[in] dest Destination data address.
[in] count Number of words to transfer.

◆ LDMA_DESCRIPTOR_LINKABS_M2M_HALF

#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF ( src,
dest,
count
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 0, \
.reqMode = ldmaCtrlReqModeAll , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne , \
.size = ldmaCtrlSizeHalf , \
.dstInc = ldmaCtrlDstIncOne , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = ldmaLinkModeAbs , \
.link = 1, \
.linkAddr = 0 /* Must be set runtime ! */ \
} \
}

DMA descriptor initializer for linked memory to memory half-word transfer.

Link address must be an absolute address.

Note
The linkAddr member of the transfer descriptor is not initialized. linkAddr must be initialized by using the proper bits right-shift to get the correct bits from the absolute address. _LDMA_CH_LINK_LINKADDR_SHIFT should be used for that operation:
desc.linkAddr = ((int32_t)&next_desc) >> _LDMA_CH_LINK_LINKADDR_SHIFT;
The opposite bit shift (left) must be done if linkAddr is read.
Parameters
[in] src Source data address.
[in] dest Destination data address.
[in] count Number of half-words to transfer.

◆ LDMA_DESCRIPTOR_LINKABS_M2M_BYTE

#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE ( src,
dest,
count
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 0, \
.reqMode = ldmaCtrlReqModeAll , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne , \
.size = ldmaCtrlSizeByte , \
.dstInc = ldmaCtrlDstIncOne , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = ldmaLinkModeAbs , \
.link = 1, \
.linkAddr = 0 /* Must be set runtime ! */ \
} \
}

DMA descriptor initializer for linked memory to memory byte transfer.

Link address must be an absolute address.

Note
The linkAddr member of the transfer descriptor is not initialized. linkAddr must be initialized by using the proper bits right-shift to get the correct bits from the absolute address. _LDMA_CH_LINK_LINKADDR_SHIFT should be used for that operation:
desc.linkAddr = ((int32_t)&next_desc) >> _LDMA_CH_LINK_LINKADDR_SHIFT;
The opposite bit shift (left) must be done if linkAddr is read.
Parameters
[in] src Source data address.
[in] dest Destination data address.
[in] count Number of bytes to transfer.

◆ LDMA_DESCRIPTOR_LINKREL_M2M_WORD

#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD ( src,
dest,
count,
linkjmp
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 0, \
.reqMode = ldmaCtrlReqModeAll , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne , \
.size = ldmaCtrlSizeWord , \
.dstInc = ldmaCtrlDstIncOne , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = ldmaLinkModeRel , \
.link = 1, \
.linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
} \
}

DMA descriptor initializer for linked memory to memory word transfer.

Link address is a relative address.

Note
The linkAddr member of the transfer descriptor is initialized to 4 (regular descriptor) or 7 (extended descriptor), assuming that the next descriptor immediately follows this descriptor (in memory).
Parameters
[in] src Source data address.
[in] dest Destination data address.
[in] count Number of words to transfer.
[in] linkjmp Address of descriptor to link to, expressed as a signed number of descriptors from "here". 1=one descriptor forward in memory, 0=this descriptor, -1=one descriptor back in memory.

◆ LDMA_DESCRIPTOR_LINKREL_M2M_HALF

#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF ( src,
dest,
count,
linkjmp
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 0, \
.reqMode = ldmaCtrlReqModeAll , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne , \
.size = ldmaCtrlSizeHalf , \
.dstInc = ldmaCtrlDstIncOne , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = ldmaLinkModeRel , \
.link = 1, \
.linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
} \
}

DMA descriptor initializer for linked memory to memory half-word transfer.

Link address is a relative address.

Note
The linkAddr member of the transfer descriptor is initialized to 4 (regular descriptor) or 7 (extended descriptor), assuming that the next descriptor immediately follows this descriptor (in memory).
Parameters
[in] src Source data address.
[in] dest Destination data address.
[in] count Number of half-words to transfer.
[in] linkjmp Address of descriptor to link to, expressed as a signed number of descriptors from "here". 1=one descriptor forward in memory, 0=this descriptor, -1=one descriptor back in memory.

◆ LDMA_DESCRIPTOR_LINKREL_M2M_BYTE

#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE ( src,
dest,
count,
linkjmp
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 0, \
.reqMode = ldmaCtrlReqModeAll , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne , \
.size = ldmaCtrlSizeByte , \
.dstInc = ldmaCtrlDstIncOne , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = ldmaLinkModeRel , \
.link = 1, \
.linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
} \
}

DMA descriptor initializer for linked memory to memory byte transfer.

Link address is a relative address.

Note
The linkAddr member of the transfer descriptor is initialized to 4 (regular descriptor) or 7 (extended descriptor), assuming that the next descriptor immediately follows this descriptor (in memory).
Parameters
[in] src Source data address.
[in] dest Destination data address.
[in] count Number of bytes to transfer.
[in] linkjmp Address of descriptor to link to, expressed as a signed number of descriptors from "here". 1=one descriptor forward in memory, 0=this descriptor, -1=one descriptor back in memory.

◆ LDMA_DESCRIPTOR_SINGLE_P2M_BYTE

#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE ( src,
dest,
count
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 0, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 1, \
.reqMode = ldmaCtrlReqModeBlock , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncNone , \
.size = ldmaCtrlSizeByte , \
.dstInc = ldmaCtrlDstIncOne , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = 0, \
.link = 0, \
.linkAddr = 0 \
} \
}

DMA descriptor initializer for byte transfers from a peripheral to memory.

Parameters
[in] src Peripheral data source register address.
[in] dest Destination data address.
[in] count Number of bytes to transfer.

◆ LDMA_DESCRIPTOR_SINGLE_P2P_BYTE

#define LDMA_DESCRIPTOR_SINGLE_P2P_BYTE ( src,
dest,
count
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 0, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 1, \
.reqMode = ldmaCtrlReqModeBlock , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncNone , \
.size = ldmaCtrlSizeByte , \
.dstInc = ldmaCtrlDstIncNone , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = 0, \
.link = 0, \
.linkAddr = 0 \
} \
}

DMA descriptor initializer for byte transfers from a peripheral to a peripheral.

Parameters
[in] src Peripheral data source register address.
[in] dest Peripheral data destination register address.
[in] count Number of bytes to transfer.

◆ LDMA_DESCRIPTOR_SINGLE_M2P_BYTE

#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE ( src,
dest,
count
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 0, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 1, \
.reqMode = ldmaCtrlReqModeBlock , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne , \
.size = ldmaCtrlSizeByte , \
.dstInc = ldmaCtrlDstIncNone , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = 0, \
.link = 0, \
.linkAddr = 0 \
} \
}

DMA descriptor initializer for byte transfers from memory to a peripheral.

Parameters
[in] src Source data address.
[in] dest Peripheral data register destination address.
[in] count Number of bytes to transfer.

◆ LDMA_DESCRIPTOR_LINKREL_P2M_BYTE

#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE ( src,
dest,
count,
linkjmp
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 0, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 1, \
.reqMode = ldmaCtrlReqModeBlock , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncNone , \
.size = ldmaCtrlSizeByte , \
.dstInc = ldmaCtrlDstIncOne , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = ldmaLinkModeRel , \
.link = 1, \
.linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
} \
}

DMA descriptor initializer for byte transfers from a peripheral to memory.

Parameters
[in] src Peripheral data source register address.
[in] dest Destination data address.
[in] count Number of bytes to transfer.
[in] linkjmp Address of descriptor to link to, expressed as a signed number of descriptors from "here". 1=one descriptor forward in memory, 0=this descriptor, -1=one descriptor back in memory.

◆ LDMA_DESCRIPTOR_LINKREL_P2M_WORD

#define LDMA_DESCRIPTOR_LINKREL_P2M_WORD ( src,
dest,
count,
linkjmp
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 0, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 1, \
.reqMode = ldmaCtrlReqModeBlock , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncNone , \
.size = ldmaCtrlSizeWord , \
.dstInc = ldmaCtrlDstIncOne , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = ldmaLinkModeRel , \
.link = 1, \
.linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
} \
}

DMA descriptor initializer for word transfers from a peripheral to memory.

Parameters
[in] src Peripheral data source register address.
[in] dest Destination data address.
[in] count Number of words to transfer.
[in] linkjmp Address of descriptor to link to, expressed as a signed number of descriptors from "here". 1=one descriptor forward in memory, 0=this descriptor, -1=one descriptor back in memory.

◆ LDMA_DESCRIPTOR_LINKREL_M2P_BYTE

#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE ( src,
dest,
count,
linkjmp
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer , \
.structReq = 0, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1 , \
.doneIfs = 1, \
.reqMode = ldmaCtrlReqModeBlock , \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne , \
.size = ldmaCtrlSizeByte , \
.dstInc = ldmaCtrlDstIncNone , \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs , \
.dstAddrMode = ldmaCtrlDstAddrModeAbs , \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = ldmaLinkModeRel , \
.link = 1, \
.linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
} \
}

DMA descriptor initializer for byte transfers from memory to a peripheral.

Parameters
[in] src Source data address.
[in] dest Peripheral data register destination address.
[in] count Number of bytes to transfer.
[in] linkjmp Address of descriptor to link to, expressed as a signed number of descriptors from "here". 1=one descriptor forward in memory, 0=this descriptor, -1=one descriptor back in memory.

◆ LDMA_DESCRIPTOR_SINGLE_WRITE

#define LDMA_DESCRIPTOR_SINGLE_WRITE ( value,
address
)
Value:
{ \
.wri = \
{ \
.structType = ldmaCtrlStructTypeWrite , \
.structReq = 1, \
.xferCnt = 0, \
.byteSwap = 0, \
.blockSize = 0, \
.doneIfs = 1, \
.reqMode = 0, \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = 0, \
.size = 0, \
.dstInc = 0, \
.srcAddrMode = 0, \
.dstAddrMode = 0, \
.immVal = (value), \
.dstAddr = (uint32_t)(address), \
.linkMode = 0, \
.link = 0, \
.linkAddr = 0 \
} \
}

DMA descriptor initializer for Immediate WRITE transfer.

Parameters
[in] value Immediate value to write.
[in] address Write address.

◆ LDMA_DESCRIPTOR_LINKABS_WRITE

#define LDMA_DESCRIPTOR_LINKABS_WRITE ( value,
address
)
Value:
{ \
.wri = \
{ \
.structType = ldmaCtrlStructTypeWrite , \
.structReq = 1, \
.xferCnt = 0, \
.byteSwap = 0, \
.blockSize = 0, \
.doneIfs = 0, \
.reqMode = 0, \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = 0, \
.size = 0, \
.dstInc = 0, \
.srcAddrMode = 0, \
.dstAddrMode = 0, \
.immVal = (value), \
.dstAddr = (uint32_t)(address), \
.linkMode = ldmaLinkModeAbs , \
.link = 1, \
.linkAddr = 0 /* Must be set runtime ! */ \
} \
}

DMA descriptor initializer for Immediate WRITE transfer.

Link address must be an absolute address.

Note
The linkAddr member of the transfer descriptor is not initialized. linkAddr must be initialized by using the proper bits right-shift to get the correct bits from the absolute address. _LDMA_CH_LINK_LINKADDR_SHIFT should be used for that operation:
desc.linkAddr = ((int32_t)&next_desc) >> _LDMA_CH_LINK_LINKADDR_SHIFT;
The opposite bit shift (left) must be done if linkAddr is read.
Parameters
[in] value Immediate value to write.
[in] address Write address.

◆ LDMA_DESCRIPTOR_LINKREL_WRITE

#define LDMA_DESCRIPTOR_LINKREL_WRITE ( value,
address,
linkjmp
)
Value:
{ \
.wri = \
{ \
.structType = ldmaCtrlStructTypeWrite , \
.structReq = 1, \
.xferCnt = 0, \
.byteSwap = 0, \
.blockSize = 0, \
.doneIfs = 0, \
.reqMode = 0, \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = 0, \
.size = 0, \
.dstInc = 0, \
.srcAddrMode = 0, \
.dstAddrMode = 0, \
.immVal = (value), \
.dstAddr = (uint32_t)(address), \
.linkMode = ldmaLinkModeRel , \
.link = 1, \
.linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
} \
}

DMA descriptor initializer for Immediate WRITE transfer.

Parameters
[in] value Immediate value to write.
[in] address Write address.
[in] linkjmp Address of descriptor to link to, expressed as a signed number of descriptors from "here". 1=one descriptor forward in memory, 0=this descriptor, -1=one descriptor back in memory.

◆ LDMA_DESCRIPTOR_SINGLE_SYNC

#define LDMA_DESCRIPTOR_SINGLE_SYNC ( set,
clr,
matchValue,
matchEnable
)
Value:
{ \
.sync = \
{ \
.structType = ldmaCtrlStructTypeSync , \
.structReq = 1, \
.xferCnt = 0, \
.byteSwap = 0, \
.blockSize = 0, \
.doneIfs = 1, \
.reqMode = 0, \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = 0, \
.size = 0, \
.dstInc = 0, \
.srcAddrMode = 0, \
.dstAddrMode = 0, \
.syncSet = ( set ), \
.syncClr = (clr), \
.matchVal = (matchValue), \
.matchEn = (matchEnable), \
.linkMode = 0, \
.link = 0, \
.linkAddr = 0 \
} \
}

DMA descriptor initializer for SYNC transfer.

Parameters
[in] set Sync pattern bits to set.
[in] clr Sync pattern bits to clear.
[in] matchValue Sync pattern to match.
[in] matchEnable Sync pattern bits to enable for match.

◆ LDMA_DESCRIPTOR_LINKABS_SYNC

#define LDMA_DESCRIPTOR_LINKABS_SYNC ( set,
clr,
matchValue,
matchEnable
)
Value:
{ \
.sync = \
{ \
.structType = ldmaCtrlStructTypeSync , \
.structReq = 1, \
.xferCnt = 0, \
.byteSwap = 0, \
.blockSize = 0, \
.doneIfs = 0, \
.reqMode = 0, \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = 0, \
.size = 0, \
.dstInc = 0, \
.srcAddrMode = 0, \
.dstAddrMode = 0, \
.syncSet = ( set ), \
.syncClr = (clr), \
.matchVal = (matchValue), \
.matchEn = (matchEnable), \
.linkMode = ldmaLinkModeAbs , \
.link = 1, \
.linkAddr = 0 /* Must be set runtime ! */ \
} \
}

DMA descriptor initializer for SYNC transfer.

Link address must be an absolute address.

Note
The linkAddr member of the transfer descriptor is not initialized. linkAddr must be initialized by using the proper bits right-shift to get the correct bits from the absolute address. _LDMA_CH_LINK_LINKADDR_SHIFT should be used for that operation:
desc.linkAddr = ((int32_t)&next_desc) >> _LDMA_CH_LINK_LINKADDR_SHIFT;
The opposite bit shift (left) must be done if linkAddr is read.
Parameters
[in] set Sync pattern bits to set.
[in] clr Sync pattern bits to clear.
[in] matchValue Sync pattern to match.
[in] matchEnable Sync pattern bits to enable for match.

◆ LDMA_DESCRIPTOR_LINKREL_SYNC

#define LDMA_DESCRIPTOR_LINKREL_SYNC ( set,
clr,
matchValue,
matchEnable,
linkjmp
)
Value:
{ \
.sync = \
{ \
.structType = ldmaCtrlStructTypeSync , \
.structReq = 1, \
.xferCnt = 0, \
.byteSwap = 0, \
.blockSize = 0, \
.doneIfs = 0, \
.reqMode = 0, \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = 0, \
.size = 0, \
.dstInc = 0, \
.srcAddrMode = 0, \
.dstAddrMode = 0, \
.syncSet = ( set ), \
.syncClr = (clr), \
.matchVal = (matchValue), \
.matchEn = (matchEnable), \
.linkMode = ldmaLinkModeRel , \
.link = 1, \
.linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
} \
}

DMA descriptor initializer for SYNC transfer.

Parameters
[in] set Sync pattern bits to set.
[in] clr Sync pattern bits to clear.
[in] matchValue Sync pattern to match.
[in] matchEnable Sync pattern bits to enable for match.
[in] linkjmp Address of descriptor to link to, expressed as a signed number of descriptors from "here". 1=one descriptor forward in memory, 0=this descriptor, -1=one descriptor back in memory.

Enumeration Type Documentation

◆ LDMA_CtrlBlockSize_t

enum LDMA_CtrlBlockSize_t

Controls the number of unit data transfers per arbitration cycle, providing a means to balance DMA channels' load on the controller.

Enumerator
ldmaCtrlBlockSizeUnit1

One transfer per arbitration.


ldmaCtrlBlockSizeUnit2

Two transfers per arbitration.


ldmaCtrlBlockSizeUnit3

Three transfers per arbitration.


ldmaCtrlBlockSizeUnit4

Four transfers per arbitration.


ldmaCtrlBlockSizeUnit6

Six transfers per arbitration.


ldmaCtrlBlockSizeUnit8

Eight transfers per arbitration.


ldmaCtrlBlockSizeUnit16

16 transfers per arbitration.


ldmaCtrlBlockSizeUnit32

32 transfers per arbitration.


ldmaCtrlBlockSizeUnit64

64 transfers per arbitration.


ldmaCtrlBlockSizeUnit128

128 transfers per arbitration.


ldmaCtrlBlockSizeUnit256

256 transfers per arbitration.


ldmaCtrlBlockSizeUnit512

512 transfers per arbitration.


ldmaCtrlBlockSizeUnit1024

1024 transfers per arbitration.


ldmaCtrlBlockSizeAll

Lock arbitration during transfer.

◆ LDMA_CtrlStructType_t

enum LDMA_CtrlStructType_t

DMA structure type.

Enumerator
ldmaCtrlStructTypeXfer

TRANSFER transfer type.


ldmaCtrlStructTypeSync

SYNCHRONIZE transfer type.

ldmaCtrlStructTypeWrite

WRITE transfer type.


◆ LDMA_CtrlReqMode_t

enum LDMA_CtrlReqMode_t

DMA transfer block or cycle selector.

Enumerator
ldmaCtrlReqModeBlock

Each DMA request trigger transfer of one block.


ldmaCtrlReqModeAll

A DMA request trigger transfer of a complete cycle.

◆ LDMA_CtrlSrcInc_t

enum LDMA_CtrlSrcInc_t

Source address increment unit size.

Enumerator
ldmaCtrlSrcIncOne

Increment source address by one unit data size.


ldmaCtrlSrcIncTwo

Increment source address by two unit data sizes.


ldmaCtrlSrcIncFour

Increment source address by four unit data sizes.

ldmaCtrlSrcIncNone

Do not increment source address.


◆ LDMA_CtrlSize_t

enum LDMA_CtrlSize_t

DMA transfer unit size.

Enumerator
ldmaCtrlSizeByte

Each unit transfer is a byte.


ldmaCtrlSizeHalf

Each unit transfer is a half-word.

ldmaCtrlSizeWord

Each unit transfer is a word.


◆ LDMA_CtrlDstInc_t

enum LDMA_CtrlDstInc_t

Destination address increment unit size.

Enumerator
ldmaCtrlDstIncOne

Increment destination address by one unit data size.


ldmaCtrlDstIncTwo

Increment destination address by two unit data sizes.


ldmaCtrlDstIncFour

Increment destination address by four unit data sizes.

ldmaCtrlDstIncNone

Do not increment destination address.


◆ LDMA_CtrlSrcAddrMode_t

enum LDMA_CtrlSrcAddrMode_t

Source addressing mode.

Enumerator
ldmaCtrlSrcAddrModeAbs

Address fetched from a linked structure is absolute.


ldmaCtrlSrcAddrModeRel

Address fetched from a linked structure is relative.


◆ LDMA_CtrlDstAddrMode_t

enum LDMA_CtrlDstAddrMode_t

Destination addressing mode.

Enumerator
ldmaCtrlDstAddrModeAbs

Address fetched from a linked structure is absolute.


ldmaCtrlDstAddrModeRel

Address fetched from a linked structure is relative.


◆ LDMA_LinkMode_t

enum LDMA_LinkMode_t

DMA link load address mode.

Enumerator
ldmaLinkModeAbs

Link address is an absolute address value.


ldmaLinkModeRel

Link address is a two's complement relative address.


◆ LDMA_CfgArbSlots_t

enum LDMA_CfgArbSlots_t

Insert extra arbitration slots to increase channel arbitration priority.

Enumerator
ldmaCfgArbSlotsAs1

One arbitration slot selected.


ldmaCfgArbSlotsAs2

Two arbitration slots selected.


ldmaCfgArbSlotsAs4

Four arbitration slots selected.


ldmaCfgArbSlotsAs8

Eight arbitration slots selected.

◆ LDMA_CfgSrcIncSign_t

enum LDMA_CfgSrcIncSign_t

Source address increment sign.

Enumerator
ldmaCfgSrcIncSignPos

Increment source address.

ldmaCfgSrcIncSignNeg

Decrement source address.

◆ LDMA_CfgDstIncSign_t

enum LDMA_CfgDstIncSign_t

Destination address increment sign.

Enumerator
ldmaCfgDstIncSignPos

Increment destination address.

ldmaCfgDstIncSignNeg

Decrement destination address.

◆ LDMA_PeripheralSignal_t

enum LDMA_PeripheralSignal_t

Peripherals that can trigger LDMA transfers.

Enumerator
ldmaPeripheralSignal_NONE

No peripheral selected for DMA triggering.

ldmaPeripheralSignal_ADC0_SCAN

Trigger on ADC0_SCAN.

ldmaPeripheralSignal_ADC0_SINGLE

Trigger on ADC0_SINGLE.

ldmaPeripheralSignal_ADC1_SCAN

Trigger on ADC1_SCAN.

ldmaPeripheralSignal_ADC1_SINGLE

Trigger on ADC1_SINGLE.

ldmaPeripheralSignal_CRYPTO0_DATA0RD

Trigger on CRYPTO0_DATA0RD.

ldmaPeripheralSignal_CRYPTO0_DATA0WR

Trigger on CRYPTO0_DATA0WR.

ldmaPeripheralSignal_CRYPTO0_DATA0XWR

Trigger on CRYPTO0_DATA0XWR.

ldmaPeripheralSignal_CRYPTO0_DATA1RD

Trigger on CRYPTO0_DATA1RD.

ldmaPeripheralSignal_CRYPTO0_DATA1WR

Trigger on CRYPTO0_DATA1WR.

ldmaPeripheralSignal_CSEN_BSLN

Trigger on CSEN_BSLN.

ldmaPeripheralSignal_CSEN_DATA

Trigger on CSEN_DATA.

ldmaPeripheralSignal_EBI_PXL0EMPTY

Trigger on EBI_PXL0EMPTY.

ldmaPeripheralSignal_EBI_PXL1EMPTY

Trigger on EBI_PXL1EMPTY.

ldmaPeripheralSignal_EBI_PXLFULL

Trigger on EBI_PXLFULL.

ldmaPeripheralSignal_EBI_DDEMPTY

Trigger on EBI_DDEMPTY.

ldmaPeripheralSignal_EBI_VSYNC

Trigger on EBI_VSYNC.

ldmaPeripheralSignal_EBI_HSYNC

Trigger on EBI_HSYNC.

ldmaPeripheralSignal_I2C0_RXDATAV

Trigger on I2C0_RXDATAV.

ldmaPeripheralSignal_I2C0_TXBL

Trigger on I2C0_TXBL.

ldmaPeripheralSignal_I2C1_RXDATAV

Trigger on I2C1_RXDATAV.

ldmaPeripheralSignal_I2C1_TXBL

Trigger on I2C1_TXBL.

ldmaPeripheralSignal_I2C2_RXDATAV

Trigger on I2C2_RXDATAV.

ldmaPeripheralSignal_I2C2_TXBL

Trigger on I2C2_TXBL.

ldmaPeripheralSignal_LESENSE_BUFDATAV

Trigger on LESENSE_BUFDATAV.

ldmaPeripheralSignal_LEUART0_RXDATAV

Trigger on LEUART0_RXDATAV.

ldmaPeripheralSignal_LEUART0_TXBL

Trigger on LEUART0_TXBL.

ldmaPeripheralSignal_LEUART0_TXEMPTY

Trigger on LEUART0_TXEMPTY.

ldmaPeripheralSignal_LEUART1_RXDATAV

Trigger on LEUART1_RXDATAV.

ldmaPeripheralSignal_LEUART1_TXBL

Trigger on LEUART1_TXBL.

ldmaPeripheralSignal_LEUART1_TXEMPTY

Trigger on LEUART1_TXEMPTY.

ldmaPeripheralSignal_MSC_WDATA

Trigger on MSC_WDATA.

ldmaPeripheralSignal_PRS_REQ0

Trigger on PRS_REQ0.

ldmaPeripheralSignal_PRS_REQ1

Trigger on PRS_REQ1.

ldmaPeripheralSignal_TIMER0_CC0

Trigger on TIMER0_CC0.

ldmaPeripheralSignal_TIMER0_CC1

Trigger on TIMER0_CC1.

ldmaPeripheralSignal_TIMER0_CC2

Trigger on TIMER0_CC2.

ldmaPeripheralSignal_TIMER0_UFOF

Trigger on TIMER0_UFOF.

ldmaPeripheralSignal_TIMER1_CC0

Trigger on TIMER1_CC0.

ldmaPeripheralSignal_TIMER1_CC1

Trigger on TIMER1_CC1.

ldmaPeripheralSignal_TIMER1_CC2

Trigger on TIMER1_CC2.

ldmaPeripheralSignal_TIMER1_CC3

Trigger on TIMER1_CC3.

ldmaPeripheralSignal_TIMER1_UFOF

Trigger on TIMER1_UFOF.

ldmaPeripheralSignal_TIMER2_CC0

Trigger on TIMER2_CC0.

ldmaPeripheralSignal_TIMER2_CC1

Trigger on TIMER2_CC1.

ldmaPeripheralSignal_TIMER2_CC2

Trigger on TIMER2_CC2.

ldmaPeripheralSignal_TIMER2_UFOF

Trigger on TIMER2_UFOF.

ldmaPeripheralSignal_TIMER3_CC0

Trigger on TIMER3_CC0.

ldmaPeripheralSignal_TIMER3_CC1

Trigger on TIMER3_CC1.

ldmaPeripheralSignal_TIMER3_CC2

Trigger on TIMER3_CC2.

ldmaPeripheralSignal_TIMER3_UFOF

Trigger on TIMER3_UFOF.

ldmaPeripheralSignal_TIMER4_CC0

Trigger on TIMER4_CC0.

ldmaPeripheralSignal_TIMER4_CC1

Trigger on TIMER4_CC1.

ldmaPeripheralSignal_TIMER4_CC2

Trigger on TIMER4_CC2.

ldmaPeripheralSignal_TIMER4_UFOF

Trigger on TIMER4_UFOF.

ldmaPeripheralSignal_TIMER5_CC0

Trigger on TIMER5_CC0.

ldmaPeripheralSignal_TIMER5_CC1

Trigger on TIMER5_CC1.

ldmaPeripheralSignal_TIMER5_CC2

Trigger on TIMER5_CC2.

ldmaPeripheralSignal_TIMER5_UFOF

Trigger on TIMER5_UFOF.

ldmaPeripheralSignal_TIMER6_CC0

Trigger on TIMER6_CC0.

ldmaPeripheralSignal_TIMER6_CC1

Trigger on TIMER6_CC1.

ldmaPeripheralSignal_TIMER6_CC2

Trigger on TIMER6_CC2.

ldmaPeripheralSignal_TIMER6_UFOF

Trigger on TIMER6_UFOF.

ldmaPeripheralSignal_UART0_RXDATAV

Trigger on UART0_RXDATAV.

ldmaPeripheralSignal_UART0_TXBL

Trigger on UART0_TXBL.

ldmaPeripheralSignal_UART0_TXEMPTY

Trigger on UART0_TXEMPTY.

ldmaPeripheralSignal_UART1_RXDATAV

Trigger on UART1_RXDATAV.

ldmaPeripheralSignal_UART1_TXBL

Trigger on UART1_TXBL.

ldmaPeripheralSignal_UART1_TXEMPTY

Trigger on UART1_TXEMPTY.

ldmaPeripheralSignal_USART0_RXDATAV

Trigger on USART0_RXDATAV.

ldmaPeripheralSignal_USART0_TXBL

Trigger on USART0_TXBL.

ldmaPeripheralSignal_USART0_TXEMPTY

Trigger on USART0_TXEMPTY.

ldmaPeripheralSignal_USART1_RXDATAV

Trigger on USART1_RXDATAV.

ldmaPeripheralSignal_USART1_RXDATAVRIGHT

Trigger on USART1_RXDATAVRIGHT.

ldmaPeripheralSignal_USART1_TXBL

Trigger on USART1_TXBL.

ldmaPeripheralSignal_USART1_TXBLRIGHT

Trigger on USART1_TXBLRIGHT.

ldmaPeripheralSignal_USART1_TXEMPTY

Trigger on USART1_TXEMPTY.

ldmaPeripheralSignal_USART2_RXDATAV

Trigger on USART2_RXDATAV.

ldmaPeripheralSignal_USART2_TXBL

Trigger on USART2_TXBL.

ldmaPeripheralSignal_USART2_TXEMPTY

Trigger on USART2_TXEMPTY.

ldmaPeripheralSignal_USART3_RXDATAV

Trigger on USART3_RXDATAV.

ldmaPeripheralSignal_USART3_RXDATAVRIGHT

Trigger on USART3_RXDATAVRIGHT.

ldmaPeripheralSignal_USART3_TXBL

Trigger on USART3_TXBL.

ldmaPeripheralSignal_USART3_TXBLRIGHT

Trigger on USART3_TXBLRIGHT.

ldmaPeripheralSignal_USART3_TXEMPTY

Trigger on USART3_TXEMPTY.

ldmaPeripheralSignal_USART4_RXDATAV

Trigger on USART4_RXDATAV.

ldmaPeripheralSignal_USART4_RXDATAVRIGHT

Trigger on USART4_RXDATAVRIGHT.

ldmaPeripheralSignal_USART4_TXBL

Trigger on USART4_TXBL.

ldmaPeripheralSignal_USART4_TXBLRIGHT

Trigger on USART4_TXBLRIGHT.

ldmaPeripheralSignal_USART4_TXEMPTY

Trigger on USART4_TXEMPTY.

ldmaPeripheralSignal_USART5_RXDATAV

Trigger on USART5_RXDATAV.

ldmaPeripheralSignal_USART5_TXBL

Trigger on USART5_TXBL.

ldmaPeripheralSignal_USART5_TXEMPTY

Trigger on USART5_TXEMPTY.

ldmaPeripheralSignal_VDAC0_CH0

Trigger on VDAC0_CH0.

ldmaPeripheralSignal_VDAC0_CH1

Trigger on VDAC0_CH1.

ldmaPeripheralSignal_WTIMER0_CC0

Trigger on WTIMER0_CC0.

ldmaPeripheralSignal_WTIMER0_CC1

Trigger on WTIMER0_CC1.

ldmaPeripheralSignal_WTIMER0_CC2

Trigger on WTIMER0_CC2.

ldmaPeripheralSignal_WTIMER0_UFOF

Trigger on WTIMER0_UFOF.

ldmaPeripheralSignal_WTIMER1_CC0

Trigger on WTIMER1_CC0.

ldmaPeripheralSignal_WTIMER1_CC1

Trigger on WTIMER1_CC1.

ldmaPeripheralSignal_WTIMER1_CC2

Trigger on WTIMER1_CC2.

ldmaPeripheralSignal_WTIMER1_CC3

Trigger on WTIMER1_CC3.

ldmaPeripheralSignal_WTIMER1_UFOF

Trigger on WTIMER1_UFOF.

ldmaPeripheralSignal_WTIMER2_CC0

Trigger on WTIMER2_CC0.

ldmaPeripheralSignal_WTIMER2_CC1

Trigger on WTIMER2_CC1.

ldmaPeripheralSignal_WTIMER2_CC2

Trigger on WTIMER2_CC2.

ldmaPeripheralSignal_WTIMER2_UFOF

Trigger on WTIMER2_UFOF.

ldmaPeripheralSignal_WTIMER3_CC0

Trigger on WTIMER3_CC0.

ldmaPeripheralSignal_WTIMER3_CC1

Trigger on WTIMER3_CC1.

ldmaPeripheralSignal_WTIMER3_CC2

Trigger on WTIMER3_CC2.

ldmaPeripheralSignal_WTIMER3_UFOF

Trigger on WTIMER3_UFOF.