SMU - Security Management Unit
Description
Security Management Unit (SMU) Peripheral API.
SMU forms the control and status/reporting component of bus-level security in EFM32/EFR32 devices.
Peripheral-level protection is provided via the Peripheral Protection Unit (PPU). PPU provides hardware access barrier to any peripheral that is configured to be protected. When an attempt is made to access a peripheral without the required privilege/security level, PPU detects the fault and intercepts the access. No write or read of the peripheral register space occurs, and an all-zero value is returned if the access is a read.
Usage example
// SMU is always clocked, so no call to CMU_ClockEnable() is necessary
// Initialize SMU to prevent access to CMU, EMU, SMU and GPIO
SMU_Init_TypeDef
init =
SMU_INIT_DEFAULT
;
SMU_Init
(&init);
Data Structures |
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| struct | SMU_PrivilegedAccess_TypeDef |
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SMU peripheral privileged access enablers.
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| struct | SMU_Init_TypeDef |
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SMU initialization structure.
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Functions |
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| void | SMU_EnablePPU (bool enable) |
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Enable or disable PPU of SMU.
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| void | SMU_Init (const SMU_Init_TypeDef *init) |
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Initialize PPU of SMU.
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| void | SMU_SetPrivilegedAccess ( SMU_Peripheral_TypeDef peripheral, bool privileged) |
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Change access settings for a peripheral.
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| SMU_Peripheral_TypeDef | SMU_GetFaultingPeripheral (void) |
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Get the ID of the peripheral that caused an access fault.
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| void | SMU_IntClear (uint32_t flags) |
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Clear one or more pending SMU interrupts.
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| void | SMU_IntDisable (uint32_t flags) |
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Disable one or more SMU interrupts.
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| void | SMU_IntEnable (uint32_t flags) |
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Enable one or more SMU interrupts.
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| uint32_t | SMU_IntGet (void) |
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Get pending SMU interrupts.
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| uint32_t | SMU_IntGetEnabled (void) |
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Get enabled and pending SMU interrupt flags.
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| void | SMU_IntSet (uint32_t flags) |
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Set one or more pending SMU interrupts from SW.
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Macros |
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| #define | SMU_INIT_DEFAULT |
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Default SMU initialization structure settings.
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Enumerations |
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| enum |
SMU_Peripheral_TypeDef
{
smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, smuPeripheralACMP3 = _SMU_PPUPATD0_ACMP3_SHIFT, smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, smuPeripheralI2C2 = _SMU_PPUPATD0_I2C2_SHIFT, smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, smuPeripheralTIMER4 = 32 + _SMU_PPUPATD1_TIMER4_SHIFT, smuPeripheralTIMER5 = 32 + _SMU_PPUPATD1_TIMER5_SHIFT, smuPeripheralTIMER6 = 32 + _SMU_PPUPATD1_TIMER6_SHIFT, smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, smuPeripheralUSART5 = 32 + _SMU_PPUPATD1_USART5_SHIFT, smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, smuPeripheralWTIMER2 = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT, smuPeripheralWTIMER3 = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT, smuPeripheralEnd } |
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SMU peripheral identifiers.
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Function Documentation
◆ SMU_EnablePPU()
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inline |
Enable or disable PPU of SMU.
- Parameters
-
[in] enableSet to true to enable PPU; set to false otherwise.
◆ SMU_Init()
|
inline |
Initialize PPU of SMU.
- Parameters
-
[in] initPointer to initialization structure that defines which peripherals should only be accessed from privileged mode, and if PPU should be enabled.
◆ SMU_SetPrivilegedAccess()
|
inline |
Change access settings for a peripheral.
Set to limit access of a peripheral from privileged mode.
- Parameters
-
[in] peripheralID of the peripheral to change access settings for. [in] privilegedSet to true if the peripheral should only be accessed from privileged mode; set to false otherwise.
◆ SMU_GetFaultingPeripheral()
|
inline |
Get the ID of the peripheral that caused an access fault.
- Note
- The return value is only valid if SMU_IF_PPUPRIV interrupt flag is set.
- Returns
- ID of the peripheral that caused an access fault.
◆ SMU_IntClear()
|
inline |
Clear one or more pending SMU interrupts.
- Parameters
-
[in] flagsBitwise logic OR of SMU interrupt sources to clear.
◆ SMU_IntDisable()
|
inline |
Disable one or more SMU interrupts.
- Parameters
-
[in] flagsSMU interrupt sources to disable.
◆ SMU_IntEnable()
|
inline |
Enable one or more SMU interrupts.
- Note
- Depending on the use, a pending interrupt may already be set prior to enabling the interrupt. To ignore a pending interrupt, consider using SMU_IntClear() prior to enabling the interrupt.
- Parameters
-
[in] flagsSMU interrupt sources to enable.
◆ SMU_IntGet()
|
inline |
Get pending SMU interrupts.
- Returns
- SMU interrupt sources pending.
◆ SMU_IntGetEnabled()
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inline |
Get enabled and pending SMU interrupt flags.
Useful for handling more interrupt sources in the same interrupt handler.
- Note
- Interrupt flags are not cleared by this function.
- Returns
-
Pending and enabled SMU interrupt sources. The return value is the bitwise AND combination of
- the OR combination of enabled interrupt sources in SMU_IEN register and
- the OR combination of valid interrupt flags in SMU_IF register.
◆ SMU_IntSet()
|
inline |
Set one or more pending SMU interrupts from SW.
- Parameters
-
[in] flagsSMU interrupt sources to set to pending.
Macro Definition Documentation
◆ SMU_INIT_DEFAULT
| #define SMU_INIT_DEFAULT |
Value:
{ \
{ { 0 } },
/* No peripherals access protected. */
\
true
/* Enable SMU.*/
\
}
Default SMU initialization structure settings.
Enumeration Type Documentation
◆ SMU_Peripheral_TypeDef
SMU peripheral identifiers.