CORE - Core Interrupt

Description

Core interrupt handling API.


Introduction

CORE interrupt API provides a simple and safe means to disable and enable interrupts to protect sections of code.

This is often referred to as "critical sections". This module provides support for three types of critical sections, each with different interrupt blocking capabilities.

  • CRITICAL section: Inside a critical section, all interrupts are disabled (except for fault handlers). The PRIMASK register is always used for interrupt disable/enable.
  • ATOMIC section: This type of section is configurable and the default method is to use PRIMASK. With BASEPRI configuration, interrupts with priority equal to or lower than a given configurable level are disabled. The interrupt disable priority level is defined at compile time. The BASEPRI register is not available for all architectures.
  • NVIC mask section: Disable NVIC (external interrupts) on an individual manner.

em_core also has an API for manipulating RAM-based interrupt vector tables.


Compile-time Configuration

The following #defines are used to configure em_core:

// The interrupt priority level used inside ATOMIC sections.
#define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3
// A method used for interrupt disable/enable within ATOMIC sections.
#define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK

If the default values do not support your needs, they can be overridden by supplying -D compiler flags on the compiler command line or by collecting all macro redefinitions in a file named emlib_config.h and then supplying -DEMLIB_USER_CONFIG on a compiler command line.

Note
The default emlib configuration for ATOMIC section interrupt disable method is using PRIMASK, i.e., ATOMIC sections are implemented as CRITICAL sections.
Due to architectural limitations Cortex-M0+ devices do not support ATOMIC type critical sections using the BASEPRI register. On M0+ devices ATOMIC section helper macros are available but they are implemented as CRITICAL sections using PRIMASK register.


Macro API

The primary em_core API is the macro API. Macro API will map to correct CORE functions according to the selected CORE_ATOMIC_METHOD and similar configurations (the full CORE API is of course also available). The most useful macros are as follows:

CORE_DECLARE_IRQ_STATE
CORE_ENTER_ATOMIC()
CORE_EXIT_ATOMIC()
Used together to implement an ATOMIC section.

{
CORE_DECLARE_IRQ_STATE ; // Storage for saving IRQ state prior to
// atomic section entry.
CORE_ENTER_ATOMIC (); // Enter atomic section.
...
... your code goes here ...
...
CORE_EXIT_ATOMIC (); // Exit atomic section, IRQ state is restored.
}


CORE_ATOMIC_SECTION(yourcode)
A concatenation of all three macros above.

{
CORE_ATOMIC_SECTION (
...
... your code goes here ...
...
)
}


CORE_DECLARE_IRQ_STATE
CORE_ENTER_CRITICAL()
CORE_EXIT_CRITICAL()