MSC - Memory System Controller

Description

Memory System Controller API.

Contains functions to control the MSC, primarily the Flash. Users can perform Flash memory write and erase operations, as well as optimization of the CPU instruction fetch interface for the application. Available instruction fetch features depends on the MCU or SoC family, but features such as instruction pre-fetch, cache, and configurable branch prediction are typically available.

Note
Flash wait-state configuration is handled by CMU - Clock Management Unit . When core clock configuration is changed by a call to functions such as CMU_ClockSelectSet() or CMU_HFRCOBandSet() , then Flash wait-state configuration is also updated.

MSC resets into a safe state. To initialize the instruction interface to recommended settings:

Note
The optimal configuration is highly application dependent. Performance benchmarking is supported by most families. See MSC_StartCacheMeasurement() and MSC_GetCacheMeasurement() for more details.
The flash write and erase runs from RAM on the EFM32G devices. On all other devices the flash write and erase functions run from flash.
Flash erase may add ms of delay to interrupt latency if executing from Flash.

Flash write and erase operations are supported by MSC_WriteWord() , MSC_ErasePage() , and MSC_MassErase() . Mass erase is supported for MCU and SoC families with larger Flash sizes.

Note
MSC_Init() must be called prior to any Flash write or erase operation.

The following steps are necessary to perform a page erase and write:

uint32_t * userDataPage = (uint32_t *) USERDATA_BASE;
uint32_t userData[] = {
0x01020304,
0x05060708
};
MSC_ErasePage (userDataPage);
MSC_WriteWord (userDataPage, userData, sizeof (userData));

Data Structures

struct MSC_ExecConfig_TypeDef
Code execution configuration.

Functions

void MSC_IntClear (uint32_t flags)
Clear one or more pending MSC interrupts.
void MSC_IntDisable (uint32_t flags)
Disable one or more MSC interrupts.
void MSC_IntEnable (uint32_t flags)
Enable one or more MSC interrupts.